llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX6 %s
   3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
   6
   7 ---
   8
   9 name: trunc_sgpr_v2s32_to_v2s16
  10 legalized:       true
  11 regBankSelected: true
  12
  13 body: |
  14   bb.0:
  15     liveins: $sgpr0_sgpr1
  16     ; GFX6-LABEL: name: trunc_sgpr_v2s32_to_v2s16
  17     ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  18     ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  19     ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  20     ; GFX6: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 16, implicit-def $scc
  21     ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  22     ; GFX6: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
  23     ; GFX6: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_LSHL_B32_]], [[S_AND_B32_]], implicit-def $scc
  24     ; GFX6: S_ENDPGM 0, implicit [[S_OR_B32_]]
  25     ; GFX8-LABEL: name: trunc_sgpr_v2s32_to_v2s16
  26     ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  27     ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  28     ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  29     ; GFX8: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 16, implicit-def $scc
  30     ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  31     ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
  32     ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_LSHL_B32_]], [[S_AND_B32_]], implicit-def $scc
  33     ; GFX8: S_ENDPGM 0, implicit [[S_OR_B32_]]
  34     %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
  35     %1:sgpr(<2 x s16>) = G_TRUNC %0
  36     S_ENDPGM 0, implicit %1
  37 ...
  38
  39 ---
  40
  41 name: trunc_vgpr_v2s32_to_v2s16
  42 legalized:       true
  43 regBankSelected: true
  44
  45 body: |
  46   bb.0:
  47     liveins: $vgpr0_vgpr1
  48     ; GFX6-LABEL: name: trunc_vgpr_v2s32_to_v2s16
  49     ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  50     ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
  51     ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
  52     ; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, [[COPY2]], implicit $exec
  53     ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec
  54     ; GFX6: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
  55     ; GFX6: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_LSHLREV_B32_e64_]], [[V_AND_B32_e64_]], implicit $exec
  56     ; GFX6: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
  57     ; GFX8-LABEL: name: trunc_vgpr_v2s32_to_v2s16
  58     ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  59     ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
  60     ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
  61     ; GFX8: [[V_MOV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_MOV_B32_sdwa 0, [[COPY2]], 0, 5, 2, 4, implicit $exec, implicit [[COPY1]](tied-def 0)
  62     ; GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_sdwa]]
  63     %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
  64     %1:vgpr(<2 x s16>) = G_TRUNC %0
  65     S_ENDPGM 0, implicit %1
  66 ...