1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
4 # The only simple instruction selection for G_SBFX/G_UBFX are the 64-bit
5 # vector versions. All other versions are expanded during register bank
12 tracksRegLiveness: true
16 ; WAVE64-LABEL: name: ubfx_s32_vii
17 ; WAVE64: liveins: $vgpr0
18 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19 ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
20 ; WAVE64: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
21 ; WAVE64: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec
22 ; WAVE64: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
23 ; WAVE32-LABEL: name: ubfx_s32_vii
24 ; WAVE32: liveins: $vgpr0
25 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
26 ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
27 ; WAVE32: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
28 ; WAVE32: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec
29 ; WAVE32: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
30 ; CHECK-LABEL: name: ubfx_s32_vii
31 ; CHECK: liveins: $vgpr0
32 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
33 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
34 ; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
35 ; CHECK: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec
36 ; CHECK: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
37 %0:vgpr(s32) = COPY $vgpr0
38 %1:vgpr(s32) = G_CONSTANT i32 2
39 %2:vgpr(s32) = G_CONSTANT i32 10
40 %3:vgpr(s32) = G_UBFX %0, %1(s32), %2
41 S_ENDPGM 0, implicit %3
48 tracksRegLiveness: true
51 liveins: $vgpr0, $vgpr1, $vgpr2
52 ; WAVE64-LABEL: name: ubfx_s32_vvv
53 ; WAVE64: liveins: $vgpr0, $vgpr1, $vgpr2
54 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
55 ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
56 ; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
57 ; WAVE64: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
58 ; WAVE64: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
59 ; WAVE32-LABEL: name: ubfx_s32_vvv
60 ; WAVE32: liveins: $vgpr0, $vgpr1, $vgpr2
61 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
62 ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
63 ; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
64 ; WAVE32: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
65 ; WAVE32: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
66 ; CHECK-LABEL: name: ubfx_s32_vvv
67 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
68 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
69 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
70 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
71 ; CHECK: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
72 ; CHECK: S_ENDPGM 0, implicit [[V_BFE_U32_e64_]]
73 %0:vgpr(s32) = COPY $vgpr0
74 %1:vgpr(s32) = COPY $vgpr1
75 %2:vgpr(s32) = COPY $vgpr2
76 %3:vgpr(s32) = G_UBFX %0, %1(s32), %2
77 S_ENDPGM 0, implicit %3