llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE64 %s
   3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE64 %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE64 %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
   6
   7 ---
   8 name: usube_s32_s1_sss
   9 legalized: true
  10 regBankSelected: true
  11
  12 body: |
  13   bb.0:
  14     liveins: $sgpr0, $sgpr1, $sgpr2
  15
  16     ; WAVE64-LABEL: name: usube_s32_s1_sss
  17     ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  18     ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  19     ; WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  20     ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  21     ; WAVE64: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
  22     ; WAVE64: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
  23     ; WAVE64: $scc = COPY [[COPY3]]
  24     ; WAVE64: [[S_SUBB_U32_:%[0-9]+]]:sreg_32 = S_SUBB_U32 [[COPY]], [[COPY1]], implicit-def $scc, implicit $scc
  25     ; WAVE64: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
  26     ; WAVE64: $scc = COPY [[COPY4]]
  27     ; WAVE64: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
  28     ; WAVE64: S_ENDPGM 0, implicit [[S_SUBB_U32_]], implicit [[S_CSELECT_B32_]]
  29     ; WAVE32-LABEL: name: usube_s32_s1_sss
  30     ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  31     ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  32     ; WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
  33     ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  34     ; WAVE32: S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
  35     ; WAVE32: [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
  36     ; WAVE32: $scc = COPY [[COPY3]]
  37     ; WAVE32: [[S_SUBB_U32_:%[0-9]+]]:sreg_32 = S_SUBB_U32 [[COPY]], [[COPY1]], implicit-def $scc, implicit $scc
  38     ; WAVE32: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
  39     ; WAVE32: $scc = COPY [[COPY4]]
  40     ; WAVE32: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
  41     ; WAVE32: S_ENDPGM 0, implicit [[S_SUBB_U32_]], implicit [[S_CSELECT_B32_]]
  42     %0:sgpr(s32) = COPY $sgpr0
  43     %1:sgpr(s32) = COPY $sgpr1
  44     %2:sgpr(s32) = COPY $sgpr2
  45     %3:sgpr(s32) = G_CONSTANT i32 0
  46     %4:sgpr(s32) = G_ICMP intpred(eq), %2, %3
  47     %5:sgpr(s32), %6:sgpr(s32) = G_USUBE %0, %1, %4
  48     %7:sgpr(s32) = G_SELECT %6, %0, %1
  49     S_ENDPGM 0, implicit %5, implicit %7
  50 ...
  51
  52 ---
  53 name: usube_s32_s1_vvv
  54 legalized: true
  55 regBankSelected: true
  56
  57 body: |
  58   bb.0:
  59     liveins: $vgpr0, $vgpr1, $vgpr2
  60
  61     ; WAVE64-LABEL: name: usube_s32_s1_vvv
  62     ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  63     ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  64     ; WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  65     ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  66     ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
  67     ; WAVE64: [[V_SUBB_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUBB_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_SUBB_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
  68     ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_SUBB_U32_e64_1]], implicit $exec
  69     ; WAVE64: S_ENDPGM 0, implicit [[V_SUBB_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
  70     ; WAVE32-LABEL: name: usube_s32_s1_vvv
  71     ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  72     ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  73     ; WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  74     ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  75     ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec
  76     ; WAVE32: [[V_SUBB_U32_e64_:%[0-9]+]]:vgpr_32, [[V_SUBB_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_SUBB_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec
  77     ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_SUBB_U32_e64_1]], implicit $exec
  78     ; WAVE32: S_ENDPGM 0, implicit [[V_SUBB_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]
  79     %0:vgpr(s32) = COPY $vgpr0
  80     %1:vgpr(s32) = COPY $vgpr1
  81     %2:vgpr(s32) = COPY $vgpr2
  82     %3:vgpr(s32) = G_CONSTANT i32 0
  83     %4:vcc(s1) = G_ICMP intpred(eq), %2, %3
  84     %5:vgpr(s32), %6:vcc(s1) = G_USUBE %0, %1, %4
  85     %7:vgpr(s32) = G_SELECT %6, %0, %1
  86     S_ENDPGM 0, implicit %5, implicit %7
  87 ...