llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
   3
   4 ---
   5
   6 name: zext_sgpr_s1_to_sgpr_s16
   7 legalized:       true
   8 regBankSelected: true
   9 body: |
  10   bb.0:
  11     liveins: $sgpr0
  12
  13     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s16
  14     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  15     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
  16     ; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_AND_B32_]]
  17     ; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
  18     %0:sgpr(s32) = COPY $sgpr0
  19     %1:sgpr(s1) = G_TRUNC %0
  20     %2:sgpr(s16) = G_ZEXT %1
  21     %3:sgpr(s32) = G_SEXT %2
  22     $sgpr0 = COPY %3
  23 ...
  24
  25 ---
  26
  27 name: zext_sgpr_s1_to_sgpr_s32
  28 legalized:       true
  29 regBankSelected: true
  30 body: |
  31   bb.0:
  32     liveins: $sgpr0
  33
  34     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
  35     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  36     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
  37     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  38     %0:sgpr(s32) = COPY $sgpr0
  39     %1:sgpr(s1) = G_TRUNC %0
  40     %2:sgpr(s32) = G_ZEXT %1
  41     $sgpr0 = COPY %2
  42 ...
  43
  44 ---
  45
  46 name: zext_sgpr_s1_to_sgpr_s64
  47 legalized:       true
  48 regBankSelected: true
  49 body: |
  50   bb.0:
  51     liveins: $sgpr0
  52
  53     ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
  54     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  55     ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  56     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
  57     ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
  58     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
  59     %0:sgpr(s32) = COPY $sgpr0
  60     %1:sgpr(s1) = G_TRUNC %0
  61     %2:sgpr(s64) = G_ZEXT %1
  62     $sgpr0_sgpr1 = COPY %2
  63 ...
  64
  65 ---
  66
  67 name: zext_sgpr_s16_to_sgpr_s32
  68 legalized:       true
  69 regBankSelected: true
  70 body: |
  71   bb.0:
  72     liveins: $sgpr0
  73
  74     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
  75     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  76     ; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
  77     ; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
  78     %0:sgpr(s32) = COPY $sgpr0
  79     %1:sgpr(s16) = G_TRUNC %0
  80     %2:sgpr(s32) = G_ZEXT %1
  81     $sgpr0 = COPY %2
  82
  83 ...
  84
  85 ---
  86
  87 name: zext_sgpr_s16_to_sgpr_s64
  88 legalized:       true
  89 regBankSelected: true
  90 body: |
  91   bb.0:
  92     liveins: $sgpr0
  93
  94     ; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
  95     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  96     ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  97     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
  98     ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
  99     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
 100     %0:sgpr(s32) = COPY $sgpr0
 101     %1:sgpr(s16) = G_TRUNC %0
 102     %2:sgpr(s64) = G_ZEXT %1
 103     $sgpr0_sgpr1 = COPY %2
 104
 105 ...
 106
 107 ---
 108
 109 name: zext_sgpr_s32_to_sgpr_s64
 110 legalized:       true
 111 regBankSelected: true
 112 body: |
 113   bb.0:
 114     liveins: $sgpr0
 115
 116     ; GCN-LABEL: name: zext_sgpr_s32_to_sgpr_s64
 117     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 118     ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
 119     ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
 120     ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 2097152, implicit-def $scc
 121     ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
 122     %0:sgpr(s32) = COPY $sgpr0
 123     %1:sgpr(s64) = G_ZEXT %0
 124     $sgpr0_sgpr1 = COPY %1
 125
 126 ...
 127
 128 # ---
 129
 130 # name: zext_vcc_s1_to_vgpr_s32
 131 # legalized:       true
 132 # regBankSelected: true
 133 # body: |
 134 #   bb.0:
 135 #     liveins: $vgpr0
 136
 137 #     %0:vgpr(s32) = COPY $vgpr0
 138 #     %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
 139 #     %2:vgpr(s32) = G_ZEXT %1
 140 #     $vgpr0 = COPY %2
 141 # ...
 142
 143 ---
 144
 145 name: zext_vgpr_s1_to_vgpr_s16
 146 legalized:       true
 147 regBankSelected: true
 148 body: |
 149   bb.0:
 150     liveins: $vgpr0
 151
 152     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s16
 153     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 154     ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 155     ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], 0, 16, implicit $exec
 156     ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
 157     %0:vgpr(s32) = COPY $vgpr0
 158     %1:vgpr(s1) = G_TRUNC %0
 159     %2:vgpr(s16) = G_ZEXT %1
 160     %3:vgpr(s32) = G_SEXT %2
 161     $vgpr0 = COPY %3
 162 ...
 163
 164 ---
 165
 166 name: zext_vgpr_s1_to_vgpr_s32
 167 legalized:       true
 168 regBankSelected: true
 169 body: |
 170   bb.0:
 171     liveins: $vgpr0
 172
 173     ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
 174     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 175     ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 176     ; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e32_]]
 177     %0:vgpr(s32) = COPY $vgpr0
 178     %1:vgpr(s1) = G_TRUNC %0
 179     %2:vgpr(s32) = G_ZEXT %1
 180     $vgpr0 = COPY %2
 181 ...
 182
 183 ---
 184
 185 name: zext_vgpr_s16_to_vgpr_s32
 186 legalized:       true
 187 regBankSelected: true
 188 body: |
 189   bb.0:
 190     liveins: $vgpr0
 191
 192     ; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
 193     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 194     ; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
 195     ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
 196     %0:vgpr(s32) = COPY $vgpr0
 197     %1:vgpr(s16) = G_TRUNC %0
 198     %2:vgpr(s32) = G_ZEXT %1
 199     $vgpr0 = COPY %2
 200
 201 ...
 202
 203 ---
 204
 205 name: zext_sgpr_reg_class_s1_to_sgpr_s32
 206 legalized:       true
 207 regBankSelected: true
 208 body: |
 209   bb.0:
 210     liveins: $sgpr0
 211
 212     ; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
 213     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 214     ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
 215     ; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 216     %0:sgpr(s32) = COPY $sgpr0
 217     %1:sreg_32(s1) = G_TRUNC %0
 218     %2:sgpr(s32) = G_ZEXT %1
 219     $sgpr0 = COPY %2
 220 ...