| blob | 9e2a29eec743954a3136ad04267c81e23e367e62 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -march=amdgcn -mcpu=verde -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX6 %s
3 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s
4 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX789 %s
5 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GFX10 %s
7 ; FIXME: This test has a DAG duplicate
9 ; Immediate values:
10 ; (mode register ID = 1) | (Offset << 6) | ((Width - 1) << 11)
11 ; Offset: fp_round = 0, fp_denorm = 4, dx10_clamp = 8, ieee_mode = 9
14 ; Set FP32 fp_round to round to zero
15 define amdgpu_kernel void @test_setreg_f32_round_mode_rtz() {
16 ; GFX6-LABEL: test_setreg_f32_round_mode_rtz:
17 ; GFX6: ; %bb.0:
18 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00,0x00,0x00]
19 ; GFX6-NEXT: ;;#ASMSTART
20 ; GFX6-NEXT: ;;#ASMEND
21 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
22 ;
23 ; GFX789-LABEL: test_setreg_f32_round_mode_rtz:
24 ; GFX789: ; %bb.0:
25 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x00,0xba,0x03,0x00,0x00,0x00]
26 ; GFX789-NEXT: ;;#ASMSTART
27 ; GFX789-NEXT: ;;#ASMEND
28 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
29 ;
30 ; GFX10-LABEL: test_setreg_f32_round_mode_rtz:
31 ; GFX10: ; %bb.0:
32 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3 ; encoding: [0x01,0x08,0x80,0xba,0x03,0x00,0x00,0x00]
33 ; GFX10-NEXT: ;;#ASMSTART
34 ; GFX10-NEXT: ;;#ASMEND
35 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
36 call void @llvm.amdgcn.s.setreg(i32 2049, i32 3)
37 call void asm sideeffect "", ""()
38 ret void
39 }
41 ; Set FP64/FP16 fp_round to round to zero
42 define amdgpu_kernel void @test_setreg_f64_round_mode_rtz() {
43 ; GFX6-LABEL: test_setreg_f64_round_mode_rtz:
44 ; GFX6: ; %bb.0:
45 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00]
46 ; GFX6-NEXT: ;;#ASMSTART
47 ; GFX6-NEXT: ;;#ASMEND
48 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
49 ;
50 ; GFX789-LABEL: test_setreg_f64_round_mode_rtz:
51 ; GFX789: ; %bb.0:
52 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x00,0xba,0x03,0x00,0x00,0x00]
53 ; GFX789-NEXT: ;;#ASMSTART
54 ; GFX789-NEXT: ;;#ASMEND
55 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
56 ;
57 ; GFX10-LABEL: test_setreg_f64_round_mode_rtz:
58 ; GFX10: ; %bb.0:
59 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x03,0x00,0x00,0x00]
60 ; GFX10-NEXT: ;;#ASMSTART
61 ; GFX10-NEXT: ;;#ASMEND
62 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
63 call void @llvm.amdgcn.s.setreg(i32 2177, i32 3)
64 call void asm sideeffect "", ""()
65 ret void
66 }
68 ; Set all fp_round to round to zero
69 define amdgpu_kernel void @test_setreg_all_round_mode_rtz() {
70 ; GFX6-LABEL: test_setreg_all_round_mode_rtz:
71 ; GFX6: ; %bb.0:
72 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00]
73 ; GFX6-NEXT: ;;#ASMSTART
74 ; GFX6-NEXT: ;;#ASMEND
75 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
76 ;
77 ; GFX789-LABEL: test_setreg_all_round_mode_rtz:
78 ; GFX789: ; %bb.0:
79 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x00,0xba,0x07,0x00,0x00,0x00]
80 ; GFX789-NEXT: ;;#ASMSTART
81 ; GFX789-NEXT: ;;#ASMEND
82 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
83 ;
84 ; GFX10-LABEL: test_setreg_all_round_mode_rtz:
85 ; GFX10: ; %bb.0:
86 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x07,0x00,0x00,0x00]
87 ; GFX10-NEXT: ;;#ASMSTART
88 ; GFX10-NEXT: ;;#ASMEND
89 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
90 call void @llvm.amdgcn.s.setreg(i32 6273, i32 7)
91 call void asm sideeffect "", ""()
92 ret void
93 }
95 ; Set FP32 fp_round to dynamic mode
96 define amdgpu_cs void @test_setreg_roundingmode_var(i32 inreg %var.mode) {
97 ; GFX6-LABEL: test_setreg_roundingmode_var:
98 ; GFX6: ; %bb.0:
99 ; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9]
100 ; GFX6-NEXT: ;;#ASMSTART
101 ; GFX6-NEXT: ;;#ASMEND
102 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
103 ;
104 ; GFX789-LABEL: test_setreg_roundingmode_var:
105 ; GFX789: ; %bb.0:
106 ; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x00,0xb9]
107 ; GFX789-NEXT: ;;#ASMSTART
108 ; GFX789-NEXT: ;;#ASMEND
109 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
110 ;
111 ; GFX10-LABEL: test_setreg_roundingmode_var:
112 ; GFX10: ; %bb.0:
113 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 2), s0 ; encoding: [0x01,0x08,0x80,0xb9]
114 ; GFX10-NEXT: ;;#ASMSTART
115 ; GFX10-NEXT: ;;#ASMEND
116 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
117 call void @llvm.amdgcn.s.setreg(i32 2049, i32 %var.mode)
118 call void asm sideeffect "", ""()
119 ret void
120 }
122 define amdgpu_kernel void @test_setreg_ieee_mode_off() {
123 ; GFX6-LABEL: test_setreg_ieee_mode_off:
124 ; GFX6: ; %bb.0:
125 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x00,0x00]
126 ; GFX6-NEXT: ;;#ASMSTART
127 ; GFX6-NEXT: ;;#ASMEND
128 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
129 ;
130 ; GFX789-LABEL: test_setreg_ieee_mode_off:
131 ; GFX789: ; %bb.0:
132 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x00,0xba,0x00,0x00,0x00,0x00]
133 ; GFX789-NEXT: ;;#ASMSTART
134 ; GFX789-NEXT: ;;#ASMEND
135 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
136 ;
137 ; GFX10-LABEL: test_setreg_ieee_mode_off:
138 ; GFX10: ; %bb.0:
139 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 0 ; encoding: [0x41,0x02,0x80,0xba,0x00,0x00,0x00,0x00]
140 ; GFX10-NEXT: ;;#ASMSTART
141 ; GFX10-NEXT: ;;#ASMEND
142 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
143 call void @llvm.amdgcn.s.setreg(i32 577, i32 0)
144 call void asm sideeffect "", ""()
145 ret void
146 }
148 define amdgpu_kernel void @test_setreg_ieee_mode_on() {
149 ; GFX6-LABEL: test_setreg_ieee_mode_on:
150 ; GFX6: ; %bb.0:
151 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
152 ; GFX6-NEXT: ;;#ASMSTART
153 ; GFX6-NEXT: ;;#ASMEND
154 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
155 ;
156 ; GFX789-LABEL: test_setreg_ieee_mode_on:
157 ; GFX789: ; %bb.0:
158 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x00,0xba,0x01,0x00,0x00,0x00]
159 ; GFX789-NEXT: ;;#ASMSTART
160 ; GFX789-NEXT: ;;#ASMEND
161 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
162 ;
163 ; GFX10-LABEL: test_setreg_ieee_mode_on:
164 ; GFX10: ; %bb.0:
165 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 9, 1), 1 ; encoding: [0x41,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
166 ; GFX10-NEXT: ;;#ASMSTART
167 ; GFX10-NEXT: ;;#ASMEND
168 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
169 call void @llvm.amdgcn.s.setreg(i32 577, i32 1)
170 call void asm sideeffect "", ""()
171 ret void
172 }
174 define amdgpu_kernel void @test_setreg_dx10_clamp_off() {
175 ; GFX6-LABEL: test_setreg_dx10_clamp_off:
176 ; GFX6: ; %bb.0:
177 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x00,0x00]
178 ; GFX6-NEXT: ;;#ASMSTART
179 ; GFX6-NEXT: ;;#ASMEND
180 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
181 ;
182 ; GFX789-LABEL: test_setreg_dx10_clamp_off:
183 ; GFX789: ; %bb.0:
184 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x00,0xba,0x00,0x00,0x00,0x00]
185 ; GFX789-NEXT: ;;#ASMSTART
186 ; GFX789-NEXT: ;;#ASMEND
187 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
188 ;
189 ; GFX10-LABEL: test_setreg_dx10_clamp_off:
190 ; GFX10: ; %bb.0:
191 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 0 ; encoding: [0x01,0x02,0x80,0xba,0x00,0x00,0x00,0x00]
192 ; GFX10-NEXT: ;;#ASMSTART
193 ; GFX10-NEXT: ;;#ASMEND
194 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
195 call void @llvm.amdgcn.s.setreg(i32 513, i32 0)
196 call void asm sideeffect "", ""()
197 ret void
198 }
200 define amdgpu_kernel void @test_setreg_dx10_clamp_on() {
201 ; GFX6-LABEL: test_setreg_dx10_clamp_on:
202 ; GFX6: ; %bb.0:
203 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
204 ; GFX6-NEXT: ;;#ASMSTART
205 ; GFX6-NEXT: ;;#ASMEND
206 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
207 ;
208 ; GFX789-LABEL: test_setreg_dx10_clamp_on:
209 ; GFX789: ; %bb.0:
210 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x00,0xba,0x01,0x00,0x00,0x00]
211 ; GFX789-NEXT: ;;#ASMSTART
212 ; GFX789-NEXT: ;;#ASMEND
213 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
214 ;
215 ; GFX10-LABEL: test_setreg_dx10_clamp_on:
216 ; GFX10: ; %bb.0:
217 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 8, 1), 1 ; encoding: [0x01,0x02,0x80,0xba,0x01,0x00,0x00,0x00]
218 ; GFX10-NEXT: ;;#ASMSTART
219 ; GFX10-NEXT: ;;#ASMEND
220 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
221 call void @llvm.amdgcn.s.setreg(i32 513, i32 1)
222 call void asm sideeffect "", ""()
223 ret void
224 }
226 ; Sets full width of fp round and fp denorm fields, to a variable
227 define amdgpu_cs void @test_setreg_full_both_round_mode_and_denorm_mode(i32 inreg %mode) {
228 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode:
229 ; GFX6: ; %bb.0:
230 ; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9]
231 ; GFX6-NEXT: ;;#ASMSTART
232 ; GFX6-NEXT: ;;#ASMEND
233 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
234 ;
235 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode:
236 ; GFX789: ; %bb.0:
237 ; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x00,0xb9]
238 ; GFX789-NEXT: ;;#ASMSTART
239 ; GFX789-NEXT: ;;#ASMEND
240 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
241 ;
242 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode:
243 ; GFX10: ; %bb.0:
244 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 8), s0 ; encoding: [0x01,0x38,0x80,0xb9]
245 ; GFX10-NEXT: ;;#ASMSTART
246 ; GFX10-NEXT: ;;#ASMEND
247 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
248 call void @llvm.amdgcn.s.setreg(i32 14337, i32 inreg %mode)
249 call void asm sideeffect "", ""()
250 ret void
251 }
253 ; Does not cover last bit of denorm field
254 define amdgpu_cs void @test_setreg_most_both_round_mode_and_denorm_mode() {
255 ; GFX6-LABEL: test_setreg_most_both_round_mode_and_denorm_mode:
256 ; GFX6: ; %bb.0:
257 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00,0x00,0x00]
258 ; GFX6-NEXT: ;;#ASMSTART
259 ; GFX6-NEXT: ;;#ASMEND
260 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
261 ;
262 ; GFX789-LABEL: test_setreg_most_both_round_mode_and_denorm_mode:
263 ; GFX789: ; %bb.0:
264 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x00,0xba,0x06,0x00,0x00,0x00]
265 ; GFX789-NEXT: ;;#ASMSTART
266 ; GFX789-NEXT: ;;#ASMEND
267 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
268 ;
269 ; GFX10-LABEL: test_setreg_most_both_round_mode_and_denorm_mode:
270 ; GFX10: ; %bb.0:
271 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 7), 6 ; encoding: [0x01,0x30,0x80,0xba,0x06,0x00,0x00,0x00]
272 ; GFX10-NEXT: ;;#ASMSTART
273 ; GFX10-NEXT: ;;#ASMEND
274 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
275 call void @llvm.amdgcn.s.setreg(i32 12289, i32 6)
276 call void asm sideeffect "", ""()
277 ret void
278 }
280 ; Does not cover first bit of denorm field
281 define amdgpu_cs void @test_setreg_most_both_round_mode_and_denorm_mode_6() {
282 ; GFX6-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6:
283 ; GFX6: ; %bb.0:
284 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00]
285 ; GFX6-NEXT: ;;#ASMSTART
286 ; GFX6-NEXT: ;;#ASMEND
287 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
288 ;
289 ; GFX789-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6:
290 ; GFX789: ; %bb.0:
291 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x00,0xba,0x06,0x00,0x00,0x00]
292 ; GFX789-NEXT: ;;#ASMSTART
293 ; GFX789-NEXT: ;;#ASMEND
294 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
295 ;
296 ; GFX10-LABEL: test_setreg_most_both_round_mode_and_denorm_mode_6:
297 ; GFX10: ; %bb.0:
298 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 1, 3), 6 ; encoding: [0x41,0x10,0x80,0xba,0x06,0x00,0x00,0x00]
299 ; GFX10-NEXT: ;;#ASMSTART
300 ; GFX10-NEXT: ;;#ASMEND
301 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
302 call void @llvm.amdgcn.s.setreg(i32 4161, i32 6)
303 call void asm sideeffect "", ""()
304 ret void
305 }
307 define amdgpu_cs void @test_setreg_f32_denorm_mode(i32 inreg %val) {
308 ; GFX6-LABEL: test_setreg_f32_denorm_mode:
309 ; GFX6: ; %bb.0:
310 ; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9]
311 ; GFX6-NEXT: ;;#ASMSTART
312 ; GFX6-NEXT: ;;#ASMEND
313 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
314 ;
315 ; GFX789-LABEL: test_setreg_f32_denorm_mode:
316 ; GFX789: ; %bb.0:
317 ; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x00,0xb9]
318 ; GFX789-NEXT: ;;#ASMSTART
319 ; GFX789-NEXT: ;;#ASMEND
320 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
321 ;
322 ; GFX10-LABEL: test_setreg_f32_denorm_mode:
323 ; GFX10: ; %bb.0:
324 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 4, 2), s0 ; encoding: [0x01,0x09,0x80,0xb9]
325 ; GFX10-NEXT: ;;#ASMSTART
326 ; GFX10-NEXT: ;;#ASMEND
327 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
328 call void @llvm.amdgcn.s.setreg(i32 2305, i32 %val)
329 call void asm sideeffect "", ""()
330 ret void
331 }
333 define amdgpu_cs void @test_setreg_f64_denorm_mode(i32 inreg %val) {
334 ; GFX6-LABEL: test_setreg_f64_denorm_mode:
335 ; GFX6: ; %bb.0:
336 ; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9]
337 ; GFX6-NEXT: ;;#ASMSTART
338 ; GFX6-NEXT: ;;#ASMEND
339 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
340 ;
341 ; GFX789-LABEL: test_setreg_f64_denorm_mode:
342 ; GFX789: ; %bb.0:
343 ; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x00,0xb9]
344 ; GFX789-NEXT: ;;#ASMSTART
345 ; GFX789-NEXT: ;;#ASMEND
346 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
347 ;
348 ; GFX10-LABEL: test_setreg_f64_denorm_mode:
349 ; GFX10: ; %bb.0:
350 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 6, 2), s0 ; encoding: [0x81,0x09,0x80,0xb9]
351 ; GFX10-NEXT: ;;#ASMSTART
352 ; GFX10-NEXT: ;;#ASMEND
353 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
354 call void @llvm.amdgcn.s.setreg(i32 2433, i32 %val)
355 call void asm sideeffect "", ""()
356 ret void
357 }
359 define amdgpu_cs void @test_setreg_full_denorm_mode(i32 inreg %val) {
360 ; GFX6-LABEL: test_setreg_full_denorm_mode:
361 ; GFX6: ; %bb.0:
362 ; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9]
363 ; GFX6-NEXT: ;;#ASMSTART
364 ; GFX6-NEXT: ;;#ASMEND
365 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
366 ;
367 ; GFX789-LABEL: test_setreg_full_denorm_mode:
368 ; GFX789: ; %bb.0:
369 ; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x00,0xb9]
370 ; GFX789-NEXT: ;;#ASMSTART
371 ; GFX789-NEXT: ;;#ASMEND
372 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
373 ;
374 ; GFX10-LABEL: test_setreg_full_denorm_mode:
375 ; GFX10: ; %bb.0:
376 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 4), s0 ; encoding: [0x01,0x18,0x80,0xb9]
377 ; GFX10-NEXT: ;;#ASMSTART
378 ; GFX10-NEXT: ;;#ASMEND
379 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
380 call void @llvm.amdgcn.s.setreg(i32 6145, i32 %val)
381 call void asm sideeffect "", ""()
382 ret void
383 }
385 define amdgpu_kernel void @test_setreg_full_round_mode_0() {
386 ; GFX6-LABEL: test_setreg_full_round_mode_0:
387 ; GFX6: ; %bb.0:
388 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x80,0xba,0x00,0x00,0x00,0x00]
389 ; GFX6-NEXT: ;;#ASMSTART
390 ; GFX6-NEXT: ;;#ASMEND
391 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
392 ;
393 ; GFX789-LABEL: test_setreg_full_round_mode_0:
394 ; GFX789: ; %bb.0:
395 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 0 ; encoding: [0x01,0x18,0x00,0xba,0x00,0x00,0x00,0x00]
396 ; GFX789-NEXT: ;;#ASMSTART
397 ; GFX789-NEXT: ;;#ASMEND
398 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
399 ;
400 ; GFX10-LABEL: test_setreg_full_round_mode_0:
401 ; GFX10: ; %bb.0:
402 ; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
403 ; GFX10-NEXT: ;;#ASMSTART
404 ; GFX10-NEXT: ;;#ASMEND
405 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
406 call void @llvm.amdgcn.s.setreg(i32 6145, i32 0)
407 call void asm sideeffect "", ""()
408 ret void
409 }
411 define amdgpu_kernel void @test_setreg_full_round_mode_1() {
412 ; GFX6-LABEL: test_setreg_full_round_mode_1:
413 ; GFX6: ; %bb.0:
414 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x80,0xba,0x01,0x00,0x00,0x00]
415 ; GFX6-NEXT: ;;#ASMSTART
416 ; GFX6-NEXT: ;;#ASMEND
417 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
418 ;
419 ; GFX789-LABEL: test_setreg_full_round_mode_1:
420 ; GFX789: ; %bb.0:
421 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 1 ; encoding: [0x01,0x18,0x00,0xba,0x01,0x00,0x00,0x00]
422 ; GFX789-NEXT: ;;#ASMSTART
423 ; GFX789-NEXT: ;;#ASMEND
424 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
425 ;
426 ; GFX10-LABEL: test_setreg_full_round_mode_1:
427 ; GFX10: ; %bb.0:
428 ; GFX10-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf]
429 ; GFX10-NEXT: ;;#ASMSTART
430 ; GFX10-NEXT: ;;#ASMEND
431 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
432 call void @llvm.amdgcn.s.setreg(i32 6145, i32 1)
433 call void asm sideeffect "", ""()
434 ret void
435 }
437 define amdgpu_kernel void @test_setreg_full_round_mode_2() {
438 ; GFX6-LABEL: test_setreg_full_round_mode_2:
439 ; GFX6: ; %bb.0:
440 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x80,0xba,0x02,0x00,0x00,0x00]
441 ; GFX6-NEXT: ;;#ASMSTART
442 ; GFX6-NEXT: ;;#ASMEND
443 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
444 ;
445 ; GFX789-LABEL: test_setreg_full_round_mode_2:
446 ; GFX789: ; %bb.0:
447 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 2 ; encoding: [0x01,0x18,0x00,0xba,0x02,0x00,0x00,0x00]
448 ; GFX789-NEXT: ;;#ASMSTART
449 ; GFX789-NEXT: ;;#ASMEND
450 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
451 ;
452 ; GFX10-LABEL: test_setreg_full_round_mode_2:
453 ; GFX10: ; %bb.0:
454 ; GFX10-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf]
455 ; GFX10-NEXT: ;;#ASMSTART
456 ; GFX10-NEXT: ;;#ASMEND
457 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
458 call void @llvm.amdgcn.s.setreg(i32 6145, i32 2)
459 call void asm sideeffect "", ""()
460 ret void
461 }
463 define amdgpu_kernel void @test_setreg_full_round_mode_4() {
464 ; GFX6-LABEL: test_setreg_full_round_mode_4:
465 ; GFX6: ; %bb.0:
466 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x80,0xba,0x04,0x00,0x00,0x00]
467 ; GFX6-NEXT: ;;#ASMSTART
468 ; GFX6-NEXT: ;;#ASMEND
469 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
470 ;
471 ; GFX789-LABEL: test_setreg_full_round_mode_4:
472 ; GFX789: ; %bb.0:
473 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 4 ; encoding: [0x01,0x18,0x00,0xba,0x04,0x00,0x00,0x00]
474 ; GFX789-NEXT: ;;#ASMSTART
475 ; GFX789-NEXT: ;;#ASMEND
476 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
477 ;
478 ; GFX10-LABEL: test_setreg_full_round_mode_4:
479 ; GFX10: ; %bb.0:
480 ; GFX10-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf]
481 ; GFX10-NEXT: ;;#ASMSTART
482 ; GFX10-NEXT: ;;#ASMEND
483 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
484 call void @llvm.amdgcn.s.setreg(i32 6145, i32 4)
485 call void asm sideeffect "", ""()
486 ret void
487 }
489 define amdgpu_kernel void @test_setreg_full_round_mode_8() {
490 ; GFX6-LABEL: test_setreg_full_round_mode_8:
491 ; GFX6: ; %bb.0:
492 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x80,0xba,0x08,0x00,0x00,0x00]
493 ; GFX6-NEXT: ;;#ASMSTART
494 ; GFX6-NEXT: ;;#ASMEND
495 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
496 ;
497 ; GFX789-LABEL: test_setreg_full_round_mode_8:
498 ; GFX789: ; %bb.0:
499 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 8 ; encoding: [0x01,0x18,0x00,0xba,0x08,0x00,0x00,0x00]
500 ; GFX789-NEXT: ;;#ASMSTART
501 ; GFX789-NEXT: ;;#ASMEND
502 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
503 ;
504 ; GFX10-LABEL: test_setreg_full_round_mode_8:
505 ; GFX10: ; %bb.0:
506 ; GFX10-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf]
507 ; GFX10-NEXT: ;;#ASMSTART
508 ; GFX10-NEXT: ;;#ASMEND
509 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
510 call void @llvm.amdgcn.s.setreg(i32 6145, i32 8)
511 call void asm sideeffect "", ""()
512 ret void
513 }
515 define amdgpu_kernel void @test_setreg_full_round_mode_15() {
516 ; GFX6-LABEL: test_setreg_full_round_mode_15:
517 ; GFX6: ; %bb.0:
518 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]
519 ; GFX6-NEXT: ;;#ASMSTART
520 ; GFX6-NEXT: ;;#ASMEND
521 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
522 ;
523 ; GFX789-LABEL: test_setreg_full_round_mode_15:
524 ; GFX789: ; %bb.0:
525 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 15 ; encoding: [0x01,0x18,0x00,0xba,0x0f,0x00,0x00,0x00]
526 ; GFX789-NEXT: ;;#ASMSTART
527 ; GFX789-NEXT: ;;#ASMEND
528 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
529 ;
530 ; GFX10-LABEL: test_setreg_full_round_mode_15:
531 ; GFX10: ; %bb.0:
532 ; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]
533 ; GFX10-NEXT: ;;#ASMSTART
534 ; GFX10-NEXT: ;;#ASMEND
535 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
536 call void @llvm.amdgcn.s.setreg(i32 6145, i32 15)
537 call void asm sideeffect "", ""()
538 ret void
539 }
541 ; Should truncate set immediate value
542 define amdgpu_kernel void @test_setreg_full_round_mode_42() {
543 ; GFX6-LABEL: test_setreg_full_round_mode_42:
544 ; GFX6: ; %bb.0:
545 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x80,0xba,0x2a,0x00,0x00,0x00]
546 ; GFX6-NEXT: ;;#ASMSTART
547 ; GFX6-NEXT: ;;#ASMEND
548 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
549 ;
550 ; GFX789-LABEL: test_setreg_full_round_mode_42:
551 ; GFX789: ; %bb.0:
552 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 4), 42 ; encoding: [0x01,0x18,0x00,0xba,0x2a,0x00,0x00,0x00]
553 ; GFX789-NEXT: ;;#ASMSTART
554 ; GFX789-NEXT: ;;#ASMEND
555 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
556 ;
557 ; GFX10-LABEL: test_setreg_full_round_mode_42:
558 ; GFX10: ; %bb.0:
559 ; GFX10-NEXT: s_round_mode 0xa ; encoding: [0x0a,0x00,0xa4,0xbf]
560 ; GFX10-NEXT: ;;#ASMSTART
561 ; GFX10-NEXT: ;;#ASMEND
562 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
563 call void @llvm.amdgcn.s.setreg(i32 6145, i32 42)
564 call void asm sideeffect "", ""()
565 ret void
566 }
568 define amdgpu_kernel void @test_setreg_full_denorm_mode_0() {
569 ; GFX6-LABEL: test_setreg_full_denorm_mode_0:
570 ; GFX6: ; %bb.0:
571 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x80,0xba,0x00,0x00,0x00,0x00]
572 ; GFX6-NEXT: ;;#ASMSTART
573 ; GFX6-NEXT: ;;#ASMEND
574 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
575 ;
576 ; GFX789-LABEL: test_setreg_full_denorm_mode_0:
577 ; GFX789: ; %bb.0:
578 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 0 ; encoding: [0x01,0x19,0x00,0xba,0x00,0x00,0x00,0x00]
579 ; GFX789-NEXT: ;;#ASMSTART
580 ; GFX789-NEXT: ;;#ASMEND
581 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
582 ;
583 ; GFX10-LABEL: test_setreg_full_denorm_mode_0:
584 ; GFX10: ; %bb.0:
585 ; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
586 ; GFX10-NEXT: ;;#ASMSTART
587 ; GFX10-NEXT: ;;#ASMEND
588 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
589 call void @llvm.amdgcn.s.setreg(i32 6401, i32 0)
590 call void asm sideeffect "", ""()
591 ret void
592 }
594 define amdgpu_kernel void @test_setreg_full_denorm_mode_1() {
595 ; GFX6-LABEL: test_setreg_full_denorm_mode_1:
596 ; GFX6: ; %bb.0:
597 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x80,0xba,0x01,0x00,0x00,0x00]
598 ; GFX6-NEXT: ;;#ASMSTART
599 ; GFX6-NEXT: ;;#ASMEND
600 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
601 ;
602 ; GFX789-LABEL: test_setreg_full_denorm_mode_1:
603 ; GFX789: ; %bb.0:
604 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 1 ; encoding: [0x01,0x19,0x00,0xba,0x01,0x00,0x00,0x00]
605 ; GFX789-NEXT: ;;#ASMSTART
606 ; GFX789-NEXT: ;;#ASMEND
607 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
608 ;
609 ; GFX10-LABEL: test_setreg_full_denorm_mode_1:
610 ; GFX10: ; %bb.0:
611 ; GFX10-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf]
612 ; GFX10-NEXT: ;;#ASMSTART
613 ; GFX10-NEXT: ;;#ASMEND
614 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
615 call void @llvm.amdgcn.s.setreg(i32 6401, i32 1)
616 call void asm sideeffect "", ""()
617 ret void
618 }
621 define amdgpu_kernel void @test_setreg_full_denorm_mode_2() {
622 ; GFX6-LABEL: test_setreg_full_denorm_mode_2:
623 ; GFX6: ; %bb.0:
624 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x80,0xba,0x02,0x00,0x00,0x00]
625 ; GFX6-NEXT: ;;#ASMSTART
626 ; GFX6-NEXT: ;;#ASMEND
627 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
628 ;
629 ; GFX789-LABEL: test_setreg_full_denorm_mode_2:
630 ; GFX789: ; %bb.0:
631 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 2 ; encoding: [0x01,0x19,0x00,0xba,0x02,0x00,0x00,0x00]
632 ; GFX789-NEXT: ;;#ASMSTART
633 ; GFX789-NEXT: ;;#ASMEND
634 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
635 ;
636 ; GFX10-LABEL: test_setreg_full_denorm_mode_2:
637 ; GFX10: ; %bb.0:
638 ; GFX10-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf]
639 ; GFX10-NEXT: ;;#ASMSTART
640 ; GFX10-NEXT: ;;#ASMEND
641 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
642 call void @llvm.amdgcn.s.setreg(i32 6401, i32 2)
643 call void asm sideeffect "", ""()
644 ret void
645 }
647 define amdgpu_kernel void @test_setreg_full_denorm_mode_4() {
648 ; GFX6-LABEL: test_setreg_full_denorm_mode_4:
649 ; GFX6: ; %bb.0:
650 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x80,0xba,0x04,0x00,0x00,0x00]
651 ; GFX6-NEXT: ;;#ASMSTART
652 ; GFX6-NEXT: ;;#ASMEND
653 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
654 ;
655 ; GFX789-LABEL: test_setreg_full_denorm_mode_4:
656 ; GFX789: ; %bb.0:
657 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 4 ; encoding: [0x01,0x19,0x00,0xba,0x04,0x00,0x00,0x00]
658 ; GFX789-NEXT: ;;#ASMSTART
659 ; GFX789-NEXT: ;;#ASMEND
660 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
661 ;
662 ; GFX10-LABEL: test_setreg_full_denorm_mode_4:
663 ; GFX10: ; %bb.0:
664 ; GFX10-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf]
665 ; GFX10-NEXT: ;;#ASMSTART
666 ; GFX10-NEXT: ;;#ASMEND
667 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
668 call void @llvm.amdgcn.s.setreg(i32 6401, i32 4)
669 call void asm sideeffect "", ""()
670 ret void
671 }
673 define amdgpu_kernel void @test_setreg_full_denorm_mode_8() {
674 ; GFX6-LABEL: test_setreg_full_denorm_mode_8:
675 ; GFX6: ; %bb.0:
676 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x80,0xba,0x08,0x00,0x00,0x00]
677 ; GFX6-NEXT: ;;#ASMSTART
678 ; GFX6-NEXT: ;;#ASMEND
679 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
680 ;
681 ; GFX789-LABEL: test_setreg_full_denorm_mode_8:
682 ; GFX789: ; %bb.0:
683 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 8 ; encoding: [0x01,0x19,0x00,0xba,0x08,0x00,0x00,0x00]
684 ; GFX789-NEXT: ;;#ASMSTART
685 ; GFX789-NEXT: ;;#ASMEND
686 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
687 ;
688 ; GFX10-LABEL: test_setreg_full_denorm_mode_8:
689 ; GFX10: ; %bb.0:
690 ; GFX10-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf]
691 ; GFX10-NEXT: ;;#ASMSTART
692 ; GFX10-NEXT: ;;#ASMEND
693 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
694 call void @llvm.amdgcn.s.setreg(i32 6401, i32 8)
695 call void asm sideeffect "", ""()
696 ret void
697 }
699 define amdgpu_kernel void @test_setreg_full_denorm_mode_15() {
700 ; GFX6-LABEL: test_setreg_full_denorm_mode_15:
701 ; GFX6: ; %bb.0:
702 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x80,0xba,0x0f,0x00,0x00,0x00]
703 ; GFX6-NEXT: ;;#ASMSTART
704 ; GFX6-NEXT: ;;#ASMEND
705 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
706 ;
707 ; GFX789-LABEL: test_setreg_full_denorm_mode_15:
708 ; GFX789: ; %bb.0:
709 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 15 ; encoding: [0x01,0x19,0x00,0xba,0x0f,0x00,0x00,0x00]
710 ; GFX789-NEXT: ;;#ASMSTART
711 ; GFX789-NEXT: ;;#ASMEND
712 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
713 ;
714 ; GFX10-LABEL: test_setreg_full_denorm_mode_15:
715 ; GFX10: ; %bb.0:
716 ; GFX10-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf]
717 ; GFX10-NEXT: ;;#ASMSTART
718 ; GFX10-NEXT: ;;#ASMEND
719 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
720 call void @llvm.amdgcn.s.setreg(i32 6401, i32 15)
721 call void asm sideeffect "", ""()
722 ret void
723 }
725 define amdgpu_kernel void @test_setreg_full_denorm_mode_42() {
726 ; GFX6-LABEL: test_setreg_full_denorm_mode_42:
727 ; GFX6: ; %bb.0:
728 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x80,0xba,0x2a,0x00,0x00,0x00]
729 ; GFX6-NEXT: ;;#ASMSTART
730 ; GFX6-NEXT: ;;#ASMEND
731 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
732 ;
733 ; GFX789-LABEL: test_setreg_full_denorm_mode_42:
734 ; GFX789: ; %bb.0:
735 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 4), 42 ; encoding: [0x01,0x19,0x00,0xba,0x2a,0x00,0x00,0x00]
736 ; GFX789-NEXT: ;;#ASMSTART
737 ; GFX789-NEXT: ;;#ASMEND
738 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
739 ;
740 ; GFX10-LABEL: test_setreg_full_denorm_mode_42:
741 ; GFX10: ; %bb.0:
742 ; GFX10-NEXT: s_denorm_mode 10 ; encoding: [0x0a,0x00,0xa5,0xbf]
743 ; GFX10-NEXT: ;;#ASMSTART
744 ; GFX10-NEXT: ;;#ASMEND
745 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
746 call void @llvm.amdgcn.s.setreg(i32 6401, i32 42)
747 call void asm sideeffect "", ""()
748 ret void
749 }
751 ; Sets all fp round and fp denorm bits.
752 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_0() {
753 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:
754 ; GFX6: ; %bb.0:
755 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x80,0xba,0x00,0x00,0x00,0x00]
756 ; GFX6-NEXT: ;;#ASMSTART
757 ; GFX6-NEXT: ;;#ASMEND
758 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
759 ;
760 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:
761 ; GFX789: ; %bb.0:
762 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0 ; encoding: [0x01,0x38,0x00,0xba,0x00,0x00,0x00,0x00]
763 ; GFX789-NEXT: ;;#ASMSTART
764 ; GFX789-NEXT: ;;#ASMEND
765 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
766 ;
767 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_0:
768 ; GFX10: ; %bb.0:
769 ; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
770 ; GFX10-NEXT: ;;#ASMSTART
771 ; GFX10-NEXT: ;;#ASMEND
772 ; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
773 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
774 call void @llvm.amdgcn.s.setreg(i32 14337, i32 0)
775 call void asm sideeffect "", ""()
776 ret void
777 }
779 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1() {
780 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:
781 ; GFX6: ; %bb.0:
782 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x80,0xba,0x01,0x00,0x00,0x00]
783 ; GFX6-NEXT: ;;#ASMSTART
784 ; GFX6-NEXT: ;;#ASMEND
785 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
786 ;
787 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:
788 ; GFX789: ; %bb.0:
789 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 1 ; encoding: [0x01,0x38,0x00,0xba,0x01,0x00,0x00,0x00]
790 ; GFX789-NEXT: ;;#ASMSTART
791 ; GFX789-NEXT: ;;#ASMEND
792 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
793 ;
794 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_1:
795 ; GFX10: ; %bb.0:
796 ; GFX10-NEXT: s_round_mode 0x1 ; encoding: [0x01,0x00,0xa4,0xbf]
797 ; GFX10-NEXT: ;;#ASMSTART
798 ; GFX10-NEXT: ;;#ASMEND
799 ; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
800 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
801 call void @llvm.amdgcn.s.setreg(i32 14337, i32 1)
802 call void asm sideeffect "", ""()
803 ret void
804 }
806 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2() {
807 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:
808 ; GFX6: ; %bb.0:
809 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x80,0xba,0x02,0x00,0x00,0x00]
810 ; GFX6-NEXT: ;;#ASMSTART
811 ; GFX6-NEXT: ;;#ASMEND
812 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
813 ;
814 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:
815 ; GFX789: ; %bb.0:
816 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 2 ; encoding: [0x01,0x38,0x00,0xba,0x02,0x00,0x00,0x00]
817 ; GFX789-NEXT: ;;#ASMSTART
818 ; GFX789-NEXT: ;;#ASMEND
819 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
820 ;
821 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_2:
822 ; GFX10: ; %bb.0:
823 ; GFX10-NEXT: s_round_mode 0x2 ; encoding: [0x02,0x00,0xa4,0xbf]
824 ; GFX10-NEXT: ;;#ASMSTART
825 ; GFX10-NEXT: ;;#ASMEND
826 ; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
827 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
828 call void @llvm.amdgcn.s.setreg(i32 14337, i32 2)
829 call void asm sideeffect "", ""()
830 ret void
831 }
833 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4() {
834 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:
835 ; GFX6: ; %bb.0:
836 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x80,0xba,0x04,0x00,0x00,0x00]
837 ; GFX6-NEXT: ;;#ASMSTART
838 ; GFX6-NEXT: ;;#ASMEND
839 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
840 ;
841 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:
842 ; GFX789: ; %bb.0:
843 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 4 ; encoding: [0x01,0x38,0x00,0xba,0x04,0x00,0x00,0x00]
844 ; GFX789-NEXT: ;;#ASMSTART
845 ; GFX789-NEXT: ;;#ASMEND
846 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
847 ;
848 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_4:
849 ; GFX10: ; %bb.0:
850 ; GFX10-NEXT: s_round_mode 0x4 ; encoding: [0x04,0x00,0xa4,0xbf]
851 ; GFX10-NEXT: ;;#ASMSTART
852 ; GFX10-NEXT: ;;#ASMEND
853 ; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
854 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
855 call void @llvm.amdgcn.s.setreg(i32 14337, i32 4)
856 call void asm sideeffect "", ""()
857 ret void
858 }
860 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8() {
861 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:
862 ; GFX6: ; %bb.0:
863 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x80,0xba,0x08,0x00,0x00,0x00]
864 ; GFX6-NEXT: ;;#ASMSTART
865 ; GFX6-NEXT: ;;#ASMEND
866 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
867 ;
868 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:
869 ; GFX789: ; %bb.0:
870 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 8 ; encoding: [0x01,0x38,0x00,0xba,0x08,0x00,0x00,0x00]
871 ; GFX789-NEXT: ;;#ASMSTART
872 ; GFX789-NEXT: ;;#ASMEND
873 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
874 ;
875 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_8:
876 ; GFX10: ; %bb.0:
877 ; GFX10-NEXT: s_round_mode 0x8 ; encoding: [0x08,0x00,0xa4,0xbf]
878 ; GFX10-NEXT: ;;#ASMSTART
879 ; GFX10-NEXT: ;;#ASMEND
880 ; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
881 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
882 call void @llvm.amdgcn.s.setreg(i32 14337, i32 8)
883 call void asm sideeffect "", ""()
884 ret void
885 }
887 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16() {
888 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:
889 ; GFX6: ; %bb.0:
890 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x80,0xba,0x10,0x00,0x00,0x00]
891 ; GFX6-NEXT: ;;#ASMSTART
892 ; GFX6-NEXT: ;;#ASMEND
893 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
894 ;
895 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:
896 ; GFX789: ; %bb.0:
897 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 16 ; encoding: [0x01,0x38,0x00,0xba,0x10,0x00,0x00,0x00]
898 ; GFX789-NEXT: ;;#ASMSTART
899 ; GFX789-NEXT: ;;#ASMEND
900 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
901 ;
902 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_16:
903 ; GFX10: ; %bb.0:
904 ; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
905 ; GFX10-NEXT: ;;#ASMSTART
906 ; GFX10-NEXT: ;;#ASMEND
907 ; GFX10-NEXT: s_denorm_mode 1 ; encoding: [0x01,0x00,0xa5,0xbf]
908 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
909 call void @llvm.amdgcn.s.setreg(i32 14337, i32 16)
910 call void asm sideeffect "", ""()
911 ret void
912 }
914 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32() {
915 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:
916 ; GFX6: ; %bb.0:
917 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x80,0xba,0x20,0x00,0x00,0x00]
918 ; GFX6-NEXT: ;;#ASMSTART
919 ; GFX6-NEXT: ;;#ASMEND
920 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
921 ;
922 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:
923 ; GFX789: ; %bb.0:
924 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 32 ; encoding: [0x01,0x38,0x00,0xba,0x20,0x00,0x00,0x00]
925 ; GFX789-NEXT: ;;#ASMSTART
926 ; GFX789-NEXT: ;;#ASMEND
927 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
928 ;
929 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_32:
930 ; GFX10: ; %bb.0:
931 ; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
932 ; GFX10-NEXT: ;;#ASMSTART
933 ; GFX10-NEXT: ;;#ASMEND
934 ; GFX10-NEXT: s_denorm_mode 2 ; encoding: [0x02,0x00,0xa5,0xbf]
935 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
936 call void @llvm.amdgcn.s.setreg(i32 14337, i32 32)
937 call void asm sideeffect "", ""()
938 ret void
939 }
941 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64() {
942 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:
943 ; GFX6: ; %bb.0:
944 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x80,0xba,0x40,0x00,0x00,0x00]
945 ; GFX6-NEXT: ;;#ASMSTART
946 ; GFX6-NEXT: ;;#ASMEND
947 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
948 ;
949 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:
950 ; GFX789: ; %bb.0:
951 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 64 ; encoding: [0x01,0x38,0x00,0xba,0x40,0x00,0x00,0x00]
952 ; GFX789-NEXT: ;;#ASMSTART
953 ; GFX789-NEXT: ;;#ASMEND
954 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
955 ;
956 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_64:
957 ; GFX10: ; %bb.0:
958 ; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
959 ; GFX10-NEXT: ;;#ASMSTART
960 ; GFX10-NEXT: ;;#ASMEND
961 ; GFX10-NEXT: s_denorm_mode 4 ; encoding: [0x04,0x00,0xa5,0xbf]
962 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
963 call void @llvm.amdgcn.s.setreg(i32 14337, i32 64)
964 call void asm sideeffect "", ""()
965 ret void
966 }
968 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128() {
969 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:
970 ; GFX6: ; %bb.0:
971 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x80,0xba,0x80,0x00,0x00,0x00]
972 ; GFX6-NEXT: ;;#ASMSTART
973 ; GFX6-NEXT: ;;#ASMEND
974 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
975 ;
976 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:
977 ; GFX789: ; %bb.0:
978 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x80 ; encoding: [0x01,0x38,0x00,0xba,0x80,0x00,0x00,0x00]
979 ; GFX789-NEXT: ;;#ASMSTART
980 ; GFX789-NEXT: ;;#ASMEND
981 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
982 ;
983 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_128:
984 ; GFX10: ; %bb.0:
985 ; GFX10-NEXT: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf]
986 ; GFX10-NEXT: ;;#ASMSTART
987 ; GFX10-NEXT: ;;#ASMEND
988 ; GFX10-NEXT: s_denorm_mode 8 ; encoding: [0x08,0x00,0xa5,0xbf]
989 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
990 call void @llvm.amdgcn.s.setreg(i32 14337, i32 128)
991 call void asm sideeffect "", ""()
992 ret void
993 }
995 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15() {
996 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:
997 ; GFX6: ; %bb.0:
998 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x80,0xba,0x0f,0x00,0x00,0x00]
999 ; GFX6-NEXT: ;;#ASMSTART
1000 ; GFX6-NEXT: ;;#ASMEND
1001 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1002 ;
1003 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:
1004 ; GFX789: ; %bb.0:
1005 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 15 ; encoding: [0x01,0x38,0x00,0xba,0x0f,0x00,0x00,0x00]
1006 ; GFX789-NEXT: ;;#ASMSTART
1007 ; GFX789-NEXT: ;;#ASMEND
1008 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1009 ;
1010 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_15:
1011 ; GFX10: ; %bb.0:
1012 ; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]
1013 ; GFX10-NEXT: ;;#ASMSTART
1014 ; GFX10-NEXT: ;;#ASMEND
1015 ; GFX10-NEXT: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf]
1016 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1017 call void @llvm.amdgcn.s.setreg(i32 14337, i32 15)
1018 call void asm sideeffect "", ""()
1019 ret void
1020 }
1022 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255() {
1023 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:
1024 ; GFX6: ; %bb.0:
1025 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x80,0xba,0xff,0x00,0x00,0x00]
1026 ; GFX6-NEXT: ;;#ASMSTART
1027 ; GFX6-NEXT: ;;#ASMEND
1028 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1029 ;
1030 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:
1031 ; GFX789: ; %bb.0:
1032 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0xff ; encoding: [0x01,0x38,0x00,0xba,0xff,0x00,0x00,0x00]
1033 ; GFX789-NEXT: ;;#ASMSTART
1034 ; GFX789-NEXT: ;;#ASMEND
1035 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1036 ;
1037 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_255:
1038 ; GFX10: ; %bb.0:
1039 ; GFX10-NEXT: s_round_mode 0xf ; encoding: [0x0f,0x00,0xa4,0xbf]
1040 ; GFX10-NEXT: ;;#ASMSTART
1041 ; GFX10-NEXT: ;;#ASMEND
1042 ; GFX10-NEXT: s_denorm_mode 15 ; encoding: [0x0f,0x00,0xa5,0xbf]
1043 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1044 call void @llvm.amdgcn.s.setreg(i32 14337, i32 255)
1045 call void asm sideeffect "", ""()
1046 ret void
1047 }
1049 ; Truncate extra high bit
1050 define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597() {
1051 ; GFX6-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:
1052 ; GFX6: ; %bb.0:
1053 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x80,0xba,0x55,0x02,0x00,0x00]
1054 ; GFX6-NEXT: ;;#ASMSTART
1055 ; GFX6-NEXT: ;;#ASMEND
1056 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1057 ;
1058 ; GFX789-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:
1059 ; GFX789: ; %bb.0:
1060 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 8), 0x255 ; encoding: [0x01,0x38,0x00,0xba,0x55,0x02,0x00,0x00]
1061 ; GFX789-NEXT: ;;#ASMSTART
1062 ; GFX789-NEXT: ;;#ASMEND
1063 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1064 ;
1065 ; GFX10-LABEL: test_setreg_full_both_round_mode_and_denorm_mode_597:
1066 ; GFX10: ; %bb.0:
1067 ; GFX10-NEXT: s_round_mode 0x5 ; encoding: [0x05,0x00,0xa4,0xbf]
1068 ; GFX10-NEXT: ;;#ASMSTART
1069 ; GFX10-NEXT: ;;#ASMEND
1070 ; GFX10-NEXT: s_denorm_mode 5 ; encoding: [0x05,0x00,0xa5,0xbf]
1071 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1072 call void @llvm.amdgcn.s.setreg(i32 14337, i32 597)
1073 call void asm sideeffect "", ""()
1074 ret void
1075 }
1077 define amdgpu_kernel void @test_setreg_set_8_bits_straddles_round_and_denorm() {
1078 ; GFX6-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:
1079 ; GFX6: ; %bb.0:
1080 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0x00,0x00]
1081 ; GFX6-NEXT: ;;#ASMSTART
1082 ; GFX6-NEXT: ;;#ASMEND
1083 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1084 ;
1085 ; GFX789-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:
1086 ; GFX789: ; %bb.0:
1087 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x00,0xba,0xff,0x00,0x00,0x00]
1088 ; GFX789-NEXT: ;;#ASMSTART
1089 ; GFX789-NEXT: ;;#ASMEND
1090 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1091 ;
1092 ; GFX10-LABEL: test_setreg_set_8_bits_straddles_round_and_denorm:
1093 ; GFX10: ; %bb.0:
1094 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 8), 0xff ; encoding: [0x81,0x38,0x80,0xba,0xff,0x00,0x00,0x00]
1095 ; GFX10-NEXT: ;;#ASMSTART
1096 ; GFX10-NEXT: ;;#ASMEND
1097 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1098 call void @llvm.amdgcn.s.setreg(i32 14465, i32 255)
1099 call void asm sideeffect "", ""()
1100 ret void
1101 }
1103 define amdgpu_kernel void @test_setreg_set_4_bits_straddles_round_and_denorm() {
1104 ; GFX6-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm:
1105 ; GFX6: ; %bb.0:
1106 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]
1107 ; GFX6-NEXT: ;;#ASMSTART
1108 ; GFX6-NEXT: ;;#ASMEND
1109 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1110 ;
1111 ; GFX789-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm:
1112 ; GFX789: ; %bb.0:
1113 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x00,0xba,0x0f,0x00,0x00,0x00]
1114 ; GFX789-NEXT: ;;#ASMSTART
1115 ; GFX789-NEXT: ;;#ASMEND
1116 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1117 ;
1118 ; GFX10-LABEL: test_setreg_set_4_bits_straddles_round_and_denorm:
1119 ; GFX10: ; %bb.0:
1120 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 15 ; encoding: [0x81,0x18,0x80,0xba,0x0f,0x00,0x00,0x00]
1121 ; GFX10-NEXT: ;;#ASMSTART
1122 ; GFX10-NEXT: ;;#ASMEND
1123 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
1124 call void @llvm.amdgcn.s.setreg(i32 6273, i32 15)
1125 call void asm sideeffect "", ""()
1126 ret void
1127 }
1129 ; FIXME: Broken for DAG
1130 define void @test_setreg_roundingmode_var_vgpr(i32 %var.mode) {
1131 ; GFX6-LABEL: test_setreg_roundingmode_var_vgpr:
1132 ; GFX6: ; %bb.0:
1133 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
1134 ; GFX6-NEXT: v_readfirstlane_b32 s4, v0 ; encoding: [0x00,0x05,0x08,0x7e]
1135 ; GFX6-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 3), s4 ; encoding: [0x01,0x10,0x84,0xb9]
1136 ; GFX6-NEXT: ;;#ASMSTART
1137 ; GFX6-NEXT: ;;#ASMEND
1138 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
1139 ;
1140 ; GFX789-LABEL: test_setreg_roundingmode_var_vgpr:
1141 ; GFX789: ; %bb.0:
1142 ; GFX789-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
1143 ; GFX789-NEXT: v_readfirstlane_b32 s4, v0 ; encoding: [0x00,0x05,0x08,0x7e]
1144 ; GFX789-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 3), s4 ; encoding: [0x01,0x10,0x04,0xb9]
1145 ; GFX789-NEXT: ;;#ASMSTART
1146 ; GFX789-NEXT: ;;#ASMEND
1147 ; GFX789-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x1d,0x80,0xbe]
1148 ;
1149 ; GFX10-LABEL: test_setreg_roundingmode_var_vgpr:
1150 ; GFX10: ; %bb.0:
1151 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
1152 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
1153 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0 ; encoding: [0x00,0x05,0x08,0x7e]
1154 ; GFX10-NEXT: ;;#ASMSTART
1155 ; GFX10-NEXT: ;;#ASMEND
1156 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_MODE, 0, 3), s4 ; encoding: [0x01,0x10,0x84,0xb9]
1157 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
1158 call void @llvm.amdgcn.s.setreg(i32 4097, i32 %var.mode)
1159 call void asm sideeffect "", ""()
1160 ret void
1161 }
1163 declare void @llvm.amdgcn.s.setreg(i32 immarg, i32) #0
1165 attributes #0 = { nounwind }