llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
   3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
   4
   5 ---
   6 name: ds_gws_init_s
   7 legalized: true
   8 tracksRegLiveness: true
   9
  10 body: |
  11   bb.0:
  12     liveins: $sgpr0
  13     ; CHECK-LABEL: name: ds_gws_init_s
  14     ; CHECK: liveins: $sgpr0
  15     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  16     ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), [[COPY]](s32)
  17     %0:_(s32) = COPY $sgpr0
  18     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), %0
  19 ...
  20
  21 ---
  22 name: ds_gws_init_v
  23 legalized: true
  24 tracksRegLiveness: true
  25
  26 body: |
  27   bb.0:
  28     liveins: $vgpr0
  29     ; CHECK-LABEL: name: ds_gws_init_v
  30     ; CHECK: liveins: $vgpr0
  31     ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
  32     ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
  33     ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), [[V_READFIRSTLANE_B32_]](s32)
  34     %0:_(s32) = COPY $vgpr0
  35     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), %0
  36 ...
  37