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[AMDGPU] Test codegen'ing True16 additions.
[llvm-project.git] / llvm / lib / TargetParser / Host.cpp
blobcdb1f72ae39b9fcc57501bd94e04810fe3b44fc8
1 //===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the operating system Host detection.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/TargetParser/Host.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringMap.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/Config/llvm-config.h"
19 #include "llvm/Support/MemoryBuffer.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/TargetParser/Triple.h"
22 #include "llvm/TargetParser/X86TargetParser.h"
23 #include <string.h>
24
25 // Include the platform-specific parts of this class.
26 #ifdef LLVM_ON_UNIX
27 #include "Unix/Host.inc"
28 #include <sched.h>
29 #endif
30 #ifdef _WIN32
31 #include "Windows/Host.inc"
32 #endif
33 #ifdef _MSC_VER
34 #include <intrin.h>
35 #endif
36 #ifdef __MVS__
37 #include "llvm/Support/BCD.h"
38 #endif
39 #if defined(__APPLE__)
40 #include <mach/host_info.h>
41 #include <mach/mach.h>
42 #include <mach/mach_host.h>
43 #include <mach/machine.h>
44 #include <sys/param.h>
45 #include <sys/sysctl.h>
46 #endif
47 #ifdef _AIX
48 #include <sys/systemcfg.h>
49 #endif
50 #if defined(__sun__) && defined(__svr4__)
51 #include <kstat.h>
52 #endif
53
54 #define DEBUG_TYPE "host-detection"
55
56 //===----------------------------------------------------------------------===//
57 //
58 // Implementations of the CPU detection routines
59 //
60 //===----------------------------------------------------------------------===//
61
62 using namespace llvm;
63
64 static std::unique_ptr<llvm::MemoryBuffer>
65 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
66 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
67 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
68 if (std::error_code EC = Text.getError()) {
69 llvm::errs() << "Can't read "
70 << "/proc/cpuinfo: " << EC.message() << "\n";
71 return nullptr;
72 }
73 return std::move(*Text);
74 }
75
76 StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) {
77 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
78 // and so we must use an operating-system interface to determine the current
79 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
80 const char *generic = "generic";
81
82 // The cpu line is second (after the 'processor: 0' line), so if this
83 // buffer is too small then something has changed (or is wrong).
84 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
85 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
86
87 StringRef::const_iterator CIP = CPUInfoStart;
88
89 StringRef::const_iterator CPUStart = nullptr;
90 size_t CPULen = 0;
91
92 // We need to find the first line which starts with cpu, spaces, and a colon.
93 // After the colon, there may be some additional spaces and then the cpu type.
94 while (CIP < CPUInfoEnd && CPUStart == nullptr) {
95 if (CIP < CPUInfoEnd && *CIP == '\n')
96 ++CIP;
97
98 if (CIP < CPUInfoEnd && *CIP == 'c') {
99 ++CIP;
100 if (CIP < CPUInfoEnd && *CIP == 'p') {
101 ++CIP;
102 if (CIP < CPUInfoEnd && *CIP == 'u') {
103 ++CIP;
104 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
105 ++CIP;
106
107 if (CIP < CPUInfoEnd && *CIP == ':') {
108 ++CIP;
109 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
110 ++CIP;
111
112 if (CIP < CPUInfoEnd) {
113 CPUStart = CIP;
114 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
115 *CIP != ',' && *CIP != '\n'))
116 ++CIP;
117 CPULen = CIP - CPUStart;
118 }
119 }
120 }
121 }
122 }
123
124 if (CPUStart == nullptr)
125 while (CIP < CPUInfoEnd && *CIP != '\n')
126 ++CIP;
127 }
128
129 if (CPUStart == nullptr)
130 return generic;
131
132 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
133 .Case("604e", "604e")
134 .Case("604", "604")
135 .Case("7400", "7400")
136 .Case("7410", "7400")
137 .Case("7447", "7400")
138 .Case("7455", "7450")
139 .Case("G4", "g4")
140 .Case("POWER4", "970")
141 .Case("PPC970FX", "970")
142 .Case("PPC970MP", "970")
143 .Case("G5", "g5")
144 .Case("POWER5", "g5")
145 .Case("A2", "a2")
146 .Case("POWER6", "pwr6")
147 .Case("POWER7", "pwr7")
148 .Case("POWER8", "pwr8")
149 .Case("POWER8E", "pwr8")
150 .Case("POWER8NVL", "pwr8")
151 .Case("POWER9", "pwr9")
152 .Case("POWER10", "pwr10")
153 // FIXME: If we get a simulator or machine with the capabilities of
154 // mcpu=future, we should revisit this and add the name reported by the
155 // simulator/machine.
156 .Default(generic);
157 }
158
159 StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
160 // The cpuid register on arm is not accessible from user space. On Linux,
161 // it is exposed through the /proc/cpuinfo file.
162
163 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
164 // in all cases.
165 SmallVector<StringRef, 32> Lines;
166 ProcCpuinfoContent.split(Lines, "\n");
167
168 // Look for the CPU implementer line.
169 StringRef Implementer;
170 StringRef Hardware;
171 StringRef Part;
172 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
173 if (Lines[I].startswith("CPU implementer"))
174 Implementer = Lines[I].substr(15).ltrim("\t :");
175 if (Lines[I].startswith("Hardware"))
176 Hardware = Lines[I].substr(8).ltrim("\t :");
177 if (Lines[I].startswith("CPU part"))
178 Part = Lines[I].substr(8).ltrim("\t :");
179 }
180
181 if (Implementer == "0x41") { // ARM Ltd.
182 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
183 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
184 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
185 return "cortex-a53";
186
187
188 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
189 // values correspond to the "Part number" in the CP15/c0 register. The
190 // contents are specified in the various processor manuals.
191 // This corresponds to the Main ID Register in Technical Reference Manuals.
192 // and is used in programs like sys-utils
193 return StringSwitch<const char *>(Part)
194 .Case("0x926", "arm926ej-s")
195 .Case("0xb02", "mpcore")
196 .Case("0xb36", "arm1136j-s")
197 .Case("0xb56", "arm1156t2-s")
198 .Case("0xb76", "arm1176jz-s")
199 .Case("0xc08", "cortex-a8")
200 .Case("0xc09", "cortex-a9")
201 .Case("0xc0f", "cortex-a15")
202 .Case("0xc20", "cortex-m0")
203 .Case("0xc23", "cortex-m3")
204 .Case("0xc24", "cortex-m4")
205 .Case("0xd22", "cortex-m55")
206 .Case("0xd02", "cortex-a34")
207 .Case("0xd04", "cortex-a35")
208 .Case("0xd03", "cortex-a53")
209 .Case("0xd05", "cortex-a55")
210 .Case("0xd46", "cortex-a510")
211 .Case("0xd07", "cortex-a57")
212 .Case("0xd08", "cortex-a72")
213 .Case("0xd09", "cortex-a73")
214 .Case("0xd0a", "cortex-a75")
215 .Case("0xd0b", "cortex-a76")
216 .Case("0xd0d", "cortex-a77")
217 .Case("0xd41", "cortex-a78")
218 .Case("0xd47", "cortex-a710")
219 .Case("0xd4d", "cortex-a715")
220 .Case("0xd44", "cortex-x1")
221 .Case("0xd4c", "cortex-x1c")
222 .Case("0xd48", "cortex-x2")
223 .Case("0xd4e", "cortex-x3")
224 .Case("0xd0c", "neoverse-n1")
225 .Case("0xd49", "neoverse-n2")
226 .Case("0xd40", "neoverse-v1")
227 .Case("0xd4f", "neoverse-v2")
228 .Default("generic");
229 }
230
231 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
232 return StringSwitch<const char *>(Part)
233 .Case("0x516", "thunderx2t99")
234 .Case("0x0516", "thunderx2t99")
235 .Case("0xaf", "thunderx2t99")
236 .Case("0x0af", "thunderx2t99")
237 .Case("0xa1", "thunderxt88")
238 .Case("0x0a1", "thunderxt88")
239 .Default("generic");
240 }
241
242 if (Implementer == "0x46") { // Fujitsu Ltd.
243 return StringSwitch<const char *>(Part)
244 .Case("0x001", "a64fx")
245 .Default("generic");
246 }
247
248 if (Implementer == "0x4e") { // NVIDIA Corporation
249 return StringSwitch<const char *>(Part)
250 .Case("0x004", "carmel")
251 .Default("generic");
252 }
253
254 if (Implementer == "0x48") // HiSilicon Technologies, Inc.
255 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
256 // values correspond to the "Part number" in the CP15/c0 register. The
257 // contents are specified in the various processor manuals.
258 return StringSwitch<const char *>(Part)
259 .Case("0xd01", "tsv110")
260 .Default("generic");
261
262 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
263 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
264 // values correspond to the "Part number" in the CP15/c0 register. The
265 // contents are specified in the various processor manuals.
266 return StringSwitch<const char *>(Part)
267 .Case("0x06f", "krait") // APQ8064
268 .Case("0x201", "kryo")
269 .Case("0x205", "kryo")
270 .Case("0x211", "kryo")
271 .Case("0x800", "cortex-a73") // Kryo 2xx Gold
272 .Case("0x801", "cortex-a73") // Kryo 2xx Silver
273 .Case("0x802", "cortex-a75") // Kryo 3xx Gold
274 .Case("0x803", "cortex-a75") // Kryo 3xx Silver
275 .Case("0x804", "cortex-a76") // Kryo 4xx Gold
276 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
277 .Case("0xc00", "falkor")
278 .Case("0xc01", "saphira")
279 .Default("generic");
280 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
281 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
282 // any predictive pattern across variants and parts.
283 unsigned Variant = 0, Part = 0;
284
285 // Look for the CPU variant line, whose value is a 1 digit hexadecimal
286 // number, corresponding to the Variant bits in the CP15/C0 register.
287 for (auto I : Lines)
288 if (I.consume_front("CPU variant"))
289 I.ltrim("\t :").getAsInteger(0, Variant);
290
291 // Look for the CPU part line, whose value is a 3 digit hexadecimal
292 // number, corresponding to the PartNum bits in the CP15/C0 register.
293 for (auto I : Lines)
294 if (I.consume_front("CPU part"))
295 I.ltrim("\t :").getAsInteger(0, Part);
296
297 unsigned Exynos = (Variant << 12) | Part;
298 switch (Exynos) {
299 default:
300 // Default by falling through to Exynos M3.
301 [[fallthrough]];
302 case 0x1002:
303 return "exynos-m3";
304 case 0x1003:
305 return "exynos-m4";
306 }
307 }
308
309 if (Implementer == "0xc0") { // Ampere Computing
310 return StringSwitch<const char *>(Part)
311 .Case("0xac3", "ampere1")
312 .Case("0xac4", "ampere1a")
313 .Default("generic");
314 }
315
316 return "generic";
317 }
318
319 namespace {
320 StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
321 switch (Id) {
322 case 2064: // z900 not supported by LLVM
323 case 2066:
324 case 2084: // z990 not supported by LLVM
325 case 2086:
326 case 2094: // z9-109 not supported by LLVM
327 case 2096:
328 return "generic";
329 case 2097:
330 case 2098:
331 return "z10";
332 case 2817:
333 case 2818:
334 return "z196";
335 case 2827:
336 case 2828:
337 return "zEC12";
338 case 2964:
339 case 2965:
340 return HaveVectorSupport? "z13" : "zEC12";
341 case 3906:
342 case 3907:
343 return HaveVectorSupport? "z14" : "zEC12";
344 case 8561:
345 case 8562:
346 return HaveVectorSupport? "z15" : "zEC12";
347 case 3931:
348 case 3932:
349 default:
350 return HaveVectorSupport? "z16" : "zEC12";
351 }
352 }
353 } // end anonymous namespace
354
355 StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) {
356 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
357
358 // The "processor 0:" line comes after a fair amount of other information,
359 // including a cache breakdown, but this should be plenty.
360 SmallVector<StringRef, 32> Lines;
361 ProcCpuinfoContent.split(Lines, "\n");
362
363 // Look for the CPU features.
364 SmallVector<StringRef, 32> CPUFeatures;
365 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
366 if (Lines[I].startswith("features")) {
367 size_t Pos = Lines[I].find(':');
368 if (Pos != StringRef::npos) {
369 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
370 break;
371 }
372 }
373
374 // We need to check for the presence of vector support independently of
375 // the machine type, since we may only use the vector register set when
376 // supported by the kernel (and hypervisor).
377 bool HaveVectorSupport = false;
378 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
379 if (CPUFeatures[I] == "vx")
380 HaveVectorSupport = true;
381 }
382
383 // Now check the processor machine type.
384 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
385 if (Lines[I].startswith("processor ")) {
386 size_t Pos = Lines[I].find("machine = ");
387 if (Pos != StringRef::npos) {
388 Pos += sizeof("machine = ") - 1;
389 unsigned int Id;
390 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id))
391 return getCPUNameFromS390Model(Id, HaveVectorSupport);
392 }
393 break;
394 }
395 }
396
397 return "generic";
398 }
399
400 StringRef sys::detail::getHostCPUNameForRISCV(StringRef ProcCpuinfoContent) {
401 // There are 24 lines in /proc/cpuinfo
402 SmallVector<StringRef> Lines;
403 ProcCpuinfoContent.split(Lines, "\n");
404
405 // Look for uarch line to determine cpu name
406 StringRef UArch;
407 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
408 if (Lines[I].startswith("uarch")) {
409 UArch = Lines[I].substr(5).ltrim("\t :");
410 break;
411 }
412 }
413
414 return StringSwitch<const char *>(UArch)
415 .Case("sifive,u74-mc", "sifive-u74")
416 .Case("sifive,bullet0", "sifive-u74")
417 .Default("generic");
418 }
419
420 StringRef sys::detail::getHostCPUNameForBPF() {
421 #if !defined(__linux__) || !defined(__x86_64__)
422 return "generic";
423 #else
424 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
425 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
426 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
427 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
428 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
429 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
430 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
431 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
432 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
433 /* BPF_EXIT_INSN() */
434 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
435
436 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
437 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
438 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
439 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
440 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
441 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
442 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
443 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
444 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
445 /* BPF_EXIT_INSN() */
446 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
447
448 struct bpf_prog_load_attr {
449 uint32_t prog_type;
450 uint32_t insn_cnt;
451 uint64_t insns;
452 uint64_t license;
453 uint32_t log_level;
454 uint32_t log_size;
455 uint64_t log_buf;
456 uint32_t kern_version;
457 uint32_t prog_flags;
458 } attr = {};
459 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
460 attr.insn_cnt = 5;
461 attr.insns = (uint64_t)v3_insns;
462 attr.license = (uint64_t)"DUMMY";
463
464 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
465 sizeof(attr));
466 if (fd >= 0) {
467 close(fd);
468 return "v3";
469 }
470
471 /* Clear the whole attr in case its content changed by syscall. */
472 memset(&attr, 0, sizeof(attr));
473 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
474 attr.insn_cnt = 5;
475 attr.insns = (uint64_t)v2_insns;
476 attr.license = (uint64_t)"DUMMY";
477 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
478 if (fd >= 0) {
479 close(fd);
480 return "v2";
481 }
482 return "v1";
483 #endif
484 }
485
486 #if defined(__i386__) || defined(_M_IX86) || \
487 defined(__x86_64__) || defined(_M_X64)
488
489 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
490 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
491 // support. Consequently, for i386, the presence of CPUID is checked first
492 // via the corresponding eflags bit.
493 // Removal of cpuid.h header motivated by PR30384
494 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
495 // or test-suite, but are used in external projects e.g. libstdcxx
496 static bool isCpuIdSupported() {
497 #if defined(__GNUC__) || defined(__clang__)
498 #if defined(__i386__)
499 int __cpuid_supported;
500 __asm__(" pushfl\n"
501 " popl %%eax\n"
502 " movl %%eax,%%ecx\n"
503 " xorl $0x00200000,%%eax\n"
504 " pushl %%eax\n"
505 " popfl\n"
506 " pushfl\n"
507 " popl %%eax\n"
508 " movl $0,%0\n"
509 " cmpl %%eax,%%ecx\n"
510 " je 1f\n"
511 " movl $1,%0\n"
512 "1:"
513 : "=r"(__cpuid_supported)
514 :
515 : "eax", "ecx");
516 if (!__cpuid_supported)
517 return false;
518 #endif
519 return true;
520 #endif
521 return true;
522 }
523
524 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
525 /// the specified arguments. If we can't run cpuid on the host, return true.
526 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
527 unsigned *rECX, unsigned *rEDX) {
528 #if defined(__GNUC__) || defined(__clang__)
529 #if defined(__x86_64__)
530 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
531 // FIXME: should we save this for Clang?
532 __asm__("movq\t%%rbx, %%rsi\n\t"
533 "cpuid\n\t"
534 "xchgq\t%%rbx, %%rsi\n\t"
535 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
536 : "a"(value));
537 return false;
538 #elif defined(__i386__)
539 __asm__("movl\t%%ebx, %%esi\n\t"
540 "cpuid\n\t"
541 "xchgl\t%%ebx, %%esi\n\t"
542 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
543 : "a"(value));
544 return false;
545 #else
546 return true;
547 #endif
548 #elif defined(_MSC_VER)
549 // The MSVC intrinsic is portable across x86 and x64.
550 int registers[4];
551 __cpuid(registers, value);
552 *rEAX = registers[0];
553 *rEBX = registers[1];
554 *rECX = registers[2];
555 *rEDX = registers[3];
556 return false;
557 #else
558 return true;
559 #endif
560 }
561
562 namespace llvm {
563 namespace sys {
564 namespace detail {
565 namespace x86 {
566
567 VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
568 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
569 if (MaxLeaf == nullptr)
570 MaxLeaf = &EAX;
571 else
572 *MaxLeaf = 0;
573
574 if (!isCpuIdSupported())
575 return VendorSignatures::UNKNOWN;
576
577 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
578 return VendorSignatures::UNKNOWN;
579
580 // "Genu ineI ntel"
581 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
582 return VendorSignatures::GENUINE_INTEL;
583
584 // "Auth enti cAMD"
585 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
586 return VendorSignatures::AUTHENTIC_AMD;
587
588 return VendorSignatures::UNKNOWN;
589 }
590
591 } // namespace x86
592 } // namespace detail
593 } // namespace sys
594 } // namespace llvm
595
596 using namespace llvm::sys::detail::x86;
597
598 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
599 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
600 /// return true.
601 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
602 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
603 unsigned *rEDX) {
604 #if defined(__GNUC__) || defined(__clang__)
605 #if defined(__x86_64__)
606 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
607 // FIXME: should we save this for Clang?
608 __asm__("movq\t%%rbx, %%rsi\n\t"
609 "cpuid\n\t"
610 "xchgq\t%%rbx, %%rsi\n\t"
611 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
612 : "a"(value), "c"(subleaf));
613 return false;
614 #elif defined(__i386__)
615 __asm__("movl\t%%ebx, %%esi\n\t"
616 "cpuid\n\t"
617 "xchgl\t%%ebx, %%esi\n\t"
618 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
619 : "a"(value), "c"(subleaf));
620 return false;
621 #else
622 return true;
623 #endif
624 #elif defined(_MSC_VER)
625 int registers[4];
626 __cpuidex(registers, value, subleaf);
627 *rEAX = registers[0];
628 *rEBX = registers[1];
629 *rECX = registers[2];
630 *rEDX = registers[3];
631 return false;
632 #else
633 return true;
634 #endif
635 }
636
637 // Read control register 0 (XCR0). Used to detect features such as AVX.
638 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
639 #if defined(__GNUC__) || defined(__clang__)
640 // Check xgetbv; this uses a .byte sequence instead of the instruction
641 // directly because older assemblers do not include support for xgetbv and
642 // there is no easy way to conditionally compile based on the assembler used.
643 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
644 return false;
645 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
646 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
647 *rEAX = Result;
648 *rEDX = Result >> 32;
649 return false;
650 #else
651 return true;
652 #endif
653 }
654
655 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
656 unsigned *Model) {
657 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
658 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
659 if (*Family == 6 || *Family == 0xf) {
660 if (*Family == 0xf)
661 // Examine extended family ID if family ID is F.
662 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
663 // Examine extended model ID if family ID is 6 or F.
664 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
665 }
666 }
667
668 static StringRef
669 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
670 const unsigned *Features,
671 unsigned *Type, unsigned *Subtype) {
672 auto testFeature = [&](unsigned F) {
673 return (Features[F / 32] & (1U << (F % 32))) != 0;
674 };
675
676 StringRef CPU;
677
678 switch (Family) {
679 case 3:
680 CPU = "i386";
681 break;
682 case 4:
683 CPU = "i486";
684 break;
685 case 5:
686 if (testFeature(X86::FEATURE_MMX)) {
687 CPU = "pentium-mmx";
688 break;
689 }
690 CPU = "pentium";
691 break;
692 case 6:
693 switch (Model) {
694 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
695 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
696 // mobile processor, Intel Core 2 Extreme processor, Intel
697 // Pentium Dual-Core processor, Intel Xeon processor, model
698 // 0Fh. All processors are manufactured using the 65 nm process.
699 case 0x16: // Intel Celeron processor model 16h. All processors are
700 // manufactured using the 65 nm process
701 CPU = "core2";
702 *Type = X86::INTEL_CORE2;
703 break;
704 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
705 // 17h. All processors are manufactured using the 45 nm process.
706 //
707 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
708 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
709 // the 45 nm process.
710 CPU = "penryn";
711 *Type = X86::INTEL_CORE2;
712 break;
713 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
714 // processors are manufactured using the 45 nm process.
715 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
716 // As found in a Summer 2010 model iMac.
717 case 0x1f:
718 case 0x2e: // Nehalem EX
719 CPU = "nehalem";
720 *Type = X86::INTEL_COREI7;
721 *Subtype = X86::INTEL_COREI7_NEHALEM;
722 break;
723 case 0x25: // Intel Core i7, laptop version.
724 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
725 // processors are manufactured using the 32 nm process.
726 case 0x2f: // Westmere EX
727 CPU = "westmere";
728 *Type = X86::INTEL_COREI7;
729 *Subtype = X86::INTEL_COREI7_WESTMERE;
730 break;
731 case 0x2a: // Intel Core i7 processor. All processors are manufactured
732 // using the 32 nm process.
733 case 0x2d:
734 CPU = "sandybridge";
735 *Type = X86::INTEL_COREI7;
736 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
737 break;
738 case 0x3a:
739 case 0x3e: // Ivy Bridge EP
740 CPU = "ivybridge";
741 *Type = X86::INTEL_COREI7;
742 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
743 break;
744
745 // Haswell:
746 case 0x3c:
747 case 0x3f:
748 case 0x45:
749 case 0x46:
750 CPU = "haswell";
751 *Type = X86::INTEL_COREI7;
752 *Subtype = X86::INTEL_COREI7_HASWELL;
753 break;
754
755 // Broadwell:
756 case 0x3d:
757 case 0x47:
758 case 0x4f:
759 case 0x56:
760 CPU = "broadwell";
761 *Type = X86::INTEL_COREI7;
762 *Subtype = X86::INTEL_COREI7_BROADWELL;
763 break;
764
765 // Skylake:
766 case 0x4e: // Skylake mobile
767 case 0x5e: // Skylake desktop
768 case 0x8e: // Kaby Lake mobile
769 case 0x9e: // Kaby Lake desktop
770 case 0xa5: // Comet Lake-H/S
771 case 0xa6: // Comet Lake-U
772 CPU = "skylake";
773 *Type = X86::INTEL_COREI7;
774 *Subtype = X86::INTEL_COREI7_SKYLAKE;
775 break;
776
777 // Rocketlake:
778 case 0xa7:
779 CPU = "rocketlake";
780 *Type = X86::INTEL_COREI7;
781 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
782 break;
783
784 // Skylake Xeon:
785 case 0x55:
786 *Type = X86::INTEL_COREI7;
787 if (testFeature(X86::FEATURE_AVX512BF16)) {
788 CPU = "cooperlake";
789 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
790 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
791 CPU = "cascadelake";
792 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
793 } else {
794 CPU = "skylake-avx512";
795 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
796 }
797 break;
798
799 // Cannonlake:
800 case 0x66:
801 CPU = "cannonlake";
802 *Type = X86::INTEL_COREI7;
803 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
804 break;
805
806 // Icelake:
807 case 0x7d:
808 case 0x7e:
809 CPU = "icelake-client";
810 *Type = X86::INTEL_COREI7;
811 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
812 break;
813
814 // Tigerlake:
815 case 0x8c:
816 case 0x8d:
817 CPU = "tigerlake";
818 *Type = X86::INTEL_COREI7;
819 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
820 break;
821
822 // Alderlake:
823 case 0x97:
824 case 0x9a:
825 // Gracemont
826 case 0xbe:
827 // Raptorlake:
828 case 0xb7:
829 case 0xba:
830 case 0xbf:
831 // Meteorlake:
832 case 0xaa:
833 case 0xac:
834 CPU = "alderlake";
835 *Type = X86::INTEL_COREI7;
836 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
837 break;
838
839 // Arrowlake:
840 case 0xc5:
841 CPU = "arrowlake";
842 *Type = X86::INTEL_COREI7;
843 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
844 break;
845
846 // Arrowlake S:
847 case 0xc6:
848 // Lunarlake:
849 case 0xbd:
850 CPU = "arrowlake-s";
851 *Type = X86::INTEL_COREI7;
852 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
853 break;
854
855 // Graniterapids:
856 case 0xad:
857 CPU = "graniterapids";
858 *Type = X86::INTEL_COREI7;
859 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
860 break;
861
862 // Granite Rapids D:
863 case 0xae:
864 CPU = "graniterapids-d";
865 *Type = X86::INTEL_COREI7;
866 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
867 break;
868
869 // Icelake Xeon:
870 case 0x6a:
871 case 0x6c:
872 CPU = "icelake-server";
873 *Type = X86::INTEL_COREI7;
874 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
875 break;
876
877 // Emerald Rapids:
878 case 0xcf:
879 // Sapphire Rapids:
880 case 0x8f:
881 CPU = "sapphirerapids";
882 *Type = X86::INTEL_COREI7;
883 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
884 break;
885
886 case 0x1c: // Most 45 nm Intel Atom processors
887 case 0x26: // 45 nm Atom Lincroft
888 case 0x27: // 32 nm Atom Medfield
889 case 0x35: // 32 nm Atom Midview
890 case 0x36: // 32 nm Atom Midview
891 CPU = "bonnell";
892 *Type = X86::INTEL_BONNELL;
893 break;
894
895 // Atom Silvermont codes from the Intel software optimization guide.
896 case 0x37:
897 case 0x4a:
898 case 0x4d:
899 case 0x5a:
900 case 0x5d:
901 case 0x4c: // really airmont
902 CPU = "silvermont";
903 *Type = X86::INTEL_SILVERMONT;
904 break;
905 // Goldmont:
906 case 0x5c: // Apollo Lake
907 case 0x5f: // Denverton
908 CPU = "goldmont";
909 *Type = X86::INTEL_GOLDMONT;
910 break;
911 case 0x7a:
912 CPU = "goldmont-plus";
913 *Type = X86::INTEL_GOLDMONT_PLUS;
914 break;
915 case 0x86:
916 case 0x8a: // Lakefield
917 case 0x96: // Elkhart Lake
918 case 0x9c: // Jasper Lake
919 CPU = "tremont";
920 *Type = X86::INTEL_TREMONT;
921 break;
922
923 // Sierraforest:
924 case 0xaf:
925 CPU = "sierraforest";
926 *Type = X86::INTEL_SIERRAFOREST;
927 break;
928
929 // Grandridge:
930 case 0xb6:
931 CPU = "grandridge";
932 *Type = X86::INTEL_GRANDRIDGE;
933 break;
934
935 // Xeon Phi (Knights Landing + Knights Mill):
936 case 0x57:
937 CPU = "knl";
938 *Type = X86::INTEL_KNL;
939 break;
940 case 0x85:
941 CPU = "knm";
942 *Type = X86::INTEL_KNM;
943 break;
944
945 default: // Unknown family 6 CPU, try to guess.
946 // Don't both with Type/Subtype here, they aren't used by the caller.
947 // They're used above to keep the code in sync with compiler-rt.
948 // TODO detect tigerlake host from model
949 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
950 CPU = "tigerlake";
951 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
952 CPU = "icelake-client";
953 } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
954 CPU = "cannonlake";
955 } else if (testFeature(X86::FEATURE_AVX512BF16)) {
956 CPU = "cooperlake";
957 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
958 CPU = "cascadelake";
959 } else if (testFeature(X86::FEATURE_AVX512VL)) {
960 CPU = "skylake-avx512";
961 } else if (testFeature(X86::FEATURE_AVX512ER)) {
962 CPU = "knl";
963 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
964 if (testFeature(X86::FEATURE_SHA))
965 CPU = "goldmont";
966 else
967 CPU = "skylake";
968 } else if (testFeature(X86::FEATURE_ADX)) {
969 CPU = "broadwell";
970 } else if (testFeature(X86::FEATURE_AVX2)) {
971 CPU = "haswell";
972 } else if (testFeature(X86::FEATURE_AVX)) {
973 CPU = "sandybridge";
974 } else if (testFeature(X86::FEATURE_SSE4_2)) {
975 if (testFeature(X86::FEATURE_MOVBE))
976 CPU = "silvermont";
977 else
978 CPU = "nehalem";
979 } else if (testFeature(X86::FEATURE_SSE4_1)) {
980 CPU = "penryn";
981 } else if (testFeature(X86::FEATURE_SSSE3)) {
982 if (testFeature(X86::FEATURE_MOVBE))
983 CPU = "bonnell";
984 else
985 CPU = "core2";
986 } else if (testFeature(X86::FEATURE_64BIT)) {
987 CPU = "core2";
988 } else if (testFeature(X86::FEATURE_SSE3)) {
989 CPU = "yonah";
990 } else if (testFeature(X86::FEATURE_SSE2)) {
991 CPU = "pentium-m";
992 } else if (testFeature(X86::FEATURE_SSE)) {
993 CPU = "pentium3";
994 } else if (testFeature(X86::FEATURE_MMX)) {
995 CPU = "pentium2";
996 } else {
997 CPU = "pentiumpro";
998 }
999 break;
1000 }
1001 break;
1002 case 15: {
1003 if (testFeature(X86::FEATURE_64BIT)) {
1004 CPU = "nocona";
1005 break;
1006 }
1007 if (testFeature(X86::FEATURE_SSE3)) {
1008 CPU = "prescott";
1009 break;
1010 }
1011 CPU = "pentium4";
1012 break;
1013 }
1014 default:
1015 break; // Unknown.
1016 }
1017
1018 return CPU;
1019 }
1020
1021 static StringRef
1022 getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
1023 const unsigned *Features,
1024 unsigned *Type, unsigned *Subtype) {
1025 auto testFeature = [&](unsigned F) {
1026 return (Features[F / 32] & (1U << (F % 32))) != 0;
1027 };
1028
1029 StringRef CPU;
1030
1031 switch (Family) {
1032 case 4:
1033 CPU = "i486";
1034 break;
1035 case 5:
1036 CPU = "pentium";
1037 switch (Model) {
1038 case 6:
1039 case 7:
1040 CPU = "k6";
1041 break;
1042 case 8:
1043 CPU = "k6-2";
1044 break;
1045 case 9:
1046 case 13:
1047 CPU = "k6-3";
1048 break;
1049 case 10:
1050 CPU = "geode";
1051 break;
1052 }
1053 break;
1054 case 6:
1055 if (testFeature(X86::FEATURE_SSE)) {
1056 CPU = "athlon-xp";
1057 break;
1058 }
1059 CPU = "athlon";
1060 break;
1061 case 15:
1062 if (testFeature(X86::FEATURE_SSE3)) {
1063 CPU = "k8-sse3";
1064 break;
1065 }
1066 CPU = "k8";
1067 break;
1068 case 16:
1069 CPU = "amdfam10";
1070 *Type = X86::AMDFAM10H; // "amdfam10"
1071 switch (Model) {
1072 case 2:
1073 *Subtype = X86::AMDFAM10H_BARCELONA;
1074 break;
1075 case 4:
1076 *Subtype = X86::AMDFAM10H_SHANGHAI;
1077 break;
1078 case 8:
1079 *Subtype = X86::AMDFAM10H_ISTANBUL;
1080 break;
1081 }
1082 break;
1083 case 20:
1084 CPU = "btver1";
1085 *Type = X86::AMD_BTVER1;
1086 break;
1087 case 21:
1088 CPU = "bdver1";
1089 *Type = X86::AMDFAM15H;
1090 if (Model >= 0x60 && Model <= 0x7f) {
1091 CPU = "bdver4";
1092 *Subtype = X86::AMDFAM15H_BDVER4;
1093 break; // 60h-7Fh: Excavator
1094 }
1095 if (Model >= 0x30 && Model <= 0x3f) {
1096 CPU = "bdver3";
1097 *Subtype = X86::AMDFAM15H_BDVER3;
1098 break; // 30h-3Fh: Steamroller
1099 }
1100 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1101 CPU = "bdver2";
1102 *Subtype = X86::AMDFAM15H_BDVER2;
1103 break; // 02h, 10h-1Fh: Piledriver
1104 }
1105 if (Model <= 0x0f) {
1106 *Subtype = X86::AMDFAM15H_BDVER1;
1107 break; // 00h-0Fh: Bulldozer
1108 }
1109 break;
1110 case 22:
1111 CPU = "btver2";
1112 *Type = X86::AMD_BTVER2;
1113 break;
1114 case 23:
1115 CPU = "znver1";
1116 *Type = X86::AMDFAM17H;
1117 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) {
1118 CPU = "znver2";
1119 *Subtype = X86::AMDFAM17H_ZNVER2;
1120 break; // 30h-3fh, 71h: Zen2
1121 }
1122 if (Model <= 0x0f) {
1123 *Subtype = X86::AMDFAM17H_ZNVER1;
1124 break; // 00h-0Fh: Zen1
1125 }
1126 break;
1127 case 25:
1128 CPU = "znver3";
1129 *Type = X86::AMDFAM19H;
1130 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
1131 // Family 19h Models 00h-0Fh - Zen3
1132 // Family 19h Models 20h-2Fh - Zen3
1133 // Family 19h Models 30h-3Fh - Zen3
1134 // Family 19h Models 40h-4Fh - Zen3+
1135 // Family 19h Models 50h-5Fh - Zen3+
1136 *Subtype = X86::AMDFAM19H_ZNVER3;
1137 break;
1138 }
1139 if ((Model >= 0x10 && Model <= 0x1f) ||
1140 (Model >= 0x60 && Model <= 0x74) ||
1141 (Model >= 0x78 && Model <= 0x7b) ||
1142 (Model >= 0xA0 && Model <= 0xAf)) {
1143 CPU = "znver4";
1144 *Subtype = X86::AMDFAM19H_ZNVER4;
1145 break; // "znver4"
1146 }
1147 break; // family 19h
1148 default:
1149 break; // Unknown AMD CPU.
1150 }
1151
1152 return CPU;
1153 }
1154
1155 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1156 unsigned *Features) {
1157 unsigned EAX, EBX;
1158
1159 auto setFeature = [&](unsigned F) {
1160 Features[F / 32] |= 1U << (F % 32);
1161 };
1162
1163 if ((EDX >> 15) & 1)
1164 setFeature(X86::FEATURE_CMOV);
1165 if ((EDX >> 23) & 1)
1166 setFeature(X86::FEATURE_MMX);
1167 if ((EDX >> 25) & 1)
1168 setFeature(X86::FEATURE_SSE);
1169 if ((EDX >> 26) & 1)
1170 setFeature(X86::FEATURE_SSE2);
1171
1172 if ((ECX >> 0) & 1)
1173 setFeature(X86::FEATURE_SSE3);
1174 if ((ECX >> 1) & 1)
1175 setFeature(X86::FEATURE_PCLMUL);
1176 if ((ECX >> 9) & 1)
1177 setFeature(X86::FEATURE_SSSE3);
1178 if ((ECX >> 12) & 1)
1179 setFeature(X86::FEATURE_FMA);
1180 if ((ECX >> 19) & 1)
1181 setFeature(X86::FEATURE_SSE4_1);
1182 if ((ECX >> 20) & 1) {
1183 setFeature(X86::FEATURE_SSE4_2);
1184 setFeature(X86::FEATURE_CRC32);
1185 }
1186 if ((ECX >> 23) & 1)
1187 setFeature(X86::FEATURE_POPCNT);
1188 if ((ECX >> 25) & 1)
1189 setFeature(X86::FEATURE_AES);
1190
1191 if ((ECX >> 22) & 1)
1192 setFeature(X86::FEATURE_MOVBE);
1193
1194 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1195 // indicates that the AVX registers will be saved and restored on context
1196 // switch, then we have full AVX support.
1197 const unsigned AVXBits = (1 << 27) | (1 << 28);
1198 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1199 ((EAX & 0x6) == 0x6);
1200 #if defined(__APPLE__)
1201 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1202 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1203 // set right now.
1204 bool HasAVX512Save = true;
1205 #else
1206 // AVX512 requires additional context to be saved by the OS.
1207 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1208 #endif
1209
1210 if (HasAVX)
1211 setFeature(X86::FEATURE_AVX);
1212
1213 bool HasLeaf7 =
1214 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1215
1216 if (HasLeaf7 && ((EBX >> 3) & 1))
1217 setFeature(X86::FEATURE_BMI);
1218 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1219 setFeature(X86::FEATURE_AVX2);
1220 if (HasLeaf7 && ((EBX >> 8) & 1))
1221 setFeature(X86::FEATURE_BMI2);
1222 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1223 setFeature(X86::FEATURE_AVX512F);
1224 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1225 setFeature(X86::FEATURE_AVX512DQ);
1226 if (HasLeaf7 && ((EBX >> 19) & 1))
1227 setFeature(X86::FEATURE_ADX);
1228 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1229 setFeature(X86::FEATURE_AVX512IFMA);
1230 if (HasLeaf7 && ((EBX >> 23) & 1))
1231 setFeature(X86::FEATURE_CLFLUSHOPT);
1232 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1233 setFeature(X86::FEATURE_AVX512PF);
1234 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1235 setFeature(X86::FEATURE_AVX512ER);
1236 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1237 setFeature(X86::FEATURE_AVX512CD);
1238 if (HasLeaf7 && ((EBX >> 29) & 1))
1239 setFeature(X86::FEATURE_SHA);
1240 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1241 setFeature(X86::FEATURE_AVX512BW);
1242 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1243 setFeature(X86::FEATURE_AVX512VL);
1244
1245 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1246 setFeature(X86::FEATURE_AVX512VBMI);
1247 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1248 setFeature(X86::FEATURE_AVX512VBMI2);
1249 if (HasLeaf7 && ((ECX >> 8) & 1))
1250 setFeature(X86::FEATURE_GFNI);
1251 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1252 setFeature(X86::FEATURE_VPCLMULQDQ);
1253 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1254 setFeature(X86::FEATURE_AVX512VNNI);
1255 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1256 setFeature(X86::FEATURE_AVX512BITALG);
1257 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1258 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1259
1260 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1261 setFeature(X86::FEATURE_AVX5124VNNIW);
1262 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1263 setFeature(X86::FEATURE_AVX5124FMAPS);
1264 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1265 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1266
1267 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1268 // return all 0s for invalid subleaves so check the limit.
1269 bool HasLeaf7Subleaf1 =
1270 HasLeaf7 && EAX >= 1 &&
1271 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1272 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1273 setFeature(X86::FEATURE_AVX512BF16);
1274
1275 unsigned MaxExtLevel;
1276 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1277
1278 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1279 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1280 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1281 setFeature(X86::FEATURE_SSE4_A);
1282 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1283 setFeature(X86::FEATURE_XOP);
1284 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1285 setFeature(X86::FEATURE_FMA4);
1286
1287 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1288 setFeature(X86::FEATURE_64BIT);
1289 }
1290
1291 StringRef sys::getHostCPUName() {
1292 unsigned MaxLeaf = 0;
1293 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1294 if (Vendor == VendorSignatures::UNKNOWN)
1295 return "generic";
1296
1297 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1298 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1299
1300 unsigned Family = 0, Model = 0;
1301 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1302 detectX86FamilyModel(EAX, &Family, &Model);
1303 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1304
1305 // These aren't consumed in this file, but we try to keep some source code the
1306 // same or similar to compiler-rt.
1307 unsigned Type = 0;
1308 unsigned Subtype = 0;
1309
1310 StringRef CPU;
1311
1312 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1313 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1314 &Subtype);
1315 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1316 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1317 &Subtype);
1318 }
1319
1320 if (!CPU.empty())
1321 return CPU;
1322
1323 return "generic";
1324 }
1325
1326 #elif defined(__APPLE__) && defined(__powerpc__)
1327 StringRef sys::getHostCPUName() {
1328 host_basic_info_data_t hostInfo;
1329 mach_msg_type_number_t infoCount;
1330
1331 infoCount = HOST_BASIC_INFO_COUNT;
1332 mach_port_t hostPort = mach_host_self();
1333 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1334 &infoCount);
1335 mach_port_deallocate(mach_task_self(), hostPort);
1336
1337 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1338 return "generic";
1339
1340 switch (hostInfo.cpu_subtype) {
1341 case CPU_SUBTYPE_POWERPC_601:
1342 return "601";
1343 case CPU_SUBTYPE_POWERPC_602:
1344 return "602";
1345 case CPU_SUBTYPE_POWERPC_603:
1346 return "603";
1347 case CPU_SUBTYPE_POWERPC_603e:
1348 return "603e";
1349 case CPU_SUBTYPE_POWERPC_603ev:
1350 return "603ev";
1351 case CPU_SUBTYPE_POWERPC_604:
1352 return "604";
1353 case CPU_SUBTYPE_POWERPC_604e:
1354 return "604e";
1355 case CPU_SUBTYPE_POWERPC_620:
1356 return "620";
1357 case CPU_SUBTYPE_POWERPC_750:
1358 return "750";
1359 case CPU_SUBTYPE_POWERPC_7400:
1360 return "7400";
1361 case CPU_SUBTYPE_POWERPC_7450:
1362 return "7450";
1363 case CPU_SUBTYPE_POWERPC_970:
1364 return "970";
1365 default:;
1366 }
1367
1368 return "generic";
1369 }
1370 #elif defined(__linux__) && defined(__powerpc__)
1371 StringRef sys::getHostCPUName() {
1372 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1373 StringRef Content = P ? P->getBuffer() : "";
1374 return detail::getHostCPUNameForPowerPC(Content);
1375 }
1376 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1377 StringRef sys::getHostCPUName() {
1378 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1379 StringRef Content = P ? P->getBuffer() : "";
1380 return detail::getHostCPUNameForARM(Content);
1381 }
1382 #elif defined(__linux__) && defined(__s390x__)
1383 StringRef sys::getHostCPUName() {
1384 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1385 StringRef Content = P ? P->getBuffer() : "";
1386 return detail::getHostCPUNameForS390x(Content);
1387 }
1388 #elif defined(__MVS__)
1389 StringRef sys::getHostCPUName() {
1390 // Get pointer to Communications Vector Table (CVT).
1391 // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1392 // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1393 int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1394 // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1395 // of address.
1396 int ReadValue = *StartToCVTOffset;
1397 // Explicitly clear the high order bit.
1398 ReadValue = (ReadValue & 0x7FFFFFFF);
1399 char *CVT = reinterpret_cast<char *>(ReadValue);
1400 // The model number is located in the CVT prefix at offset -6 and stored as
1401 // signless packed decimal.
1402 uint16_t Id = *(uint16_t *)&CVT[-6];
1403 // Convert number to integer.
1404 Id = decodePackedBCD<uint16_t>(Id, false);
1405 // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1406 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1407 // extension can only be used if bit CVTVEF is on.
1408 bool HaveVectorSupport = CVT[244] & 0x80;
1409 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1410 }
1411 #elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1412 #define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1413 #define CPUFAMILY_ARM_CYCLONE 0x37a09642
1414 #define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1415 #define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1416 #define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1417 #define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1418 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1419 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1420 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1421
1422 StringRef sys::getHostCPUName() {
1423 uint32_t Family;
1424 size_t Length = sizeof(Family);
1425 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);
1426
1427 switch (Family) {
1428 case CPUFAMILY_ARM_SWIFT:
1429 return "swift";
1430 case CPUFAMILY_ARM_CYCLONE:
1431 return "apple-a7";
1432 case CPUFAMILY_ARM_TYPHOON:
1433 return "apple-a8";
1434 case CPUFAMILY_ARM_TWISTER:
1435 return "apple-a9";
1436 case CPUFAMILY_ARM_HURRICANE:
1437 return "apple-a10";
1438 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1439 return "apple-a11";
1440 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1441 return "apple-a12";
1442 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1443 return "apple-a13";
1444 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1445 return "apple-m1";
1446 default:
1447 // Default to the newest CPU we know about.
1448 return "apple-m1";
1449 }
1450 }
1451 #elif defined(_AIX)
1452 StringRef sys::getHostCPUName() {
1453 switch (_system_configuration.implementation) {
1454 case POWER_4:
1455 if (_system_configuration.version == PV_4_3)
1456 return "970";
1457 return "pwr4";
1458 case POWER_5:
1459 if (_system_configuration.version == PV_5)
1460 return "pwr5";
1461 return "pwr5x";
1462 case POWER_6:
1463 if (_system_configuration.version == PV_6_Compat)
1464 return "pwr6";
1465 return "pwr6x";
1466 case POWER_7:
1467 return "pwr7";
1468 case POWER_8:
1469 return "pwr8";
1470 case POWER_9:
1471 return "pwr9";
1472 // TODO: simplify this once the macro is available in all OS levels.
1473 #ifdef POWER_10
1474 case POWER_10:
1475 #else
1476 case 0x40000:
1477 #endif
1478 return "pwr10";
1479 default:
1480 return "generic";
1481 }
1482 }
1483 #elif defined(__loongarch__)
1484 StringRef sys::getHostCPUName() {
1485 // Use processor id to detect cpu name.
1486 uint32_t processor_id;
1487 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id));
1488 switch (processor_id & 0xff00) {
1489 case 0xc000: // Loongson 64bit, 4-issue
1490 return "la464";
1491 // TODO: Others.
1492 default:
1493 break;
1494 }
1495 return "generic";
1496 }
1497 #elif defined(__riscv)
1498 StringRef sys::getHostCPUName() {
1499 #if defined(__linux__)
1500 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1501 StringRef Content = P ? P->getBuffer() : "";
1502 return detail::getHostCPUNameForRISCV(Content);
1503 #else
1504 #if __riscv_xlen == 64
1505 return "generic-rv64";
1506 #elif __riscv_xlen == 32
1507 return "generic-rv32";
1508 #else
1509 #error "Unhandled value of __riscv_xlen"
1510 #endif
1511 #endif
1512 }
1513 #elif defined(__sparc__)
1514 #if defined(__linux__)
1515 StringRef sys::detail::getHostCPUNameForSPARC(StringRef ProcCpuinfoContent) {
1516 SmallVector<StringRef> Lines;
1517 ProcCpuinfoContent.split(Lines, "\n");
1518
1519 // Look for cpu line to determine cpu name
1520 StringRef Cpu;
1521 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1522 if (Lines[I].startswith("cpu")) {
1523 Cpu = Lines[I].substr(5).ltrim("\t :");
1524 break;
1525 }
1526 }
1527
1528 return StringSwitch<const char *>(Cpu)
1529 .StartsWith("SuperSparc", "supersparc")
1530 .StartsWith("HyperSparc", "hypersparc")
1531 .StartsWith("SpitFire", "ultrasparc")
1532 .StartsWith("BlackBird", "ultrasparc")
1533 .StartsWith("Sabre", " ultrasparc")
1534 .StartsWith("Hummingbird", "ultrasparc")
1535 .StartsWith("Cheetah", "ultrasparc3")
1536 .StartsWith("Jalapeno", "ultrasparc3")
1537 .StartsWith("Jaguar", "ultrasparc3")
1538 .StartsWith("Panther", "ultrasparc3")
1539 .StartsWith("Serrano", "ultrasparc3")
1540 .StartsWith("UltraSparc T1", "niagara")
1541 .StartsWith("UltraSparc T2", "niagara2")
1542 .StartsWith("UltraSparc T3", "niagara3")
1543 .StartsWith("UltraSparc T4", "niagara4")
1544 .StartsWith("UltraSparc T5", "niagara4")
1545 .StartsWith("LEON", "leon3")
1546 // niagara7/m8 not supported by LLVM yet.
1547 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1548 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1549 .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1550 .Default("generic");
1551 }
1552 #endif
1553
1554 StringRef sys::getHostCPUName() {
1555 #if defined(__linux__)
1556 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1557 StringRef Content = P ? P->getBuffer() : "";
1558 return detail::getHostCPUNameForSPARC(Content);
1559 #elif defined(__sun__) && defined(__svr4__)
1560 char *buf = NULL;
1561 kstat_ctl_t *kc;
1562 kstat_t *ksp;
1563 kstat_named_t *brand = NULL;
1564
1565 kc = kstat_open();
1566 if (kc != NULL) {
1567 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1568 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1569 ksp->ks_type == KSTAT_TYPE_NAMED)
1570 brand =
1571 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));
1572 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1573 buf = KSTAT_NAMED_STR_PTR(brand);
1574 }
1575 kstat_close(kc);
1576
1577 return StringSwitch<const char *>(buf)
1578 .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I
1579 .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I
1580 .Case("TMS390Z55",
1581 "supersparc") // Texas Instruments SuperSPARC I with SuperCache
1582 .Case("MB86904", "supersparc") // Fujitsu microSPARC II
1583 .Case("MB86907", "supersparc") // Fujitsu TurboSPARC
1584 .Case("RT623", "hypersparc") // Ross hyperSPARC
1585 .Case("RT625", "hypersparc")
1586 .Case("RT626", "hypersparc")
1587 .Case("UltraSPARC-I", "ultrasparc")
1588 .Case("UltraSPARC-II", "ultrasparc")
1589 .Case("UltraSPARC-IIe", "ultrasparc")
1590 .Case("UltraSPARC-IIi", "ultrasparc")
1591 .Case("SPARC64-III", "ultrasparc")
1592 .Case("SPARC64-IV", "ultrasparc")
1593 .Case("UltraSPARC-III", "ultrasparc3")
1594 .Case("UltraSPARC-III+", "ultrasparc3")
1595 .Case("UltraSPARC-IIIi", "ultrasparc3")
1596 .Case("UltraSPARC-IIIi+", "ultrasparc3")
1597 .Case("UltraSPARC-IV", "ultrasparc3")
1598 .Case("UltraSPARC-IV+", "ultrasparc3")
1599 .Case("SPARC64-V", "ultrasparc3")
1600 .Case("SPARC64-VI", "ultrasparc3")
1601 .Case("SPARC64-VII", "ultrasparc3")
1602 .Case("UltraSPARC-T1", "niagara")
1603 .Case("UltraSPARC-T2", "niagara2")
1604 .Case("UltraSPARC-T2", "niagara2")
1605 .Case("UltraSPARC-T2+", "niagara2")
1606 .Case("SPARC-T3", "niagara3")
1607 .Case("SPARC-T4", "niagara4")
1608 .Case("SPARC-T5", "niagara4")
1609 // niagara7/m8 not supported by LLVM yet.
1610 .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1611 .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1612 .Case("SPARC-M8", "niagara4" /* "m8" */)
1613 .Default("generic");
1614 #else
1615 return "generic";
1616 #endif
1617 }
1618 #else
1619 StringRef sys::getHostCPUName() { return "generic"; }
1620 namespace llvm {
1621 namespace sys {
1622 namespace detail {
1623 namespace x86 {
1624
1625 VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
1626 return VendorSignatures::UNKNOWN;
1627 }
1628
1629 } // namespace x86
1630 } // namespace detail
1631 } // namespace sys
1632 } // namespace llvm
1633 #endif
1634
1635 #if defined(__i386__) || defined(_M_IX86) || \
1636 defined(__x86_64__) || defined(_M_X64)
1637 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1638 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1639 unsigned MaxLevel;
1640
1641 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1642 return false;
1643
1644 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1645
1646 Features["cx8"] = (EDX >> 8) & 1;
1647 Features["cmov"] = (EDX >> 15) & 1;
1648 Features["mmx"] = (EDX >> 23) & 1;
1649 Features["fxsr"] = (EDX >> 24) & 1;
1650 Features["sse"] = (EDX >> 25) & 1;
1651 Features["sse2"] = (EDX >> 26) & 1;
1652
1653 Features["sse3"] = (ECX >> 0) & 1;
1654 Features["pclmul"] = (ECX >> 1) & 1;
1655 Features["ssse3"] = (ECX >> 9) & 1;
1656 Features["cx16"] = (ECX >> 13) & 1;
1657 Features["sse4.1"] = (ECX >> 19) & 1;
1658 Features["sse4.2"] = (ECX >> 20) & 1;
1659 Features["crc32"] = Features["sse4.2"];
1660 Features["movbe"] = (ECX >> 22) & 1;
1661 Features["popcnt"] = (ECX >> 23) & 1;
1662 Features["aes"] = (ECX >> 25) & 1;
1663 Features["rdrnd"] = (ECX >> 30) & 1;
1664
1665 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1666 // indicates that the AVX registers will be saved and restored on context
1667 // switch, then we have full AVX support.
1668 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1669 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1670 #if defined(__APPLE__)
1671 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1672 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1673 // set right now.
1674 bool HasAVX512Save = true;
1675 #else
1676 // AVX512 requires additional context to be saved by the OS.
1677 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1678 #endif
1679 // AMX requires additional context to be saved by the OS.
1680 const unsigned AMXBits = (1 << 17) | (1 << 18);
1681 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1682
1683 Features["avx"] = HasAVXSave;
1684 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1685 // Only enable XSAVE if OS has enabled support for saving YMM state.
1686 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1687 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1688
1689 unsigned MaxExtLevel;
1690 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1691
1692 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1693 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1694 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1695 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1696 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1697 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1698 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1699 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1700 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1701 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1702 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1703
1704 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1705
1706 // Miscellaneous memory related features, detected by
1707 // using the 0x80000008 leaf of the CPUID instruction
1708 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1709 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1710 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1711 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
1712 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1713
1714 bool HasLeaf7 =
1715 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1716
1717 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1718 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1719 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1720 // AVX2 is only supported if we have the OS save support from AVX.
1721 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1722 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1723 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1724 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1725 // AVX512 is only supported if the OS supports the context save for it.
1726 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1727 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1728 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1729 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1730 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1731 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1732 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1733 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1734 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1735 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1736 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1737 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1738 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1739
1740 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1741 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1742 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1743 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1744 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1745 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1746 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1747 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1748 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1749 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1750 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1751 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1752 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1753 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1754 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1755 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1756 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1757 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1758
1759 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
1760 Features["avx512vp2intersect"] =
1761 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1762 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
1763 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
1764 // There are two CPUID leafs which information associated with the pconfig
1765 // instruction:
1766 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1767 // bit of EDX), while the EAX=0x1b leaf returns information on the
1768 // availability of specific pconfig leafs.
1769 // The target feature here only refers to the the first of these two.
1770 // Users might need to check for the availability of specific pconfig
1771 // leaves using cpuid, since that information is ignored while
1772 // detecting features using the "-march=native" flag.
1773 // For more info, see X86 ISA docs.
1774 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1775 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1776 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
1777 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1778 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1779 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1780 // return all 0s for invalid subleaves so check the limit.
1781 bool HasLeaf7Subleaf1 =
1782 HasLeaf7 && EAX >= 1 &&
1783 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1784 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
1785 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
1786 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);
1787 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
1788 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1789 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1790 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
1791 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
1792 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1793 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
1794 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;
1795 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
1796 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
1797 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
1798 Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
1799
1800 bool HasLeafD = MaxLevel >= 0xd &&
1801 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1802
1803 // Only enable XSAVE if OS has enabled support for saving YMM state.
1804 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1805 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1806 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1807
1808 bool HasLeaf14 = MaxLevel >= 0x14 &&
1809 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1810
1811 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1812
1813 bool HasLeaf19 =
1814 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1815 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1816
1817 return true;
1818 }
1819 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1820 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1821 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1822 if (!P)
1823 return false;
1824
1825 SmallVector<StringRef, 32> Lines;
1826 P->getBuffer().split(Lines, "\n");
1827
1828 SmallVector<StringRef, 32> CPUFeatures;
1829
1830 // Look for the CPU features.
1831 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1832 if (Lines[I].startswith("Features")) {
1833 Lines[I].split(CPUFeatures, ' ');
1834 break;
1835 }
1836
1837 #if defined(__aarch64__)
1838 // Keep track of which crypto features we have seen
1839 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1840 uint32_t crypto = 0;
1841 #endif
1842
1843 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1844 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1845 #if defined(__aarch64__)
1846 .Case("asimd", "neon")
1847 .Case("fp", "fp-armv8")
1848 .Case("crc32", "crc")
1849 .Case("atomics", "lse")
1850 .Case("sve", "sve")
1851 .Case("sve2", "sve2")
1852 #else
1853 .Case("half", "fp16")
1854 .Case("neon", "neon")
1855 .Case("vfpv3", "vfp3")
1856 .Case("vfpv3d16", "vfp3d16")
1857 .Case("vfpv4", "vfp4")
1858 .Case("idiva", "hwdiv-arm")
1859 .Case("idivt", "hwdiv")
1860 #endif
1861 .Default("");
1862
1863 #if defined(__aarch64__)
1864 // We need to check crypto separately since we need all of the crypto
1865 // extensions to enable the subtarget feature
1866 if (CPUFeatures[I] == "aes")
1867 crypto |= CAP_AES;
1868 else if (CPUFeatures[I] == "pmull")
1869 crypto |= CAP_PMULL;
1870 else if (CPUFeatures[I] == "sha1")
1871 crypto |= CAP_SHA1;
1872 else if (CPUFeatures[I] == "sha2")
1873 crypto |= CAP_SHA2;
1874 #endif
1875
1876 if (LLVMFeatureStr != "")
1877 Features[LLVMFeatureStr] = true;
1878 }
1879
1880 #if defined(__aarch64__)
1881 // If we have all crypto bits we can add the feature
1882 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1883 Features["crypto"] = true;
1884 #endif
1885
1886 return true;
1887 }
1888 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1889 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1890 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1891 Features["neon"] = true;
1892 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1893 Features["crc"] = true;
1894 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1895 Features["crypto"] = true;
1896
1897 return true;
1898 }
1899 #elif defined(__linux__) && defined(__loongarch__)
1900 #include <sys/auxv.h>
1901 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1902 unsigned long hwcap = getauxval(AT_HWCAP);
1903 bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU
1904 uint32_t cpucfg2 = 0x2;
1905 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2));
1906
1907 Features["f"] = HasFPU && (cpucfg2 & (1U << 1)); // CPUCFG.2.FP_SP
1908 Features["d"] = HasFPU && (cpucfg2 & (1U << 2)); // CPUCFG.2.FP_DP
1909
1910 Features["lsx"] = hwcap & (1UL << 4); // HWCAP_LOONGARCH_LSX
1911 Features["lasx"] = hwcap & (1UL << 5); // HWCAP_LOONGARCH_LASX
1912 Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ
1913
1914 return true;
1915 }
1916 #else
1917 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1918 #endif
1919
1920 #if __APPLE__
1921 /// \returns the \p triple, but with the Host's arch spliced in.
1922 static Triple withHostArch(Triple T) {
1923 #if defined(__arm__)
1924 T.setArch(Triple::arm);
1925 T.setArchName("arm");
1926 #elif defined(__arm64e__)
1927 T.setArch(Triple::aarch64, Triple::AArch64SubArch_arm64e);
1928 T.setArchName("arm64e");
1929 #elif defined(__aarch64__)
1930 T.setArch(Triple::aarch64);
1931 T.setArchName("arm64");
1932 #elif defined(__x86_64h__)
1933 T.setArch(Triple::x86_64);
1934 T.setArchName("x86_64h");
1935 #elif defined(__x86_64__)
1936 T.setArch(Triple::x86_64);
1937 T.setArchName("x86_64");
1938 #elif defined(__powerpc__)
1939 T.setArch(Triple::ppc);
1940 T.setArchName("powerpc");
1941 #else
1942 # error "Unimplemented host arch fixup"
1943 #endif
1944 return T;
1945 }
1946 #endif
1947
1948 std::string sys::getProcessTriple() {
1949 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1950 Triple PT(Triple::normalize(TargetTripleString));
1951
1952 #if __APPLE__
1953 /// In Universal builds, LLVM_HOST_TRIPLE will have the wrong arch in one of
1954 /// the slices. This fixes that up.
1955 PT = withHostArch(PT);
1956 #endif
1957
1958 if (sizeof(void *) == 8 && PT.isArch32Bit())
1959 PT = PT.get64BitArchVariant();
1960 if (sizeof(void *) == 4 && PT.isArch64Bit())
1961 PT = PT.get32BitArchVariant();
1962
1963 return PT.str();
1964 }
1965
1966 void sys::printDefaultTargetAndDetectedCPU(raw_ostream &OS) {
1967 #if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
1968 std::string CPU = std::string(sys::getHostCPUName());
1969 if (CPU == "generic")
1970 CPU = "(unknown)";
1971 OS << " Default target: " << sys::getDefaultTargetTriple() << '\n'
1972 << " Host CPU: " << CPU << '\n';
1973 #endif
1974 }
LLVM monorepo