llvm/lib/TargetParser/X86TargetParser.cpp

   1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements a target parser to recognise X86 hardware features.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/TargetParser/X86TargetParser.h"
  14 #include "llvm/ADT/Bitset.h"
  15 #include "llvm/ADT/StringSwitch.h"
  16 #include <numeric>
  17
  18 using namespace llvm;
  19 using namespace llvm::X86;
  20
  21 namespace {
  22
  23 using FeatureBitset = Bitset<X86::CPU_FEATURE_MAX>;
  24
  25 struct ProcInfo {
  26   StringLiteral Name;
  27   X86::CPUKind Kind;
  28   unsigned KeyFeature;
  29   FeatureBitset Features;
  30   char Mangling;
  31   bool OnlyForCPUDispatchSpecific;
  32 };
  33
  34 struct FeatureInfo {
  35   StringLiteral NameWithPlus;
  36   FeatureBitset ImpliedFeatures;
  37
  38   StringRef getName(bool WithPlus = false) const {
  39     assert(NameWithPlus[0] == '+' && "Expected string to start with '+'");
  40     if (WithPlus)
  41       return NameWithPlus;
  42     return NameWithPlus.drop_front();
  43   }
  44 };
  45
  46 } // end anonymous namespace
  47
  48 #define X86_FEATURE(ENUM, STRING)                                              \
  49   constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
  50 #include "llvm/TargetParser/X86TargetParser.def"
  51
  52 // Pentium with MMX.
  53 constexpr FeatureBitset FeaturesPentiumMMX =
  54     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
  55
  56 // Pentium 2 and 3.
  57 constexpr FeatureBitset FeaturesPentium2 =
  58     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
  59 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
  60
  61 // Pentium 4 CPUs
  62 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2;
  63 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3;
  64 constexpr FeatureBitset FeaturesNocona =
  65     FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
  66
  67 // Basic 64-bit capable CPU.
  68 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
  69 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
  70                                             FeaturePOPCNT | FeatureCRC32 |
  71                                             FeatureSSE4_2 | FeatureCMPXCHG16B;
  72 constexpr FeatureBitset FeaturesX86_64_V3 =
  73     FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
  74     FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
  75 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | FeatureEVEX512 |
  76                                             FeatureAVX512BW | FeatureAVX512CD |
  77                                             FeatureAVX512DQ | FeatureAVX512VL;
  78
  79 // Intel Core CPUs
  80 constexpr FeatureBitset FeaturesCore2 =
  81     FeaturesNocona | FeatureSAHF | FeatureSSSE3;
  82 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
  83 constexpr FeatureBitset FeaturesNehalem =
  84     FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
  85 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
  86 constexpr FeatureBitset FeaturesSandyBridge =
  87     FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
  88 constexpr FeatureBitset FeaturesIvyBridge =
  89     FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
  90 constexpr FeatureBitset FeaturesHaswell =
  91     FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
  92     FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
  93 constexpr FeatureBitset FeaturesBroadwell =
  94     FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
  95
  96 // Intel Knights Landing and Knights Mill
  97 // Knights Landing has feature parity with Broadwell.
  98 constexpr FeatureBitset FeaturesKNL =
  99     FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureEVEX512 |
 100     FeatureAVX512CD | FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
 101 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
 102
 103 // Intel Skylake processors.
 104 constexpr FeatureBitset FeaturesSkylakeClient =
 105     FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
 106     FeatureXSAVES | FeatureSGX;
 107 // SkylakeServer inherits all SkylakeClient features except SGX.
 108 // FIXME: That doesn't match gcc.
 109 constexpr FeatureBitset FeaturesSkylakeServer =
 110     (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureEVEX512 |
 111     FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL |
 112     FeatureCLWB | FeaturePKU;
 113 constexpr FeatureBitset FeaturesCascadeLake =
 114     FeaturesSkylakeServer | FeatureAVX512VNNI;
 115 constexpr FeatureBitset FeaturesCooperLake =
 116     FeaturesCascadeLake | FeatureAVX512BF16;
 117
 118 // Intel 10nm processors.
 119 constexpr FeatureBitset FeaturesCannonlake =
 120     FeaturesSkylakeClient | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
 121     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
 122     FeatureAVX512VBMI | FeaturePKU | FeatureSHA;
 123 constexpr FeatureBitset FeaturesICLClient =
 124     FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
 125     FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
 126     FeatureVAES | FeatureVPCLMULQDQ;
 127 constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX;
 128 constexpr FeatureBitset FeaturesICLServer =
 129     FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
 130 constexpr FeatureBitset FeaturesTigerlake =
 131     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
 132     FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
 133 constexpr FeatureBitset FeaturesSapphireRapids =
 134     FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
 135     FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
 136     FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
 137     FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 138     FeatureWAITPKG;
 139 constexpr FeatureBitset FeaturesGraniteRapids =
 140     FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 141
 142 // Intel Atom processors.
 143 // Bonnell has feature parity with Core2 and adds MOVBE.
 144 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
 145 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
 146 constexpr FeatureBitset FeaturesSilvermont =
 147     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
 148 constexpr FeatureBitset FeaturesGoldmont =
 149     FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
 150     FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
 151     FeatureXSAVEOPT | FeatureXSAVES;
 152 constexpr FeatureBitset FeaturesGoldmontPlus =
 153     FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
 154 constexpr FeatureBitset FeaturesTremont =
 155     FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
 156 constexpr FeatureBitset FeaturesAlderlake =
 157     FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
 158     FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
 159     FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
 160     FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
 161     FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
 162 constexpr FeatureBitset FeaturesSierraforest =
 163     FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
 164     FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 165 constexpr FeatureBitset FeaturesGrandridge =
 166     FeaturesSierraforest | FeatureRAOINT;
 167 constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
 168     FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
 169
 170 // Geode Processor.
 171 constexpr FeatureBitset FeaturesGeode =
 172     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
 173
 174 // K6 processor.
 175 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
 176
 177 // K7 and K8 architecture processors.
 178 constexpr FeatureBitset FeaturesAthlon =
 179     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
 180 constexpr FeatureBitset FeaturesAthlonXP =
 181     FeaturesAthlon | FeatureFXSR | FeatureSSE;
 182 constexpr FeatureBitset FeaturesK8 =
 183     FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
 184 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
 185 constexpr FeatureBitset FeaturesAMDFAM10 =
 186     FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
 187     FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
 188
 189 // Bobcat architecture processors.
 190 constexpr FeatureBitset FeaturesBTVER1 =
 191     FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
 192     FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
 193     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
 194     FeatureSAHF;
 195 constexpr FeatureBitset FeaturesBTVER2 =
 196     FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
 197     FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
 198
 199 // AMD Bulldozer architecture processors.
 200 constexpr FeatureBitset FeaturesBDVER1 =
 201     FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
 202     FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
 203     FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
 204     FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
 205     FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
 206     FeatureXOP | FeatureXSAVE;
 207 constexpr FeatureBitset FeaturesBDVER2 =
 208     FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
 209 constexpr FeatureBitset FeaturesBDVER3 =
 210     FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
 211 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
 212                                          FeatureBMI2 | FeatureMOVBE |
 213                                          FeatureMWAITX | FeatureRDRND;
 214
 215 // AMD Zen architecture processors.
 216 constexpr FeatureBitset FeaturesZNVER1 =
 217     FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
 218     FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
 219     FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
 220     FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
 221     FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
 222     FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
 223     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
 224     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
 225     FeatureXSAVEOPT | FeatureXSAVES;
 226 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
 227                                          FeatureRDPID | FeatureRDPRU |
 228                                          FeatureWBNOINVD;
 229 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 |
 230                                                 FeatureINVPCID | FeaturePKU |
 231                                                 FeatureVAES | FeatureVPCLMULQDQ;
 232 static constexpr FeatureBitset FeaturesZNVER4 =
 233     FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
 234     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
 235     FeatureAVX512VBMI | FeatureAVX512VBMI2 | FeatureAVX512VNNI |
 236     FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 |
 237     FeatureGFNI | FeatureSHSTK;
 238
 239 // D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
 240 // X86TargetParser.def to here. They are assigned by following ways:
 241 // 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
 242 // to '\0' by default, which means not support cpu_specific/dispatch feature.
 243 // 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
 244 // listed here before, which means it doesn't support -march, -mtune and so on.
 245 // FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
 246 // cpu_dispatch/specific() feature and -march, -mtune, and so on.
 247 // clang-format off
 248 constexpr ProcInfo Processors[] = {
 249  // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
 250   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
 251   { {"generic"}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, 'A', true },
 252   // i386-generation processors.
 253   { {"i386"}, CK_i386, ~0U, FeatureX87, '\0', false },
 254   // i486-generation processors.
 255   { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false },
 256   { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
 257   { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
 258   { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
 259   // i586-generation processors, P5 microarchitecture based.
 260   { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
 261   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
 262   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
 263   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
 264   // i686-generation processors, P6 / Pentium M microarchitecture based.
 265   { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
 266   { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
 267   { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
 268   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
 269   { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
 270   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
 271   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
 272   { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
 273   { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
 274   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
 275   { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
 276   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
 277   { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
 278   // Netburst microarchitecture based processors.
 279   { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
 280   { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
 281   { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
 282   { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
 283   { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
 284   { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
 285   // Core microarchitecture based processors.
 286   { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
 287   { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
 288   { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
 289   { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
 290   // Atom processors
 291   { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
 292   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
 293   { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
 294   { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
 295   { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
 296   { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
 297   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
 298   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
 299   { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
 300   { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
 301   // Nehalem microarchitecture based processors.
 302   { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
 303   { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
 304   { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
 305   // Westmere microarchitecture based processors.
 306   { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, 'Q', false },
 307   { {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true },
 308   // Sandy Bridge microarchitecture based processors.
 309   { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false },
 310   { {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true },
 311   { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
 312   // Ivy Bridge microarchitecture based processors.
 313   { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false },
 314   { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true },
 315   { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
 316   // Haswell microarchitecture based processors.
 317   { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false },
 318   { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
 319   { {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true },
 320   { {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true },
 321   // Broadwell microarchitecture based processors.
 322   { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false },
 323   { {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true },
 324   { {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true },
 325   // Skylake client microarchitecture based processors.
 326   { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false },
 327   // Skylake server microarchitecture based processors.
 328   { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
 329   { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', false },
 330   { {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true },
 331   // Cascadelake Server microarchitecture based processors.
 332   { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, 'o', false },
 333   // Cooperlake Server microarchitecture based processors.
 334   { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, 'f', false },
 335   // Cannonlake client microarchitecture based processors.
 336   { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false },
 337   // Icelake client microarchitecture based processors.
 338   { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
 339   { {"icelake_client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, 'k', true },
 340   // Rocketlake microarchitecture based processors.
 341   { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, 'k', false },
 342   // Icelake server microarchitecture based processors.
 343   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
 344   { {"icelake_server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, 'k', true },
 345   // Tigerlake microarchitecture based processors.
 346   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false },
 347   // Sapphire Rapids microarchitecture based processors.
 348   { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
 349   // Alderlake microarchitecture based processors.
 350   { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
 351   // Raptorlake microarchitecture based processors.
 352   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
 353   // Meteorlake microarchitecture based processors.
 354   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
 355   // Arrowlake microarchitecture based processors.
 356   { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
 357   { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
 358   { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
 359   // Lunarlake microarchitecture based processors.
 360   { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
 361   // Gracemont microarchitecture based processors.
 362   { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
 363   // Sierraforest microarchitecture based processors.
 364   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
 365   // Grandridge microarchitecture based processors.
 366   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
 367   // Granite Rapids microarchitecture based processors.
 368   { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
 369   // Granite Rapids D microarchitecture based processors.
 370   { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
 371   { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
 372   // Emerald Rapids microarchitecture based processors.
 373   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
 374   // Knights Landing processor.
 375   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
 376   { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
 377   // Knights Mill processor.
 378   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false },
 379   // Lakemont microarchitecture based processors.
 380   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false },
 381   // K6 architecture processors.
 382   { {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false },
 383   { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW, '\0', false },
 384   { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW, '\0', false },
 385   // K7 architecture processors.
 386   { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
 387   { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
 388   { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
 389   { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
 390   { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
 391   // K8 architecture processors.
 392   { {"k8"}, CK_K8, ~0U, FeaturesK8, '\0', false },
 393   { {"athlon64"}, CK_K8, ~0U, FeaturesK8, '\0', false },
 394   { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false },
 395   { {"opteron"}, CK_K8, ~0U, FeaturesK8, '\0', false },
 396   { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
 397   { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
 398   { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
 399   { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
 400   { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
 401   // Bobcat architecture processors.
 402   { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1, '\0', false },
 403   { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2, '\0', false },
 404   // Bulldozer architecture processors.
 405   { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1, '\0', false },
 406   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2, '\0', false },
 407   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3, '\0', false },
 408   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4, '\0', false },
 409   // Zen architecture processors.
 410   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1, '\0', false },
 411   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
 412   { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
 413   { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
 414   // Generic 64-bit processor.
 415   { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
 416   { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
 417   { {"x86-64-v3"}, CK_x86_64_v3, FEATURE_AVX2, FeaturesX86_64_V3, '\0', false },
 418   { {"x86-64-v4"}, CK_x86_64_v4, FEATURE_AVX512VL, FeaturesX86_64_V4, '\0', false },
 419   // Geode processors.
 420   { {"geode"}, CK_Geode, ~0U, FeaturesGeode, '\0', false },
 421 };
 422 // clang-format on
 423
 424 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
 425
 426 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
 427   for (const auto &P : Processors)
 428     if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU &&
 429         (P.Features[FEATURE_64BIT] || !Only64Bit))
 430       return P.Kind;
 431
 432   return CK_None;
 433 }
 434
 435 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) {
 436   if (llvm::is_contained(NoTuneList, CPU))
 437     return CK_None;
 438   return parseArchX86(CPU, Only64Bit);
 439 }
 440
 441 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
 442                                      bool Only64Bit) {
 443   for (const auto &P : Processors)
 444     if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
 445         (P.Features[FEATURE_64BIT] || !Only64Bit))
 446       Values.emplace_back(P.Name);
 447 }
 448
 449 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values,
 450                                      bool Only64Bit) {
 451   for (const ProcInfo &P : Processors)
 452     if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
 453         (P.Features[FEATURE_64BIT] || !Only64Bit) &&
 454         !llvm::is_contained(NoTuneList, P.Name))
 455       Values.emplace_back(P.Name);
 456 }
 457
 458 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
 459   // FIXME: Can we avoid a linear search here? The table might be sorted by
 460   // CPUKind so we could binary search?
 461   for (const auto &P : Processors) {
 462     if (P.Kind == Kind) {
 463       assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
 464       return static_cast<ProcessorFeatures>(P.KeyFeature);
 465     }
 466   }
 467
 468   llvm_unreachable("Unable to find CPU kind!");
 469 }
 470
 471 // Features with no dependencies.
 472 constexpr FeatureBitset ImpliedFeatures64BIT = {};
 473 constexpr FeatureBitset ImpliedFeaturesADX = {};
 474 constexpr FeatureBitset ImpliedFeaturesBMI = {};
 475 constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
 476 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
 477 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
 478 constexpr FeatureBitset ImpliedFeaturesCLWB = {};
 479 constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
 480 constexpr FeatureBitset ImpliedFeaturesCMOV = {};
 481 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
 482 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
 483 constexpr FeatureBitset ImpliedFeaturesCRC32 = {};
 484 constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
 485 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
 486 constexpr FeatureBitset ImpliedFeaturesFXSR = {};
 487 constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
 488 constexpr FeatureBitset ImpliedFeaturesLWP = {};
 489 constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
 490 constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
 491 constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
 492 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
 493 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
 494 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
 495 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
 496 constexpr FeatureBitset ImpliedFeaturesPKU = {};
 497 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
 498 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
 499 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
 500 constexpr FeatureBitset ImpliedFeaturesRDPID = {};
 501 constexpr FeatureBitset ImpliedFeaturesRDPRU = {};
 502 constexpr FeatureBitset ImpliedFeaturesRDRND = {};
 503 constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
 504 constexpr FeatureBitset ImpliedFeaturesRTM = {};
 505 constexpr FeatureBitset ImpliedFeaturesSAHF = {};
 506 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
 507 constexpr FeatureBitset ImpliedFeaturesSGX = {};
 508 constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
 509 constexpr FeatureBitset ImpliedFeaturesTBM = {};
 510 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
 511 constexpr FeatureBitset ImpliedFeaturesUINTR = {};
 512 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
 513 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
 514 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
 515 constexpr FeatureBitset ImpliedFeaturesX87 = {};
 516 constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
 517
 518 // Not really CPU features, but need to be in the table because clang uses
 519 // target features to communicate them to the backend.
 520 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
 521 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
 522 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
 523 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
 524 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
 525
 526 // XSAVE features are dependent on basic XSAVE.
 527 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
 528 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
 529 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
 530
 531 // MMX->3DNOW->3DNOWA chain.
 532 constexpr FeatureBitset ImpliedFeaturesMMX = {};
 533 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
 534 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
 535
 536 // SSE/AVX/AVX512F chain.
 537 constexpr FeatureBitset ImpliedFeaturesSSE = {};
 538 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
 539 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
 540 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
 541 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
 542 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
 543 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
 544 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
 545 constexpr FeatureBitset ImpliedFeaturesEVEX512 = {};
 546 constexpr FeatureBitset ImpliedFeaturesAVX512F =
 547     FeatureAVX2 | FeatureF16C | FeatureFMA;
 548
 549 // Vector extensions that build on SSE or AVX.
 550 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
 551 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
 552 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
 553 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
 554 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
 555 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
 556 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
 557 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
 558 constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
 559 constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
 560
 561 // AVX512 features.
 562 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
 563 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
 564 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
 565 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
 566 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
 567 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
 568
 569 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
 570 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
 571 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
 572 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
 573 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
 574 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
 575 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
 576 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F;
 577
 578 // FIXME: These two aren't really implemented and just exist in the feature
 579 // list for __builtin_cpu_supports. So omit their dependencies.
 580 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
 581 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
 582
 583 // SSE4_A->FMA4->XOP chain.
 584 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
 585 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
 586 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
 587
 588 // AMX Features
 589 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
 590 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
 591 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
 592 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
 593 constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
 594 constexpr FeatureBitset ImpliedFeaturesHRESET = {};
 595
 596 constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
 597 constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
 598 constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
 599 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2;
 600 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2;
 601 constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
 602 constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
 603 constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
 604 constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =
 605     FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
 606 // Key Locker Features
 607 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
 608 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
 609
 610 // AVXVNNI Features
 611 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
 612
 613 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
 614 #define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
 615 #include "llvm/TargetParser/X86TargetParser.def"
 616 };
 617
 618 void llvm::X86::getFeaturesForCPU(StringRef CPU,
 619                                   SmallVectorImpl<StringRef> &EnabledFeatures,
 620                                   bool NeedPlus) {
 621   auto I = llvm::find_if(Processors,
 622                          [&](const ProcInfo &P) { return P.Name == CPU; });
 623   assert(I != std::end(Processors) && "Processor not found!");
 624
 625   FeatureBitset Bits = I->Features;
 626
 627   // Remove the 64-bit feature which we only use to validate if a CPU can
 628   // be used with 64-bit mode.
 629   Bits &= ~Feature64BIT;
 630
 631   // Add the string version of all set bits.
 632   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
 633     if (Bits[i] && !FeatureInfos[i].getName(NeedPlus).empty())
 634       EnabledFeatures.push_back(FeatureInfos[i].getName(NeedPlus));
 635 }
 636
 637 // For each feature that is (transitively) implied by this feature, set it.
 638 static void getImpliedEnabledFeatures(FeatureBitset &Bits,
 639                                       const FeatureBitset &Implies) {
 640   // Fast path: Implies is often empty.
 641   if (!Implies.any())
 642     return;
 643   FeatureBitset Prev;
 644   Bits |= Implies;
 645   do {
 646     Prev = Bits;
 647     for (unsigned i = CPU_FEATURE_MAX; i;)
 648       if (Bits[--i])
 649         Bits |= FeatureInfos[i].ImpliedFeatures;
 650   } while (Prev != Bits);
 651 }
 652
 653 /// Create bit vector of features that are implied disabled if the feature
 654 /// passed in Value is disabled.
 655 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
 656   // Check all features looking for any dependent on this feature. If we find
 657   // one, mark it and recursively find any feature that depend on it.
 658   FeatureBitset Prev;
 659   Bits.set(Value);
 660   do {
 661     Prev = Bits;
 662     for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
 663       if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
 664         Bits.set(i);
 665   } while (Prev != Bits);
 666 }
 667
 668 void llvm::X86::updateImpliedFeatures(
 669     StringRef Feature, bool Enabled,
 670     StringMap<bool> &Features) {
 671   auto I = llvm::find_if(FeatureInfos, [&](const FeatureInfo &FI) {
 672     return FI.getName() == Feature;
 673   });
 674   if (I == std::end(FeatureInfos)) {
 675     // FIXME: This shouldn't happen, but may not have all features in the table
 676     // yet.
 677     return;
 678   }
 679
 680   FeatureBitset ImpliedBits;
 681   if (Enabled)
 682     getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
 683   else
 684     getImpliedDisabledFeatures(ImpliedBits,
 685                                std::distance(std::begin(FeatureInfos), I));
 686
 687   // Update the map entry for all implied features.
 688   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
 689     if (ImpliedBits[i] && !FeatureInfos[i].getName().empty())
 690       Features[FeatureInfos[i].getName()] = Enabled;
 691 }
 692
 693 char llvm::X86::getCPUDispatchMangling(StringRef CPU) {
 694   auto I = llvm::find_if(Processors,
 695                          [&](const ProcInfo &P) { return P.Name == CPU; });
 696   assert(I != std::end(Processors) && "Processor not found!");
 697   assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!");
 698   return I->Mangling;
 699 }
 700
 701 bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) {
 702   auto I = llvm::find_if(Processors,
 703                          [&](const ProcInfo &P) { return P.Name == Name; });
 704   return I != std::end(Processors);
 705 }
 706
 707 std::array<uint32_t, 4>
 708 llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) {
 709   // Processor features and mapping to processor feature value.
 710   std::array<uint32_t, 4> FeatureMask{};
 711   for (StringRef FeatureStr : FeatureStrs) {
 712     unsigned Feature = StringSwitch<unsigned>(FeatureStr)
 713 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
 714   .Case(STR, llvm::X86::FEATURE_##ENUM)
 715 #define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY)                               \
 716   .Case(STR, llvm::X86::FEATURE_##ENUM)
 717 #include "llvm/TargetParser/X86TargetParser.def"
 718         ;
 719     assert(Feature / 32 < FeatureMask.size());
 720     FeatureMask[Feature / 32] |= 1U << (Feature % 32);
 721   }
 722   return FeatureMask;
 723 }
 724
 725 unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
 726 #ifndef NDEBUG
 727   // Check that priorities are set properly in the .def file. We expect that
 728   // "compat" features are assigned non-duplicate consecutive priorities
 729   // starting from zero (0, 1, ..., num_features - 1).
 730 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
 731   unsigned Priorities[] = {
 732 #include "llvm/TargetParser/X86TargetParser.def"
 733   };
 734   std::array<unsigned, std::size(Priorities)> HelperList;
 735   std::iota(HelperList.begin(), HelperList.end(), 0);
 736   assert(std::is_permutation(HelperList.begin(), HelperList.end(),
 737                              std::begin(Priorities), std::end(Priorities)) &&
 738          "Priorities don't form consecutive range!");
 739 #endif
 740
 741   switch (Feat) {
 742 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
 743   case X86::FEATURE_##ENUM:                                                    \
 744     return PRIORITY;
 745 #include "llvm/TargetParser/X86TargetParser.def"
 746   default:
 747     llvm_unreachable("No Feature Priority for non-CPUSupports Features");
 748   }
 749 }