llvm/utils/TableGen/X86RecognizableInstr.h

   1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file is part of the X86 Disassembler Emitter.
  10 // It contains the interface of a single recognizable instruction.
  11 // Documentation for the disassembler emitter in general can be found in
  12 //  X86DisassemblerEmitter.h.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
  17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
  18
  19 #include "CodeGenInstruction.h"
  20 #include "llvm/Support/X86DisassemblerDecoderCommon.h"
  21 #include <cstdint>
  22 #include <string>
  23 #include <vector>
  24
  25 struct InstructionSpecifier;
  26
  27 namespace llvm {
  28 class Record;
  29 #define X86_INSTR_MRM_MAPPING                                                  \
  30   MAP(C0, 64)                                                                  \
  31   MAP(C1, 65)                                                                  \
  32   MAP(C2, 66)                                                                  \
  33   MAP(C3, 67)                                                                  \
  34   MAP(C4, 68)                                                                  \
  35   MAP(C5, 69)                                                                  \
  36   MAP(C6, 70)                                                                  \
  37   MAP(C7, 71)                                                                  \
  38   MAP(C8, 72)                                                                  \
  39   MAP(C9, 73)                                                                  \
  40   MAP(CA, 74)                                                                  \
  41   MAP(CB, 75)                                                                  \
  42   MAP(CC, 76)                                                                  \
  43   MAP(CD, 77)                                                                  \
  44   MAP(CE, 78)                                                                  \
  45   MAP(CF, 79)                                                                  \
  46   MAP(D0, 80)                                                                  \
  47   MAP(D1, 81)                                                                  \
  48   MAP(D2, 82)                                                                  \
  49   MAP(D3, 83)                                                                  \
  50   MAP(D4, 84)                                                                  \
  51   MAP(D5, 85)                                                                  \
  52   MAP(D6, 86)                                                                  \
  53   MAP(D7, 87)                                                                  \
  54   MAP(D8, 88)                                                                  \
  55   MAP(D9, 89)                                                                  \
  56   MAP(DA, 90)                                                                  \
  57   MAP(DB, 91)                                                                  \
  58   MAP(DC, 92)                                                                  \
  59   MAP(DD, 93)                                                                  \
  60   MAP(DE, 94)                                                                  \
  61   MAP(DF, 95)                                                                  \
  62   MAP(E0, 96)                                                                  \
  63   MAP(E1, 97)                                                                  \
  64   MAP(E2, 98)                                                                  \
  65   MAP(E3, 99)                                                                  \
  66   MAP(E4, 100)                                                                 \
  67   MAP(E5, 101)                                                                 \
  68   MAP(E6, 102)                                                                 \
  69   MAP(E7, 103)                                                                 \
  70   MAP(E8, 104)                                                                 \
  71   MAP(E9, 105)                                                                 \
  72   MAP(EA, 106)                                                                 \
  73   MAP(EB, 107)                                                                 \
  74   MAP(EC, 108)                                                                 \
  75   MAP(ED, 109)                                                                 \
  76   MAP(EE, 110)                                                                 \
  77   MAP(EF, 111)                                                                 \
  78   MAP(F0, 112)                                                                 \
  79   MAP(F1, 113)                                                                 \
  80   MAP(F2, 114)                                                                 \
  81   MAP(F3, 115)                                                                 \
  82   MAP(F4, 116)                                                                 \
  83   MAP(F5, 117)                                                                 \
  84   MAP(F6, 118)                                                                 \
  85   MAP(F7, 119)                                                                 \
  86   MAP(F8, 120)                                                                 \
  87   MAP(F9, 121)                                                                 \
  88   MAP(FA, 122)                                                                 \
  89   MAP(FB, 123)                                                                 \
  90   MAP(FC, 124)                                                                 \
  91   MAP(FD, 125)                                                                 \
  92   MAP(FE, 126)                                                                 \
  93   MAP(FF, 127)
  94
  95 // A clone of X86 since we can't depend on something that is generated.
  96 namespace X86Local {
  97 enum {
  98   Pseudo = 0,
  99   RawFrm = 1,
 100   AddRegFrm = 2,
 101   RawFrmMemOffs = 3,
 102   RawFrmSrc = 4,
 103   RawFrmDst = 5,
 104   RawFrmDstSrc = 6,
 105   RawFrmImm8 = 7,
 106   RawFrmImm16 = 8,
 107   AddCCFrm = 9,
 108   PrefixByte = 10,
 109   MRMDestMem4VOp3CC = 20,
 110   MRMr0 = 21,
 111   MRMSrcMemFSIB = 22,
 112   MRMDestMemFSIB = 23,
 113   MRMDestMem = 24,
 114   MRMSrcMem = 25,
 115   MRMSrcMem4VOp3 = 26,
 116   MRMSrcMemOp4 = 27,
 117   MRMSrcMemCC = 28,
 118   MRMXmCC = 30,
 119   MRMXm = 31,
 120   MRM0m = 32,
 121   MRM1m = 33,
 122   MRM2m = 34,
 123   MRM3m = 35,
 124   MRM4m = 36,
 125   MRM5m = 37,
 126   MRM6m = 38,
 127   MRM7m = 39,
 128   MRMDestReg = 40,
 129   MRMSrcReg = 41,
 130   MRMSrcReg4VOp3 = 42,
 131   MRMSrcRegOp4 = 43,
 132   MRMSrcRegCC = 44,
 133   MRMXrCC = 46,
 134   MRMXr = 47,
 135   MRM0r = 48,
 136   MRM1r = 49,
 137   MRM2r = 50,
 138   MRM3r = 51,
 139   MRM4r = 52,
 140   MRM5r = 53,
 141   MRM6r = 54,
 142   MRM7r = 55,
 143   MRM0X = 56,
 144   MRM1X = 57,
 145   MRM2X = 58,
 146   MRM3X = 59,
 147   MRM4X = 60,
 148   MRM5X = 61,
 149   MRM6X = 62,
 150   MRM7X = 63,
 151 #define MAP(from, to) MRM_##from = to,
 152   X86_INSTR_MRM_MAPPING
 153 #undef MAP
 154 };
 155
 156 enum {
 157   OB = 0,
 158   TB = 1,
 159   T8 = 2,
 160   TA = 3,
 161   XOP8 = 4,
 162   XOP9 = 5,
 163   XOPA = 6,
 164   ThreeDNow = 7,
 165   T_MAP4 = 8,
 166   T_MAP5 = 9,
 167   T_MAP6 = 10,
 168   T_MAP7 = 11
 169 };
 170
 171 enum { PD = 1, XS = 2, XD = 3, PS = 4 };
 172 enum { VEX = 1, XOP = 2, EVEX = 3 };
 173 enum { OpSize16 = 1, OpSize32 = 2 };
 174 enum { AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 };
 175 enum { ExplicitREX2 = 1, ExplicitEVEX = 3 };
 176 } // namespace X86Local
 177
 178 namespace X86Disassembler {
 179 class DisassemblerTables;
 180 /// Extract common fields of a single X86 instruction from a CodeGenInstruction
 181 struct RecognizableInstrBase {
 182   /// The OpPrefix field from the record
 183   uint8_t OpPrefix;
 184   /// The OpMap field from the record
 185   uint8_t OpMap;
 186   /// The opcode field from the record; this is the opcode used in the Intel
 187   /// encoding and therefore distinct from the UID
 188   uint8_t Opcode;
 189   /// The form field from the record
 190   uint8_t Form;
 191   // The encoding field from the record
 192   uint8_t Encoding;
 193   /// The OpSize field from the record
 194   uint8_t OpSize;
 195   /// The AdSize field from the record
 196   uint8_t AdSize;
 197   /// The hasREX_W field from the record
 198   bool HasREX_W;
 199   /// The hasVEX_4V field from the record
 200   bool HasVEX_4V;
 201   /// The IgnoresW field from the record
 202   bool IgnoresW;
 203   /// The hasVEX_L field from the record
 204   bool HasVEX_L;
 205   /// The ignoreVEX_L field from the record
 206   bool IgnoresVEX_L;
 207   /// The hasEVEX_L2Prefix field from the record
 208   bool HasEVEX_L2;
 209   /// The hasEVEX_K field from the record
 210   bool HasEVEX_K;
 211   /// The hasEVEX_KZ field from the record
 212   bool HasEVEX_KZ;
 213   /// The hasEVEX_B field from the record
 214   bool HasEVEX_B;
 215   /// The hasEVEX_NF field from the record
 216   bool HasEVEX_NF;
 217   /// Indicates that the instruction uses the L and L' fields for RC.
 218   bool EncodeRC;
 219   /// The isCodeGenOnly field from the record
 220   bool IsCodeGenOnly;
 221   /// The isAsmParserOnly field from the record
 222   bool IsAsmParserOnly;
 223   /// The ForceDisassemble field from the record
 224   bool ForceDisassemble;
 225   // The CD8_Scale field from the record
 226   uint8_t CD8_Scale;
 227   /// If explicitOpPrefix field from the record equals ExplicitREX2
 228   bool ExplicitREX2Prefix;
 229   /// \param insn The CodeGenInstruction to extract information from.
 230   RecognizableInstrBase(const CodeGenInstruction &insn);
 231   /// \returns true if this instruction should be emitted
 232   bool shouldBeEmitted() const;
 233 };
 234
 235 /// RecognizableInstr - Encapsulates all information required to decode a single
 236 ///   instruction, as extracted from the LLVM instruction tables.  Has methods
 237 ///   to interpret the information available in the LLVM tables, and to emit the
 238 ///   instruction into DisassemblerTables.
 239 class RecognizableInstr : public RecognizableInstrBase {
 240 private:
 241   /// The record from the .td files corresponding to this instruction
 242   const Record *Rec;
 243   /// The instruction name as listed in the tables
 244   std::string Name;
 245   // Whether the instruction has the predicate "In32BitMode"
 246   bool Is32Bit;
 247   // Whether the instruction has the predicate "In64BitMode"
 248   bool Is64Bit;
 249   /// The operands of the instruction, as listed in the CodeGenInstruction.
 250   /// They are not one-to-one with operands listed in the MCInst; for example,
 251   /// memory operands expand to 5 operands in the MCInst
 252   const std::vector<CGIOperandList::OperandInfo> *Operands;
 253
 254   /// The opcode of the instruction, as used in an MCInst
 255   InstrUID UID;
 256   /// The description of the instruction that is emitted into the instruction
 257   /// info table
 258   InstructionSpecifier *Spec;
 259
 260   /// insnContext - Returns the primary context in which the instruction is
 261   ///   valid.
 262   ///
 263   /// @return - The context in which the instruction is valid.
 264   InstructionContext insnContext() const;
 265
 266   /// typeFromString - Translates an operand type from the string provided in
 267   ///   the LLVM tables to an OperandType for use in the operand specifier.
 268   ///
 269   /// @param s              - The string, as extracted by calling Rec->getName()
 270   ///                         on a CodeGenInstruction::OperandInfo.
 271   /// @param hasREX_W - Indicates whether the instruction has a REX.W
 272   ///                         prefix.  If it does, 32-bit register operands stay
 273   ///                         32-bit regardless of the operand size.
 274   /// @param OpSize           Indicates the operand size of the instruction.
 275   ///                         If register size does not match OpSize, then
 276   ///                         register sizes keep their size.
 277   /// @return               - The operand's type.
 278   static OperandType typeFromString(const std::string &s, bool hasREX_W,
 279                                     uint8_t OpSize);
 280
 281   /// immediateEncodingFromString - Translates an immediate encoding from the
 282   ///   string provided in the LLVM tables to an OperandEncoding for use in
 283   ///   the operand specifier.
 284   ///
 285   /// @param s       - See typeFromString().
 286   /// @param OpSize  - Indicates whether this is an OpSize16 instruction.
 287   ///                  If it is not, then 16-bit immediate operands stay 16-bit.
 288   /// @return        - The operand's encoding.
 289   static OperandEncoding immediateEncodingFromString(const std::string &s,
 290                                                      uint8_t OpSize);
 291
 292   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
 293   ///   handles operands that are in the REG field of the ModR/M byte.
 294   static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
 295                                                       uint8_t OpSize);
 296
 297   /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
 298   ///   handles operands that are in the REG field of the ModR/M byte.
 299   static OperandEncoding roRegisterEncodingFromString(const std::string &s,
 300                                                       uint8_t OpSize);
 301   static OperandEncoding memoryEncodingFromString(const std::string &s,
 302                                                   uint8_t OpSize);
 303   static OperandEncoding relocationEncodingFromString(const std::string &s,
 304                                                       uint8_t OpSize);
 305   static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
 306                                                           uint8_t OpSize);
 307   static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
 308                                                         uint8_t OpSize);
 309   static OperandEncoding
 310   writemaskRegisterEncodingFromString(const std::string &s, uint8_t OpSize);
 311
 312   /// Adjust the encoding type for an operand based on the instruction.
 313   void adjustOperandEncoding(OperandEncoding &encoding);
 314
 315   /// handleOperand - Converts a single operand from the LLVM table format to
 316   ///   the emitted table format, handling any duplicate operands it encounters
 317   ///   and then one non-duplicate.
 318   ///
 319   /// @param optional             - Determines whether to assert that the
 320   ///                               operand exists.
 321   /// @param operandIndex         - The index into the generated operand table.
 322   ///                               Incremented by this function one or more
 323   ///                               times to reflect possible duplicate
 324   ///                               operands).
 325   /// @param physicalOperandIndex - The index of the current operand into the
 326   ///                               set of non-duplicate ('physical') operands.
 327   ///                               Incremented by this function once.
 328   /// @param numPhysicalOperands  - The number of non-duplicate operands in the
 329   ///                               instructions.
 330   /// @param operandMapping       - The operand mapping, which has an entry for
 331   ///                               each operand that indicates whether it is a
 332   ///                               duplicate, and of what.
 333   void handleOperand(bool optional, unsigned &operandIndex,
 334                      unsigned &physicalOperandIndex,
 335                      unsigned numPhysicalOperands,
 336                      const unsigned *operandMapping,
 337                      OperandEncoding (*encodingFromString)(const std::string &,
 338                                                            uint8_t OpSize));
 339
 340   /// emitInstructionSpecifier - Loads the instruction specifier for the current
 341   ///   instruction into a DisassemblerTables.
 342   ///
 343   void emitInstructionSpecifier();
 344
 345   /// emitDecodePath - Populates the proper fields in the decode tables
 346   ///   corresponding to the decode paths for this instruction.
 347   ///
 348   /// \param tables The DisassemblerTables to populate with the decode
 349   ///               decode information for the current instruction.
 350   void emitDecodePath(DisassemblerTables &tables) const;
 351
 352 public:
 353   /// Constructor - Initializes a RecognizableInstr with the appropriate fields
 354   ///   from a CodeGenInstruction.
 355   ///
 356   /// \param tables The DisassemblerTables that the specifier will be added to.
 357   /// \param insn   The CodeGenInstruction to extract information from.
 358   /// \param uid    The unique ID of the current instruction.
 359   RecognizableInstr(DisassemblerTables &tables, const CodeGenInstruction &insn,
 360                     InstrUID uid);
 361   /// processInstr - Accepts a CodeGenInstruction and loads decode information
 362   ///   for it into a DisassemblerTables if appropriate.
 363   ///
 364   /// \param tables The DiassemblerTables to be populated with decode
 365   ///               information.
 366   /// \param insn   The CodeGenInstruction to be used as a source for this
 367   ///               information.
 368   /// \param uid    The unique ID of the instruction.
 369   static void processInstr(DisassemblerTables &tables,
 370                            const CodeGenInstruction &insn, InstrUID uid);
 371 };
 372
 373 std::string getMnemonic(const CodeGenInstruction *I, unsigned Variant);
 374 bool isRegisterOperand(const Record *Rec);
 375 bool isMemoryOperand(const Record *Rec);
 376 bool isImmediateOperand(const Record *Rec);
 377 unsigned getRegOperandSize(const Record *RegRec);
 378 unsigned getMemOperandSize(const Record *MemRec);
 379 } // namespace X86Disassembler
 380 } // namespace llvm
 381 #endif