clang/test/CodeGen/arm64-be-bitfield.c

   1 // RUN:  %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -emit-llvm -O0 -o %t -fdump-record-layouts-simple %s | FileCheck %s --check-prefix=LAYOUT
   2 // RUN: FileCheck %s --check-prefix=IR <%t
   3
   4 struct bt3 { signed b2:10; signed b3:10; } b16;
   5
   6 // Get the high 32-bits and then shift appropriately for big-endian.
   7 signed callee_b0f(struct bt3 bp11) {
   8 // IR: callee_b0f(i64 [[ARG:%.*]])
   9 // IR: [[BP11:%.*]] = alloca %struct.bt3, align 4
  10 // IR: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw %struct.bt3, ptr [[BP11]], i32 0, i32 0
  11 // IR: [[COERCE_HIGHBITS:%.*]] = lshr i64 [[ARG]], 32
  12 // IR: [[COERCE_VAL_II:%.*]] = trunc i64 [[COERCE_HIGHBITS]] to i32
  13 // IR: store i32 [[COERCE_VAL_II]], ptr [[COERCE_DIVE]], align 4
  14 // IR: [[BF_LOAD:%.*]] = load i32, ptr [[BP11]], align 4
  15 // IR: [[BF_ASHR:%.*]] = ashr i32 [[BF_LOAD]], 22
  16 // IR: ret i32 [[BF_ASHR]]
  17   return bp11.b2;
  18 }
  19
  20 // LAYOUT-LABEL: LLVMType:%struct.bt3 =
  21 // LAYOUT-SAME: type { i32 }
  22 // LAYOUT: BitFields:[
  23 // LAYOUT-NEXT: <CGBitFieldInfo Offset:22 Size:10 IsSigned:1 StorageSize:32 StorageOffset:0
  24 // LAYOUT-NEXT: <CGBitFieldInfo Offset:12 Size:10 IsSigned:1 StorageSize:32 StorageOffset:0
  25 // LAYOUT-NEXT: ]>