clang/test/CodeGen/inline-asm-intel.c

   1 // REQUIRES: x86-registered-target
   2
   3 /// Accept intel inline asm but write it out as att:
   4 // RUN: %clang_cc1 -triple i386-unknown-linux -mllvm -x86-asm-syntax=att -inline-asm=intel -Werror -target-feature +hreset -target-feature +pconfig -target-feature +sgx -ffreestanding -O0 -S %s -o - | FileCheck --check-prefix=ATT %s
   5 // RUN: %clang_cc1 -triple x86_64-unknown-linux -mllvm -x86-asm-syntax=att -inline-asm=intel -Werror -target-feature +hreset -target-feature +pconfig -target-feature +sgx -ffreestanding -O0 -S %s -o - | FileCheck --check-prefix=ATT %s
   6
   7 /// Accept intel inline asm and write it out as intel:
   8 // RUN: %clang_cc1 -triple i386-unknown-linux -mllvm -x86-asm-syntax=intel -inline-asm=intel -Werror -target-feature +hreset -target-feature +pconfig -target-feature +sgx -ffreestanding -O0 -S %s -o - | FileCheck  --check-prefix=INTEL %s
   9 // RUN: %clang_cc1 -triple x86_64-unknown-linux -mllvm -x86-asm-syntax=intel -inline-asm=intel -Werror -target-feature +hreset -target-feature +pconfig -target-feature +sgx -ffreestanding -O0 -S %s -o - | FileCheck  --check-prefix=INTEL %s
  10
  11 /// Check MS compat mode (_MSC_VER defined). The driver always picks intel
  12 /// output in that mode, so test only that.
  13 // RUN: %clang_cc1 -triple i386-pc-win32 -mllvm -x86-asm-syntax=intel -inline-asm=intel -Werror -target-feature +hreset -target-feature +pconfig -target-feature +sgx -ffreestanding -O0 -S %s -o - -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 | FileCheck  --check-prefix=INTEL %s
  14 // RUN: %clang_cc1 -triple x86_64-pc-win32 -mllvm -x86-asm-syntax=intel -inline-asm=intel -Werror -target-feature +hreset -target-feature +pconfig -target-feature +sgx -ffreestanding -O0 -S %s -o - -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 | FileCheck  --check-prefix=INTEL %s
  15
  16 // Test that intrinsics headers still work with -masm=intel.
  17 #ifdef _MSC_VER
  18 #include <intrin.h>
  19 #else
  20 #include <x86intrin.h>
  21 #endif
  22
  23 void f(void) {
  24   // Intrinsic headers contain macros and inline functions.
  25   // Inline assembly in both are checked only when they are
  26   // referenced, so reference a few intrinsics here.
  27   __SSC_MARK(4);
  28   int a;
  29   _hreset(a);
  30   _pconfig_u32(0, (void*)0);
  31
  32   _encls_u32(0, (void*)0);
  33   _enclu_u32(0, (void*)0);
  34   _enclv_u32(0, (void*)0);
  35 #ifdef _MSC_VER
  36   __movsb((void*)0, (void*)0, 0);
  37   __movsd((void*)0, (void*)0, 0);
  38   __movsw((void*)0, (void*)0, 0);
  39   __stosb((void*)0, 0, 0);
  40   __stosd((void*)0, 0, 0);
  41   __stosw((void*)0, 0, 0);
  42 #ifdef __x86_64__
  43   __movsq((void*)0, (void*)0, 0);
  44   __stosq((void*)0, 0, 0);
  45 #endif
  46   __cpuid((void*)0, 0);
  47   __cpuidex((void*)0, 0, 0);
  48   __halt();
  49   __nop();
  50   __readmsr(0);
  51   __readcr3();
  52   __writecr3(0);
  53
  54   _InterlockedExchange_HLEAcquire((void*)0, 0);
  55   _InterlockedExchange_HLERelease((void*)0, 0);
  56   _InterlockedCompareExchange_HLEAcquire((void*)0, 0, 0);
  57   _InterlockedCompareExchange_HLERelease((void*)0, 0, 0);
  58 #ifdef __x86_64__
  59   _InterlockedExchange64_HLEAcquire((void*)0, 0);
  60   _InterlockedExchange64_HLERelease((void*)0, 0);
  61   _InterlockedCompareExchange64_HLEAcquire((void*)0, 0, 0);
  62   _InterlockedCompareExchange64_HLERelease((void*)0, 0, 0);
  63 #endif
  64 #endif
  65
  66
  67   __asm__("mov eax, ebx");
  68   // ATT: movl %ebx, %eax
  69   // INTEL: mov eax, ebx
  70
  71   // Explicitly overriding asm style per block works:
  72   __asm__(".att_syntax\nmovl %ebx, %eax");
  73   // ATT: movl %ebx, %eax
  74   // INTEL: mov eax, ebx
  75
  76   // The .att_syntax was only scoped to the previous statement.
  77   // (This is different from gcc, where `.att_syntax` is in
  78   // effect from that point on, so portable code would want an
  79   // explicit `.intel_syntax noprefix\n` at the start of this string).
  80   __asm__("mov eax, ebx");
  81   // ATT: movl %ebx, %eax
  82   // INTEL: mov eax, ebx
  83 }
  84