clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_  size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -fopenmp-enable-irbuilder -verify -fopenmp -fopenmp-version=50 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
   3 // expected-no-diagnostics
   4
   5 struct S {
   6   int a, b;
   7 };
   8
   9 struct P {
  10   int a, b;
  11 };
  12
  13 void simple(float *a, float *b, int *c) {
  14   S s, *p;
  15   P pp;
  16 #pragma omp simd safelen(3) order(concurrent)
  17   for (int i = 3; i < 32; i += 5) {
  18     a[i] = b[i] + s.a + p->a;
  19   }
  20
  21 #pragma omp simd
  22   for (int j = 3; j < 32; j += 5) {
  23     c[j] = pp.a;
  24   }
  25 }
  26 // CHECK-LABEL: define {{[^@]+}}@_Z6simplePfS_Pi
  27 // CHECK-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] {
  28 // CHECK-NEXT:  entry:
  29 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
  30 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
  31 // CHECK-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
  32 // CHECK-NEXT:    [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 4
  33 // CHECK-NEXT:    [[P:%.*]] = alloca ptr, align 8
  34 // CHECK-NEXT:    [[PP:%.*]] = alloca [[STRUCT_P:%.*]], align 4
  35 // CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
  36 // CHECK-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
  37 // CHECK-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
  38 // CHECK-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
  39 // CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
  40 // CHECK-NEXT:    [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
  41 // CHECK-NEXT:    [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
  42 // CHECK-NEXT:    [[DOTCOUNT_ADDR10:%.*]] = alloca i32, align 4
  43 // CHECK-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
  44 // CHECK-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
  45 // CHECK-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
  46 // CHECK-NEXT:    store i32 3, ptr [[I]], align 4
  47 // CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
  48 // CHECK-NEXT:    store ptr [[I]], ptr [[TMP0]], align 8
  49 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0
  50 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 4
  51 // CHECK-NEXT:    store i32 [[TMP2]], ptr [[TMP1]], align 4
  52 // CHECK-NEXT:    call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
  53 // CHECK-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
  54 // CHECK-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]]
  55 // CHECK:       omp_loop.preheader:
  56 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER:%.*]]
  57 // CHECK:       omp_loop.header:
  58 // CHECK-NEXT:    [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
  59 // CHECK-NEXT:    br label [[OMP_LOOP_COND:%.*]]
  60 // CHECK:       omp_loop.cond:
  61 // CHECK-NEXT:    [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]]
  62 // CHECK-NEXT:    br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]
  63 // CHECK:       omp_loop.body:
  64 // CHECK-NEXT:    call void @__captured_stmt.1(ptr [[I]], i32 [[OMP_LOOP_IV]], ptr [[AGG_CAPTURED1]]), !llvm.access.group [[ACC_GRP3:![0-9]+]]
  65 // CHECK-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP3]]
  66 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
  67 // CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
  68 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 [[IDXPROM]]
  69 // CHECK-NEXT:    [[TMP5:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
  70 // CHECK-NEXT:    [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[S]], i32 0, i32 0
  71 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[A2]], align 4, !llvm.access.group [[ACC_GRP3]]
  72 // CHECK-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP6]] to float
  73 // CHECK-NEXT:    [[ADD:%.*]] = fadd float [[TMP5]], [[CONV]]
  74 // CHECK-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[P]], align 8, !llvm.access.group [[ACC_GRP3]]
  75 // CHECK-NEXT:    [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP7]], i32 0, i32 0
  76 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !llvm.access.group [[ACC_GRP3]]
  77 // CHECK-NEXT:    [[CONV4:%.*]] = sitofp i32 [[TMP8]] to float
  78 // CHECK-NEXT:    [[ADD5:%.*]] = fadd float [[ADD]], [[CONV4]]
  79 // CHECK-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP3]]
  80 // CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
  81 // CHECK-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP10]] to i64
  82 // CHECK-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM6]]
  83 // CHECK-NEXT:    store float [[ADD5]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]]
  84 // CHECK-NEXT:    br label [[OMP_LOOP_INC]]
  85 // CHECK:       omp_loop.inc:
  86 // CHECK-NEXT:    [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1
  87 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
  88 // CHECK:       omp_loop.exit:
  89 // CHECK-NEXT:    br label [[OMP_LOOP_AFTER:%.*]]
  90 // CHECK:       omp_loop.after:
  91 // CHECK-NEXT:    store i32 3, ptr [[J]], align 4
  92 // CHECK-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED8]], i32 0, i32 0
  93 // CHECK-NEXT:    store ptr [[J]], ptr [[TMP11]], align 8
  94 // CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED9]], i32 0, i32 0
  95 // CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[J]], align 4
  96 // CHECK-NEXT:    store i32 [[TMP13]], ptr [[TMP12]], align 4
  97 // CHECK-NEXT:    call void @__captured_stmt.2(ptr [[DOTCOUNT_ADDR10]], ptr [[AGG_CAPTURED8]])
  98 // CHECK-NEXT:    [[DOTCOUNT11:%.*]] = load i32, ptr [[DOTCOUNT_ADDR10]], align 4
  99 // CHECK-NEXT:    br label [[OMP_LOOP_PREHEADER12:%.*]]
 100 // CHECK:       omp_loop.preheader12:
 101 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER13:%.*]]
 102 // CHECK:       omp_loop.header13:
 103 // CHECK-NEXT:    [[OMP_LOOP_IV19:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER12]] ], [ [[OMP_LOOP_NEXT21:%.*]], [[OMP_LOOP_INC16:%.*]] ]
 104 // CHECK-NEXT:    br label [[OMP_LOOP_COND14:%.*]]
 105 // CHECK:       omp_loop.cond14:
 106 // CHECK-NEXT:    [[OMP_LOOP_CMP20:%.*]] = icmp ult i32 [[OMP_LOOP_IV19]], [[DOTCOUNT11]]
 107 // CHECK-NEXT:    br i1 [[OMP_LOOP_CMP20]], label [[OMP_LOOP_BODY15:%.*]], label [[OMP_LOOP_EXIT17:%.*]]
 108 // CHECK:       omp_loop.body15:
 109 // CHECK-NEXT:    call void @__captured_stmt.3(ptr [[J]], i32 [[OMP_LOOP_IV19]], ptr [[AGG_CAPTURED9]]), !llvm.access.group [[ACC_GRP8:![0-9]+]]
 110 // CHECK-NEXT:    [[A22:%.*]] = getelementptr inbounds nuw [[STRUCT_P]], ptr [[PP]], i32 0, i32 0
 111 // CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[A22]], align 4, !llvm.access.group [[ACC_GRP8]]
 112 // CHECK-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP8]]
 113 // CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP8]]
 114 // CHECK-NEXT:    [[IDXPROM23:%.*]] = sext i32 [[TMP16]] to i64
 115 // CHECK-NEXT:    [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i64 [[IDXPROM23]]
 116 // CHECK-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX24]], align 4, !llvm.access.group [[ACC_GRP8]]
 117 // CHECK-NEXT:    br label [[OMP_LOOP_INC16]]
 118 // CHECK:       omp_loop.inc16:
 119 // CHECK-NEXT:    [[OMP_LOOP_NEXT21]] = add nuw i32 [[OMP_LOOP_IV19]], 1
 120 // CHECK-NEXT:    br label [[OMP_LOOP_HEADER13]], !llvm.loop [[LOOP9:![0-9]+]]
 121 // CHECK:       omp_loop.exit17:
 122 // CHECK-NEXT:    br label [[OMP_LOOP_AFTER18:%.*]]
 123 // CHECK:       omp_loop.after18:
 124 // CHECK-NEXT:    ret void
 125 //
 126 //
 127 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt
 128 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] {
 129 // CHECK-NEXT:  entry:
 130 // CHECK-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
 131 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
 132 // CHECK-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
 133 // CHECK-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
 134 // CHECK-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
 135 // CHECK-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
 136 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
 137 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
 138 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0
 139 // CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
 140 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 141 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
 142 // CHECK-NEXT:    store i32 32, ptr [[DOTSTOP]], align 4
 143 // CHECK-NEXT:    store i32 5, ptr [[DOTSTEP]], align 4
 144 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
 145 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
 146 // CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
 147 // CHECK-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 148 // CHECK:       cond.true:
 149 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
 150 // CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
 151 // CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
 152 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
 153 // CHECK-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
 154 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
 155 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
 156 // CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
 157 // CHECK-NEXT:    br label [[COND_END:%.*]]
 158 // CHECK:       cond.false:
 159 // CHECK-NEXT:    br label [[COND_END]]
 160 // CHECK:       cond.end:
 161 // CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
 162 // CHECK-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
 163 // CHECK-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
 164 // CHECK-NEXT:    ret void
 165 //
 166 //
 167 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1
 168 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] {
 169 // CHECK-NEXT:  entry:
 170 // CHECK-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
 171 // CHECK-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
 172 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
 173 // CHECK-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
 174 // CHECK-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
 175 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
 176 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
 177 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0
 178 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 179 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
 180 // CHECK-NEXT:    [[MUL:%.*]] = mul i32 5, [[TMP3]]
 181 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
 182 // CHECK-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
 183 // CHECK-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
 184 // CHECK-NEXT:    ret void
 185 //
 186 //
 187 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.2
 188 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] {
 189 // CHECK-NEXT:  entry:
 190 // CHECK-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
 191 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
 192 // CHECK-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
 193 // CHECK-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
 194 // CHECK-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
 195 // CHECK-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
 196 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
 197 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
 198 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP0]], i32 0, i32 0
 199 // CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
 200 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 201 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
 202 // CHECK-NEXT:    store i32 32, ptr [[DOTSTOP]], align 4
 203 // CHECK-NEXT:    store i32 5, ptr [[DOTSTEP]], align 4
 204 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
 205 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
 206 // CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
 207 // CHECK-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 208 // CHECK:       cond.true:
 209 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
 210 // CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
 211 // CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
 212 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
 213 // CHECK-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
 214 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
 215 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
 216 // CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
 217 // CHECK-NEXT:    br label [[COND_END:%.*]]
 218 // CHECK:       cond.false:
 219 // CHECK-NEXT:    br label [[COND_END]]
 220 // CHECK:       cond.end:
 221 // CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
 222 // CHECK-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
 223 // CHECK-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
 224 // CHECK-NEXT:    ret void
 225 //
 226 //
 227 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.3
 228 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR1]] {
 229 // CHECK-NEXT:  entry:
 230 // CHECK-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
 231 // CHECK-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
 232 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
 233 // CHECK-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
 234 // CHECK-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
 235 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
 236 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
 237 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP0]], i32 0, i32 0
 238 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 239 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
 240 // CHECK-NEXT:    [[MUL:%.*]] = mul i32 5, [[TMP3]]
 241 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
 242 // CHECK-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
 243 // CHECK-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
 244 // CHECK-NEXT:    ret void
 245 //
 246 //.
 247 // CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
 248 // CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
 249 //.
 250 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
 251 // CHECK: [[META1:![0-9]+]] = !{i32 7, !"openmp", i32 50}
 252 // CHECK: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
 253 // CHECK: [[ACC_GRP3]] = distinct !{}
 254 // CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]], [[META6:![0-9]+]], [[META7:![0-9]+]]}
 255 // CHECK: [[META5]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP3]]}
 256 // CHECK: [[META6]] = !{!"llvm.loop.vectorize.enable", i1 true}
 257 // CHECK: [[META7]] = !{!"llvm.loop.vectorize.width", i32 3}
 258 // CHECK: [[ACC_GRP8]] = distinct !{}
 259 // CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META10:![0-9]+]], [[META6]]}
 260 // CHECK: [[META10]] = !{!"llvm.loop.parallel_accesses", [[ACC_GRP8]]}
 261 //.