clang/test/OpenMP/irbuilder_unroll_unroll_partial_factor.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_  size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -fopenmp-enable-irbuilder -verify -fopenmp -x c -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
   3 // expected-no-diagnostics
   4
   5 #ifndef HEADER
   6 #define HEADER
   7
   8
   9 void unroll_partial_factor_for(float *a, float *b, float *c, float *d) {
  10 #pragma omp for
  11 #pragma omp unroll partial(2)
  12   for (int i = 0; i < 2; i++) {
  13     a[i] = b[i] * c[i] * d[i];
  14   }
  15 }
  16
  17 #endif // HEADER
  18
  19
  20
  21
  22
  23 // CHECK-LABEL: define {{[^@]+}}@unroll_partial_factor_for
  24 // CHECK-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
  25 // CHECK-NEXT:  entry:
  26 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
  27 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
  28 // CHECK-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
  29 // CHECK-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
  30 // CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
  31 // CHECK-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
  32 // CHECK-NEXT:    [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
  33 // CHECK-NEXT:    [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
  34 // CHECK-NEXT:    [[P_LASTITER:%.*]] = alloca i32, align 4
  35 // CHECK-NEXT:    [[P_LOWERBOUND:%.*]] = alloca i32, align 4
  36 // CHECK-NEXT:    [[P_UPPERBOUND:%.*]] = alloca i32, align 4
  37 // CHECK-NEXT:    [[P_STRIDE:%.*]] = alloca i32, align 4
  38 // CHECK-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
  39 // CHECK-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
  40 // CHECK-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
  41 // CHECK-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
  42 // CHECK-NEXT:    store i32 0, ptr [[I]], align 4
  43 // CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
  44 // CHECK-NEXT:    store ptr [[I]], ptr [[TMP0]], align 8
  45 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED1]], i32 0, i32 0
  46 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 4
  47 // CHECK-NEXT:    store i32 [[TMP2]], ptr [[TMP1]], align 4
  48 // CHECK-NEXT:    call void @__captured_stmt(ptr [[DOTCOUNT_ADDR]], ptr [[AGG_CAPTURED]])
  49 // CHECK-NEXT:    [[DOTCOUNT:%.*]] = load i32, ptr [[DOTCOUNT_ADDR]], align 4
  50 // CHECK-NEXT:    br label [[OMP_LOOP_PREHEADER:%.*]]
  51 // CHECK:       omp_loop.preheader:
  52 // CHECK-NEXT:    [[TMP3:%.*]] = udiv i32 [[DOTCOUNT]], 2
  53 // CHECK-NEXT:    [[TMP4:%.*]] = urem i32 [[DOTCOUNT]], 2
  54 // CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
  55 // CHECK-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
  56 // CHECK-NEXT:    [[OMP_FLOOR0_TRIPCOUNT:%.*]] = add nuw i32 [[TMP3]], [[TMP6]]
  57 // CHECK-NEXT:    br label [[OMP_FLOOR0_PREHEADER:%.*]]
  58 // CHECK:       omp_floor0.preheader:
  59 // CHECK-NEXT:    store i32 0, ptr [[P_LOWERBOUND]], align 4
  60 // CHECK-NEXT:    [[TMP7:%.*]] = sub i32 [[OMP_FLOOR0_TRIPCOUNT]], 1
  61 // CHECK-NEXT:    store i32 [[TMP7]], ptr [[P_UPPERBOUND]], align 4
  62 // CHECK-NEXT:    store i32 1, ptr [[P_STRIDE]], align 4
  63 // CHECK-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
  64 // CHECK-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, ptr [[P_LASTITER]], ptr [[P_LOWERBOUND]], ptr [[P_UPPERBOUND]], ptr [[P_STRIDE]], i32 1, i32 0)
  65 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[P_LOWERBOUND]], align 4
  66 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[P_UPPERBOUND]], align 4
  67 // CHECK-NEXT:    [[TMP10:%.*]] = sub i32 [[TMP9]], [[TMP8]]
  68 // CHECK-NEXT:    [[TMP11:%.*]] = add i32 [[TMP10]], 1
  69 // CHECK-NEXT:    br label [[OMP_FLOOR0_HEADER:%.*]]
  70 // CHECK:       omp_floor0.header:
  71 // CHECK-NEXT:    [[OMP_FLOOR0_IV:%.*]] = phi i32 [ 0, [[OMP_FLOOR0_PREHEADER]] ], [ [[OMP_FLOOR0_NEXT:%.*]], [[OMP_FLOOR0_INC:%.*]] ]
  72 // CHECK-NEXT:    br label [[OMP_FLOOR0_COND:%.*]]
  73 // CHECK:       omp_floor0.cond:
  74 // CHECK-NEXT:    [[OMP_FLOOR0_CMP:%.*]] = icmp ult i32 [[OMP_FLOOR0_IV]], [[TMP11]]
  75 // CHECK-NEXT:    br i1 [[OMP_FLOOR0_CMP]], label [[OMP_FLOOR0_BODY:%.*]], label [[OMP_FLOOR0_EXIT:%.*]]
  76 // CHECK:       omp_floor0.body:
  77 // CHECK-NEXT:    [[TMP12:%.*]] = add i32 [[OMP_FLOOR0_IV]], [[TMP8]]
  78 // CHECK-NEXT:    [[TMP13:%.*]] = icmp eq i32 [[TMP12]], [[OMP_FLOOR0_TRIPCOUNT]]
  79 // CHECK-NEXT:    [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[TMP4]], i32 2
  80 // CHECK-NEXT:    br label [[OMP_TILE0_PREHEADER:%.*]]
  81 // CHECK:       omp_tile0.preheader:
  82 // CHECK-NEXT:    br label [[OMP_TILE0_HEADER:%.*]]
  83 // CHECK:       omp_tile0.header:
  84 // CHECK-NEXT:    [[OMP_TILE0_IV:%.*]] = phi i32 [ 0, [[OMP_TILE0_PREHEADER]] ], [ [[OMP_TILE0_NEXT:%.*]], [[OMP_TILE0_INC:%.*]] ]
  85 // CHECK-NEXT:    br label [[OMP_TILE0_COND:%.*]]
  86 // CHECK:       omp_tile0.cond:
  87 // CHECK-NEXT:    [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], [[TMP14]]
  88 // CHECK-NEXT:    br i1 [[OMP_TILE0_CMP]], label [[OMP_TILE0_BODY:%.*]], label [[OMP_TILE0_EXIT:%.*]]
  89 // CHECK:       omp_tile0.body:
  90 // CHECK-NEXT:    [[TMP15:%.*]] = mul nuw i32 2, [[TMP12]]
  91 // CHECK-NEXT:    [[TMP16:%.*]] = add nuw i32 [[TMP15]], [[OMP_TILE0_IV]]
  92 // CHECK-NEXT:    br label [[OMP_LOOP_BODY:%.*]]
  93 // CHECK:       omp_loop.body:
  94 // CHECK-NEXT:    call void @__captured_stmt.1(ptr [[I]], i32 [[TMP16]], ptr [[AGG_CAPTURED1]])
  95 // CHECK-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[B_ADDR]], align 8
  96 // CHECK-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4
  97 // CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
  98 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM]]
  99 // CHECK-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 100 // CHECK-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 101 // CHECK-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4
 102 // CHECK-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64
 103 // CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM2]]
 104 // CHECK-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
 105 // CHECK-NEXT:    [[MUL:%.*]] = fmul float [[TMP19]], [[TMP22]]
 106 // CHECK-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 107 // CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4
 108 // CHECK-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP24]] to i64
 109 // CHECK-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM4]]
 110 // CHECK-NEXT:    [[TMP25:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
 111 // CHECK-NEXT:    [[MUL6:%.*]] = fmul float [[MUL]], [[TMP25]]
 112 // CHECK-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 113 // CHECK-NEXT:    [[TMP27:%.*]] = load i32, ptr [[I]], align 4
 114 // CHECK-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP27]] to i64
 115 // CHECK-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM7]]
 116 // CHECK-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4
 117 // CHECK-NEXT:    br label [[OMP_TILE0_INC]]
 118 // CHECK:       omp_tile0.inc:
 119 // CHECK-NEXT:    [[OMP_TILE0_NEXT]] = add nuw i32 [[OMP_TILE0_IV]], 1
 120 // CHECK-NEXT:    br label [[OMP_TILE0_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
 121 // CHECK:       omp_tile0.exit:
 122 // CHECK-NEXT:    br label [[OMP_TILE0_AFTER:%.*]]
 123 // CHECK:       omp_tile0.after:
 124 // CHECK-NEXT:    br label [[OMP_FLOOR0_INC]]
 125 // CHECK:       omp_floor0.inc:
 126 // CHECK-NEXT:    [[OMP_FLOOR0_NEXT]] = add nuw i32 [[OMP_FLOOR0_IV]], 1
 127 // CHECK-NEXT:    br label [[OMP_FLOOR0_HEADER]]
 128 // CHECK:       omp_floor0.exit:
 129 // CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
 130 // CHECK-NEXT:    [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 131 // CHECK-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM9]])
 132 // CHECK-NEXT:    br label [[OMP_FLOOR0_AFTER:%.*]]
 133 // CHECK:       omp_floor0.after:
 134 // CHECK-NEXT:    br label [[OMP_LOOP_AFTER:%.*]]
 135 // CHECK:       omp_loop.after:
 136 // CHECK-NEXT:    ret void
 137 //
 138 //
 139 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt
 140 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[DISTANCE:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
 141 // CHECK-NEXT:  entry:
 142 // CHECK-NEXT:    [[DISTANCE_ADDR:%.*]] = alloca ptr, align 8
 143 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
 144 // CHECK-NEXT:    [[DOTSTART:%.*]] = alloca i32, align 4
 145 // CHECK-NEXT:    [[DOTSTOP:%.*]] = alloca i32, align 4
 146 // CHECK-NEXT:    [[DOTSTEP:%.*]] = alloca i32, align 4
 147 // CHECK-NEXT:    store ptr [[DISTANCE]], ptr [[DISTANCE_ADDR]], align 8
 148 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
 149 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
 150 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0
 151 // CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
 152 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 153 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[DOTSTART]], align 4
 154 // CHECK-NEXT:    store i32 2, ptr [[DOTSTOP]], align 4
 155 // CHECK-NEXT:    store i32 1, ptr [[DOTSTEP]], align 4
 156 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTSTART]], align 4
 157 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTSTOP]], align 4
 158 // CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
 159 // CHECK-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 160 // CHECK:       cond.true:
 161 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTSTOP]], align 4
 162 // CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTSTART]], align 4
 163 // CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[TMP7]]
 164 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTSTEP]], align 4
 165 // CHECK-NEXT:    [[SUB1:%.*]] = sub i32 [[TMP8]], 1
 166 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
 167 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTSTEP]], align 4
 168 // CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP9]]
 169 // CHECK-NEXT:    br label [[COND_END:%.*]]
 170 // CHECK:       cond.false:
 171 // CHECK-NEXT:    br label [[COND_END]]
 172 // CHECK:       cond.end:
 173 // CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ]
 174 // CHECK-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8
 175 // CHECK-NEXT:    store i32 [[COND]], ptr [[TMP10]], align 4
 176 // CHECK-NEXT:    ret void
 177 //
 178 //
 179 // CHECK-LABEL: define {{[^@]+}}@__captured_stmt.1
 180 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LOOPVAR:%.*]], i32 noundef [[LOGICAL:%.*]], ptr noalias noundef [[__CONTEXT:%.*]]) #[[ATTR0]] {
 181 // CHECK-NEXT:  entry:
 182 // CHECK-NEXT:    [[LOOPVAR_ADDR:%.*]] = alloca ptr, align 8
 183 // CHECK-NEXT:    [[LOGICAL_ADDR:%.*]] = alloca i32, align 4
 184 // CHECK-NEXT:    [[__CONTEXT_ADDR:%.*]] = alloca ptr, align 8
 185 // CHECK-NEXT:    store ptr [[LOOPVAR]], ptr [[LOOPVAR_ADDR]], align 8
 186 // CHECK-NEXT:    store i32 [[LOGICAL]], ptr [[LOGICAL_ADDR]], align 4
 187 // CHECK-NEXT:    store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8
 188 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8
 189 // CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0:%.*]], ptr [[TMP0]], i32 0, i32 0
 190 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 191 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4
 192 // CHECK-NEXT:    [[MUL:%.*]] = mul i32 1, [[TMP3]]
 193 // CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]]
 194 // CHECK-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8
 195 // CHECK-NEXT:    store i32 [[ADD]], ptr [[TMP4]], align 4
 196 // CHECK-NEXT:    ret void
 197 //