clang/test/OpenMP/nvptx_parallel_for_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test target codegen - host bc file has to be created first.
   3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
   4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK
   5 // expected-no-diagnostics
   6 #ifndef HEADER
   7 #define HEADER
   8
   9 template<typename tx>
  10 tx ftemplate(int n) {
  11   tx b[10];
  12
  13   #pragma omp target
  14   {
  15     tx d = n;
  16     #pragma omp parallel for
  17     for(int i=0; i<10; i++) {
  18       b[i] += d;
  19     }
  20     b[3] += 1;
  21   }
  22
  23   return b[3];
  24 }
  25
  26 int bar(int n){
  27   int a = 0;
  28
  29   a += ftemplate<int>(n);
  30
  31   return a;
  32 }
  33
  34 #endif
  35 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13
  36 // CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
  37 // CHECK-NEXT:  entry:
  38 // CHECK-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
  39 // CHECK-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
  40 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
  41 // CHECK-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
  42 // CHECK-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
  43 // CHECK-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
  44 // CHECK-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
  45 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
  46 // CHECK-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_kernel_environment, ptr [[DYN_PTR]])
  47 // CHECK-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
  48 // CHECK-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
  49 // CHECK:       user_code.entry:
  50 // CHECK-NEXT:    [[D:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i64 4)
  51 // CHECK-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
  52 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
  53 // CHECK-NEXT:    store i32 [[TMP3]], ptr [[D]], align 4
  54 // CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
  55 // CHECK-NEXT:    store ptr [[TMP0]], ptr [[TMP4]], align 8
  56 // CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
  57 // CHECK-NEXT:    store ptr [[D]], ptr [[TMP5]], align 8
  58 // CHECK-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 2)
  59 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 3
  60 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
  61 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
  62 // CHECK-NEXT:    store i32 [[ADD]], ptr [[ARRAYIDX]], align 4
  63 // CHECK-NEXT:    call void @__kmpc_free_shared(ptr [[D]], i64 4)
  64 // CHECK-NEXT:    call void @__kmpc_target_deinit()
  65 // CHECK-NEXT:    ret void
  66 // CHECK:       worker.exit:
  67 // CHECK-NEXT:    ret void
  68 //
  69 //
  70 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_omp_outlined
  71 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) #[[ATTR2:[0-9]+]] {
  72 // CHECK-NEXT:  entry:
  73 // CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
  74 // CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
  75 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
  76 // CHECK-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
  77 // CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
  78 // CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  79 // CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
  80 // CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
  81 // CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
  82 // CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  83 // CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
  84 // CHECK-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
  85 // CHECK-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
  86 // CHECK-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
  87 // CHECK-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
  88 // CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
  89 // CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8
  90 // CHECK-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
  91 // CHECK-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
  92 // CHECK-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
  93 // CHECK-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
  94 // CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
  95 // CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
  96 // CHECK-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
  97 // CHECK-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
  98 // CHECK:       omp.dispatch.cond:
  99 // CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 100 // CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
 101 // CHECK-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 102 // CHECK:       cond.true:
 103 // CHECK-NEXT:    br label [[COND_END:%.*]]
 104 // CHECK:       cond.false:
 105 // CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 106 // CHECK-NEXT:    br label [[COND_END]]
 107 // CHECK:       cond.end:
 108 // CHECK-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 109 // CHECK-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 110 // CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 111 // CHECK-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
 112 // CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 113 // CHECK-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 114 // CHECK-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
 115 // CHECK-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 116 // CHECK:       omp.dispatch.body:
 117 // CHECK-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 118 // CHECK:       omp.inner.for.cond:
 119 // CHECK-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 120 // CHECK-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 121 // CHECK-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
 122 // CHECK-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 123 // CHECK:       omp.inner.for.body:
 124 // CHECK-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 125 // CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
 126 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 127 // CHECK-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 128 // CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4
 129 // CHECK-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 130 // CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
 131 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
 132 // CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
 133 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP12]]
 134 // CHECK-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
 135 // CHECK-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 136 // CHECK:       omp.body.continue:
 137 // CHECK-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 138 // CHECK:       omp.inner.for.inc:
 139 // CHECK-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 140 // CHECK-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
 141 // CHECK-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
 142 // CHECK-NEXT:    br label [[OMP_INNER_FOR_COND]]
 143 // CHECK:       omp.inner.for.end:
 144 // CHECK-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 145 // CHECK:       omp.dispatch.inc:
 146 // CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 147 // CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 148 // CHECK-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
 149 // CHECK-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_LB]], align 4
 150 // CHECK-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 151 // CHECK-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 152 // CHECK-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
 153 // CHECK-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_UB]], align 4
 154 // CHECK-NEXT:    br label [[OMP_DISPATCH_COND]]
 155 // CHECK:       omp.dispatch.end:
 156 // CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
 157 // CHECK-NEXT:    ret void
 158 //
 159 //
 160 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_omp_outlined_wrapper
 161 // CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
 162 // CHECK-NEXT:  entry:
 163 // CHECK-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
 164 // CHECK-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
 165 // CHECK-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
 166 // CHECK-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
 167 // CHECK-NEXT:    store i16 [[TMP0]], ptr [[DOTADDR]], align 2
 168 // CHECK-NEXT:    store i32 [[TMP1]], ptr [[DOTADDR1]], align 4
 169 // CHECK-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 170 // CHECK-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
 171 // CHECK-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ARGS]], align 8
 172 // CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 0
 173 // CHECK-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
 174 // CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 1
 175 // CHECK-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
 176 // CHECK-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_omp_outlined(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]], ptr [[TMP4]], ptr [[TMP6]]) #[[ATTR3:[0-9]+]]
 177 // CHECK-NEXT:    ret void
 178 //