clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fopenmp-version=45 -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK2
   5 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fopenmp-version=45 -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK6
  12 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - -femit-all-decls | FileCheck %s --check-prefix=CHECK8
  15 // expected-no-diagnostics
  16 #ifndef HEADER
  17 #define HEADER
  18
  19 int main(int argc, char **argv) {
  20
  21
  22
  23
  24
  25 #pragma omp parallel master taskloop simd priority(argc) safelen(8)
  26   for (int i = 0; i < 10; ++i)
  27     ;
  28
  29
  30
  31 #pragma omp parallel master taskloop simd nogroup grainsize(argc) simdlen(16)
  32   for (int i = 0; i < 10; ++i)
  33     ;
  34
  35
  36   int i;
  37 #pragma omp parallel master taskloop simd if(argc) shared(argc, argv) collapse(2) num_tasks(argc) lastprivate(i) aligned(argv:8)
  38   for (i = 0; i < argc; ++i)
  39   for (int j = argc; j < argv[argc][argc]; ++j)
  40     ;
  41 }
  42
  43 struct S {
  44   int a;
  45   S(int c) {
  46
  47 #pragma omp parallel master taskloop simd shared(c) num_tasks(4) final(c)
  48     for (a = 0; a < c; ++a)
  49       ;
  50   }
  51 } s(1);
  52
  53
  54
  55 #endif
  56 // CHECK1-LABEL: define {{[^@]+}}@main
  57 // CHECK1-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
  58 // CHECK1-NEXT:  entry:
  59 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
  60 // CHECK1-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
  61 // CHECK1-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
  62 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
  63 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
  64 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
  65 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8
  66 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
  67 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i8, align 1
  68 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
  69 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8
  70 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED7:%.*]] = alloca i64, align 8
  71 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  72 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
  73 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
  74 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
  75 // CHECK1-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
  76 // CHECK1-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
  77 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
  78 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
  79 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
  80 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
  81 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
  82 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined, i64 [[TMP3]])
  83 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
  84 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_1]], align 4
  85 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
  86 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR__CASTED2]], align 4
  87 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED2]], align 8
  88 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP6]])
  89 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
  90 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
  91 // CHECK1-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
  92 // CHECK1-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_3]], align 1
  93 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
  94 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_4]], align 4
  95 // CHECK1-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1
  96 // CHECK1-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i1
  97 // CHECK1-NEXT:    [[STOREDV6:%.*]] = zext i1 [[LOADEDV]] to i8
  98 // CHECK1-NEXT:    store i8 [[STOREDV6]], ptr [[DOTCAPTURE_EXPR__CASTED5]], align 1
  99 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED5]], align 8
 100 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
 101 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED7]], align 4
 102 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED7]], align 8
 103 // CHECK1-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1
 104 // CHECK1-NEXT:    [[LOADEDV8:%.*]] = trunc i8 [[TMP13]] to i1
 105 // CHECK1-NEXT:    br i1 [[LOADEDV8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
 106 // CHECK1:       omp_if.then:
 107 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.4, ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]])
 108 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 109 // CHECK1:       omp_if.else:
 110 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 111 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
 112 // CHECK1-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
 113 // CHECK1-NEXT:    call void @main.omp_outlined.4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR2:[0-9]+]]
 114 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 115 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 116 // CHECK1:       omp_if.end:
 117 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
 118 // CHECK1-NEXT:    ret i32 [[TMP14]]
 119 //
 120 //
 121 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined
 122 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
 123 // CHECK1-NEXT:  entry:
 124 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 125 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 126 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 127 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
 128 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 129 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 130 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 131 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 132 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 133 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 134 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
 135 // CHECK1-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
 136 // CHECK1-NEXT:    br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
 137 // CHECK1:       omp_if.then:
 138 // CHECK1-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
 139 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
 140 // CHECK1-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, ptr @.omp_task_entry.)
 141 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0
 142 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 4
 143 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[TMP7]], align 8
 144 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 5
 145 // CHECK1-NEXT:    store i64 0, ptr [[TMP8]], align 8
 146 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6
 147 // CHECK1-NEXT:    store i64 9, ptr [[TMP9]], align 8
 148 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7
 149 // CHECK1-NEXT:    store i64 1, ptr [[TMP10]], align 8
 150 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9
 151 // CHECK1-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP11]], i8 0, i64 8, i1 false)
 152 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[TMP10]], align 8
 153 // CHECK1-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP12]], i32 1, i32 0, i64 0, ptr null)
 154 // CHECK1-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
 155 // CHECK1-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
 156 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 157 // CHECK1:       omp_if.end:
 158 // CHECK1-NEXT:    ret void
 159 //
 160 //
 161 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
 162 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
 163 // CHECK1-NEXT:  entry:
 164 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 165 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 166 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 167 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 168 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 169 // CHECK1-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
 170 // CHECK1-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
 171 // CHECK1-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
 172 // CHECK1-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
 173 // CHECK1-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
 174 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 175 // CHECK1-NEXT:    [[I_I:%.*]] = alloca i32, align 4
 176 // CHECK1-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
 177 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 178 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 179 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 180 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 181 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 182 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 183 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
 184 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 185 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 186 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 187 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
 188 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
 189 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
 190 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
 191 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
 192 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
 193 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
 194 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
 195 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
 196 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
 197 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
 198 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
 199 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
 200 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
 201 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
 202 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
 203 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
 204 // CHECK1-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
 205 // CHECK1-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
 206 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
 207 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
 208 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
 209 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
 210 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
 211 // CHECK1-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
 212 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
 213 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
 214 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
 215 // CHECK1-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32
 216 // CHECK1-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
 217 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
 218 // CHECK1:       omp.inner.for.cond.i:
 219 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
 220 // CHECK1-NEXT:    [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64
 221 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
 222 // CHECK1-NEXT:    [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]
 223 // CHECK1-NEXT:    br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
 224 // CHECK1:       omp.inner.for.body.i:
 225 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
 226 // CHECK1-NEXT:    store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META14]]
 227 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
 228 // CHECK1-NEXT:    [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1
 229 // CHECK1-NEXT:    store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
 230 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]
 231 // CHECK1:       .omp_outlined..exit:
 232 // CHECK1-NEXT:    ret i32 0
 233 //
 234 //
 235 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1
 236 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
 237 // CHECK1-NEXT:  entry:
 238 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 239 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 240 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 241 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1
 242 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 243 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 244 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 245 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 246 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 247 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 248 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
 249 // CHECK1-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
 250 // CHECK1-NEXT:    br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
 251 // CHECK1:       omp_if.then:
 252 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
 253 // CHECK1-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, ptr @.omp_task_entry..3)
 254 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP5]], i32 0, i32 0
 255 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 5
 256 // CHECK1-NEXT:    store i64 0, ptr [[TMP7]], align 8
 257 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6
 258 // CHECK1-NEXT:    store i64 9, ptr [[TMP8]], align 8
 259 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7
 260 // CHECK1-NEXT:    store i64 1, ptr [[TMP9]], align 8
 261 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9
 262 // CHECK1-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false)
 263 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 8
 264 // CHECK1-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP4]] to i64
 265 // CHECK1-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 1, i64 [[TMP12]], ptr null)
 266 // CHECK1-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
 267 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 268 // CHECK1:       omp_if.end:
 269 // CHECK1-NEXT:    ret void
 270 //
 271 //
 272 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..3
 273 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
 274 // CHECK1-NEXT:  entry:
 275 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 276 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 277 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 278 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 279 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 280 // CHECK1-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
 281 // CHECK1-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
 282 // CHECK1-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
 283 // CHECK1-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
 284 // CHECK1-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
 285 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 286 // CHECK1-NEXT:    [[I_I:%.*]] = alloca i32, align 4
 287 // CHECK1-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
 288 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 289 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 290 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 291 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 292 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 293 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 294 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 0
 295 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 296 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 297 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 298 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
 299 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
 300 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
 301 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
 302 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
 303 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
 304 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
 305 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
 306 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
 307 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
 308 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
 309 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
 310 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
 311 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])
 312 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
 313 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]]
 314 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]]
 315 // CHECK1-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]
 316 // CHECK1-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]
 317 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]]
 318 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]
 319 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]]
 320 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]]
 321 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]]
 322 // CHECK1-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]]
 323 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
 324 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
 325 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]
 326 // CHECK1-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32
 327 // CHECK1-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]]
 328 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
 329 // CHECK1:       omp.inner.for.cond.i:
 330 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32:![0-9]+]]
 331 // CHECK1-NEXT:    [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64
 332 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
 333 // CHECK1-NEXT:    [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]
 334 // CHECK1-NEXT:    br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__2_EXIT:%.*]]
 335 // CHECK1:       omp.inner.for.body.i:
 336 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
 337 // CHECK1-NEXT:    store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
 338 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
 339 // CHECK1-NEXT:    [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1
 340 // CHECK1-NEXT:    store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
 341 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]
 342 // CHECK1:       .omp_outlined..2.exit:
 343 // CHECK1-NEXT:    ret i32 0
 344 //
 345 //
 346 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.4
 347 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
 348 // CHECK1-NEXT:  entry:
 349 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 350 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 351 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
 352 // CHECK1-NEXT:    [[ARGC_ADDR:%.*]] = alloca ptr, align 8
 353 // CHECK1-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
 354 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 355 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
 356 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8
 357 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 358 // CHECK1-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
 359 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
 360 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
 361 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
 362 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8
 363 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 364 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 365 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
 366 // CHECK1-NEXT:    store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
 367 // CHECK1-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
 368 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 369 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
 370 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
 371 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
 372 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
 373 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 374 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
 375 // CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])
 376 // CHECK1-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
 377 // CHECK1-NEXT:    br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
 378 // CHECK1:       omp_if.then:
 379 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 0
 380 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP7]], align 8
 381 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 1
 382 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
 383 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 2
 384 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP9]], align 8
 385 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
 386 // CHECK1-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
 387 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 4
 388 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR_4]], align 4
 389 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4
 390 // CHECK1-NEXT:    store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_5]], align 4
 391 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP2]], align 8
 392 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP1]], align 4
 393 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
 394 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP13]], i64 [[IDXPROM]]
 395 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
 396 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP1]], align 4
 397 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
 398 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[TMP15]], i64 [[IDXPROM7]]
 399 // CHECK1-NEXT:    [[TMP17:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
 400 // CHECK1-NEXT:    [[CONV:%.*]] = sext i8 [[TMP17]] to i32
 401 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTCAPTURE_EXPR_6]], align 4
 402 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
 403 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP18]], 0
 404 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 405 // CHECK1-NEXT:    [[CONV10:%.*]] = sext i32 [[DIV]] to i64
 406 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
 407 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
 408 // CHECK1-NEXT:    [[SUB11:%.*]] = sub i32 [[TMP19]], [[TMP20]]
 409 // CHECK1-NEXT:    [[SUB12:%.*]] = sub i32 [[SUB11]], 1
 410 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB12]], 1
 411 // CHECK1-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD]], 1
 412 // CHECK1-NEXT:    [[CONV14:%.*]] = zext i32 [[DIV13]] to i64
 413 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV10]], [[CONV14]]
 414 // CHECK1-NEXT:    [[SUB15:%.*]] = sub nsw i64 [[MUL]], 1
 415 // CHECK1-NEXT:    store i64 [[SUB15]], ptr [[DOTCAPTURE_EXPR_9]], align 8
 416 // CHECK1-NEXT:    [[TMP21:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, ptr @.omp_task_entry..6)
 417 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP21]], i32 0, i32 0
 418 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP22]], i32 0, i32 0
 419 // CHECK1-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
 420 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP24]], ptr align 8 [[AGG_CAPTURED]], i64 24, i1 false)
 421 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP21]], i32 0, i32 1
 422 // CHECK1-NEXT:    [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
 423 // CHECK1-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP26]] to i1
 424 // CHECK1-NEXT:    [[TMP27:%.*]] = sext i1 [[LOADEDV]] to i32
 425 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 5
 426 // CHECK1-NEXT:    store i64 0, ptr [[TMP28]], align 8
 427 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 6
 428 // CHECK1-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
 429 // CHECK1-NEXT:    store i64 [[TMP30]], ptr [[TMP29]], align 8
 430 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 7
 431 // CHECK1-NEXT:    store i64 1, ptr [[TMP31]], align 8
 432 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 9
 433 // CHECK1-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 8, i1 false)
 434 // CHECK1-NEXT:    [[TMP33:%.*]] = load i64, ptr [[TMP31]], align 8
 435 // CHECK1-NEXT:    [[TMP34:%.*]] = zext i32 [[TMP10]] to i64
 436 // CHECK1-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP21]], i32 [[TMP27]], ptr [[TMP28]], ptr [[TMP29]], i64 [[TMP33]], i32 1, i32 2, i64 [[TMP34]], ptr @.omp_task_dup.)
 437 // CHECK1-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
 438 // CHECK1-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])
 439 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 440 // CHECK1:       omp_if.end:
 441 // CHECK1-NEXT:    ret void
 442 //
 443 //
 444 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
 445 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
 446 // CHECK1-NEXT:  entry:
 447 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 448 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 449 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 450 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 451 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 452 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP2]], i32 0, i32 0
 453 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 454 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[TMP4]], align 8
 455 // CHECK1-NEXT:    ret void
 456 //
 457 //
 458 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..6
 459 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
 460 // CHECK1-NEXT:  entry:
 461 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 462 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 463 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 464 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 465 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 466 // CHECK1-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
 467 // CHECK1-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
 468 // CHECK1-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
 469 // CHECK1-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
 470 // CHECK1-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
 471 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 472 // CHECK1-NEXT:    [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
 473 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4
 474 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4
 475 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_3_I:%.*]] = alloca i32, align 4
 476 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_6_I:%.*]] = alloca i64, align 8
 477 // CHECK1-NEXT:    [[I_I:%.*]] = alloca i32, align 4
 478 // CHECK1-NEXT:    [[J_I:%.*]] = alloca i32, align 4
 479 // CHECK1-NEXT:    [[I14_I:%.*]] = alloca i32, align 4
 480 // CHECK1-NEXT:    [[J15_I:%.*]] = alloca i32, align 4
 481 // CHECK1-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i64, align 8
 482 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 483 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 484 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 485 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 486 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 487 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 488 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0
 489 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 490 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 491 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 492 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1
 493 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
 494 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
 495 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
 496 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
 497 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
 498 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
 499 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
 500 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
 501 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
 502 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
 503 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
 504 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])
 505 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
 506 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
 507 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
 508 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META47:![0-9]+]]
 509 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META47]]
 510 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META47]]
 511 // CHECK1-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META47]]
 512 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META47]]
 513 // CHECK1-NEXT:    store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META47]]
 514 // CHECK1-NEXT:    store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META47]]
 515 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META47]]
 516 // CHECK1-NEXT:    store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META47]]
 517 // CHECK1-NEXT:    store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META47]]
 518 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META47]]
 519 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META47]]
 520 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META47]]
 521 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META47]]
 522 // CHECK1-NEXT:    call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
 523 // CHECK1-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8
 524 // CHECK1-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META47]]
 525 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP19]], i32 0, i32 1
 526 // CHECK1-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8
 527 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
 528 // CHECK1-NEXT:    store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
 529 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
 530 // CHECK1-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
 531 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
 532 // CHECK1-NEXT:    store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
 533 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2
 534 // CHECK1-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8
 535 // CHECK1-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8
 536 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
 537 // CHECK1-NEXT:    [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8
 538 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
 539 // CHECK1-NEXT:    [[IDXPROM_I:%.*]] = sext i32 [[TMP35]] to i64
 540 // CHECK1-NEXT:    [[ARRAYIDX_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP32]], i64 [[IDXPROM_I]]
 541 // CHECK1-NEXT:    [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 8
 542 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
 543 // CHECK1-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8
 544 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
 545 // CHECK1-NEXT:    [[IDXPROM4_I:%.*]] = sext i32 [[TMP39]] to i64
 546 // CHECK1-NEXT:    [[ARRAYIDX5_I:%.*]] = getelementptr inbounds i8, ptr [[TMP36]], i64 [[IDXPROM4_I]]
 547 // CHECK1-NEXT:    [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 1
 548 // CHECK1-NEXT:    [[CONV_I:%.*]] = sext i8 [[TMP40]] to i32
 549 // CHECK1-NEXT:    store i32 [[CONV_I]], ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
 550 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
 551 // CHECK1-NEXT:    [[CONV7_I:%.*]] = sext i32 [[TMP41]] to i64
 552 // CHECK1-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
 553 // CHECK1-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
 554 // CHECK1-NEXT:    [[SUB8_I:%.*]] = sub i32 [[TMP42]], [[TMP43]]
 555 // CHECK1-NEXT:    [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
 556 // CHECK1-NEXT:    [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
 557 // CHECK1-NEXT:    [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
 558 // CHECK1-NEXT:    [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
 559 // CHECK1-NEXT:    store i64 [[SUB12_I]], ptr [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias [[META47]]
 560 // CHECK1-NEXT:    store i32 0, ptr [[I_I]], align 4, !noalias [[META47]]
 561 // CHECK1-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
 562 // CHECK1-NEXT:    store i32 [[TMP44]], ptr [[J_I]], align 4, !noalias [[META47]]
 563 // CHECK1-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
 564 // CHECK1-NEXT:    [[CMP_I:%.*]] = icmp slt i32 0, [[TMP45]]
 565 // CHECK1-NEXT:    br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.*]], label [[TASKLOOP_IF_END_I:%.*]]
 566 // CHECK1:       land.lhs.true.i:
 567 // CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
 568 // CHECK1-NEXT:    [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
 569 // CHECK1-NEXT:    [[CMP13_I:%.*]] = icmp slt i32 [[TMP46]], [[TMP47]]
 570 // CHECK1-NEXT:    br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]
 571 // CHECK1:       taskloop.if.then.i:
 572 // CHECK1-NEXT:    [[TMP48:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META47]]
 573 // CHECK1-NEXT:    store i64 [[TMP48]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
 574 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
 575 // CHECK1-NEXT:    [[TMP50:%.*]] = load ptr, ptr [[TMP49]], align 8
 576 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2
 577 // CHECK1-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8
 578 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
 579 // CHECK1:       omp.inner.for.cond.i:
 580 // CHECK1-NEXT:    [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48:![0-9]+]]
 581 // CHECK1-NEXT:    [[TMP54:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 582 // CHECK1-NEXT:    [[CMP16_I:%.*]] = icmp ule i64 [[TMP53]], [[TMP54]]
 583 // CHECK1-NEXT:    br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
 584 // CHECK1:       omp.inner.for.body.i:
 585 // CHECK1-NEXT:    [[TMP55:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 586 // CHECK1-NEXT:    [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 587 // CHECK1-NEXT:    [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 588 // CHECK1-NEXT:    [[SUB17_I:%.*]] = sub i32 [[TMP56]], [[TMP57]]
 589 // CHECK1-NEXT:    [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
 590 // CHECK1-NEXT:    [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
 591 // CHECK1-NEXT:    [[DIV23_I:%.*]] = sdiv i64 [[TMP55]], [[CONV22_I]]
 592 // CHECK1-NEXT:    [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
 593 // CHECK1-NEXT:    store i32 [[CONV26_I]], ptr [[I14_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 594 // CHECK1-NEXT:    [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 595 // CHECK1-NEXT:    [[CONV27_I:%.*]] = sext i32 [[TMP58]] to i64
 596 // CHECK1-NEXT:    [[TMP59:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 597 // CHECK1-NEXT:    [[TMP60:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 598 // CHECK1-NEXT:    [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 599 // CHECK1-NEXT:    [[TMP62:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 600 // CHECK1-NEXT:    [[SUB28_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]
 601 // CHECK1-NEXT:    [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
 602 // CHECK1-NEXT:    [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
 603 // CHECK1-NEXT:    [[DIV34_I:%.*]] = sdiv i64 [[TMP60]], [[CONV33_I]]
 604 // CHECK1-NEXT:    [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 605 // CHECK1-NEXT:    [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 606 // CHECK1-NEXT:    [[SUB35_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]
 607 // CHECK1-NEXT:    [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
 608 // CHECK1-NEXT:    [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
 609 // CHECK1-NEXT:    [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
 610 // CHECK1-NEXT:    [[SUB42_I:%.*]] = sub nsw i64 [[TMP59]], [[MUL41_I]]
 611 // CHECK1-NEXT:    [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
 612 // CHECK1-NEXT:    [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
 613 // CHECK1-NEXT:    store i32 [[CONV45_I]], ptr [[J15_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 614 // CHECK1-NEXT:    [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 615 // CHECK1-NEXT:    [[ADD46_I:%.*]] = add nsw i64 [[TMP65]], 1
 616 // CHECK1-NEXT:    store i64 [[ADD46_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
 617 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP49:![0-9]+]]
 618 // CHECK1:       omp.inner.for.end.i:
 619 // CHECK1-NEXT:    br label [[TASKLOOP_IF_END_I]]
 620 // CHECK1:       taskloop.if.end.i:
 621 // CHECK1-NEXT:    [[TMP66:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META47]]
 622 // CHECK1-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
 623 // CHECK1-NEXT:    br i1 [[TMP67]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__5_EXIT:%.*]]
 624 // CHECK1:       .omp.lastprivate.then.i:
 625 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__5_EXIT]]
 626 // CHECK1:       .omp_outlined..5.exit:
 627 // CHECK1-NEXT:    ret i32 0
 628 //
 629 //
 630 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup.
 631 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] {
 632 // CHECK1-NEXT:  entry:
 633 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 634 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 635 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca i32, align 4
 636 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 637 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 638 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
 639 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 640 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0
 641 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
 642 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
 643 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[TMP5]], align 8
 644 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1
 645 // CHECK1-NEXT:    ret void
 646 //
 647 //
 648 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
 649 // CHECK1-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 650 // CHECK1-NEXT:  entry:
 651 // CHECK1-NEXT:    call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)
 652 // CHECK1-NEXT:    ret void
 653 //
 654 //
 655 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1Ei
 656 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 {
 657 // CHECK1-NEXT:  entry:
 658 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 659 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
 660 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 661 // CHECK1-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
 662 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 663 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
 664 // CHECK1-NEXT:    call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
 665 // CHECK1-NEXT:    ret void
 666 //
 667 //
 668 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ei
 669 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 {
 670 // CHECK1-NEXT:  entry:
 671 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 672 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
 673 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 674 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
 675 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 676 // CHECK1-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
 677 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 678 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
 679 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
 680 // CHECK1-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
 681 // CHECK1-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
 682 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 683 // CHECK1-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1
 684 // CHECK1-NEXT:    [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i8
 685 // CHECK1-NEXT:    store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
 686 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
 687 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @_ZN1SC2Ei.omp_outlined, ptr [[THIS1]], ptr [[C_ADDR]], i64 [[TMP2]])
 688 // CHECK1-NEXT:    ret void
 689 //
 690 //
 691 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ei.omp_outlined
 692 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
 693 // CHECK1-NEXT:  entry:
 694 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 695 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 696 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 697 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 698 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 699 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8
 700 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 701 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 702 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 703 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
 704 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 705 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 706 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 707 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 708 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 709 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 710 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 711 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 712 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 713 // CHECK1-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]])
 714 // CHECK1-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
 715 // CHECK1-NEXT:    br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
 716 // CHECK1:       omp_if.then:
 717 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 0
 718 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP6]], align 8
 719 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 1
 720 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
 721 // CHECK1-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
 722 // CHECK1-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
 723 // CHECK1-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i1
 724 // CHECK1-NEXT:    store ptr [[TMP]], ptr [[_TMP1]], align 8
 725 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4
 726 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 727 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 728 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
 729 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 730 // CHECK1-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
 731 // CHECK1-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4
 732 // CHECK1-NEXT:    [[TMP11:%.*]] = select i1 [[LOADEDV]], i32 2, i32 0
 733 // CHECK1-NEXT:    [[TMP12:%.*]] = or i32 [[TMP11]], 1
 734 // CHECK1-NEXT:    [[TMP13:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP3]], i32 [[TMP12]], i64 80, i64 16, ptr @.omp_task_entry..8)
 735 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP13]], i32 0, i32 0
 736 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP14]], i32 0, i32 0
 737 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
 738 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)
 739 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 5
 740 // CHECK1-NEXT:    store i64 0, ptr [[TMP17]], align 8
 741 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 6
 742 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
 743 // CHECK1-NEXT:    [[CONV:%.*]] = sext i32 [[TMP19]] to i64
 744 // CHECK1-NEXT:    store i64 [[CONV]], ptr [[TMP18]], align 8
 745 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 7
 746 // CHECK1-NEXT:    store i64 1, ptr [[TMP20]], align 8
 747 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 9
 748 // CHECK1-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP21]], i8 0, i64 8, i1 false)
 749 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, ptr [[TMP20]], align 8
 750 // CHECK1-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP3]], ptr [[TMP13]], i32 1, ptr [[TMP17]], ptr [[TMP18]], i64 [[TMP22]], i32 1, i32 2, i64 4, ptr null)
 751 // CHECK1-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
 752 // CHECK1-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP3]])
 753 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 754 // CHECK1:       omp_if.end:
 755 // CHECK1-NEXT:    ret void
 756 //
 757 //
 758 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..8
 759 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
 760 // CHECK1-NEXT:  entry:
 761 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 762 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 763 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 764 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 765 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 766 // CHECK1-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
 767 // CHECK1-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
 768 // CHECK1-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
 769 // CHECK1-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
 770 // CHECK1-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
 771 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 772 // CHECK1-NEXT:    [[TMP_I:%.*]] = alloca i32, align 4
 773 // CHECK1-NEXT:    [[TMP1_I:%.*]] = alloca ptr, align 8
 774 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4
 775 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4
 776 // CHECK1-NEXT:    [[A_I:%.*]] = alloca i32, align 4
 777 // CHECK1-NEXT:    [[TMP4_I:%.*]] = alloca ptr, align 8
 778 // CHECK1-NEXT:    [[A5_I:%.*]] = alloca i32, align 4
 779 // CHECK1-NEXT:    [[TMP6_I:%.*]] = alloca ptr, align 8
 780 // CHECK1-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
 781 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 782 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 783 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 784 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 785 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 786 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 787 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 0
 788 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 789 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 790 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 791 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
 792 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
 793 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
 794 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
 795 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
 796 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
 797 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
 798 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
 799 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
 800 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
 801 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])
 802 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])
 803 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
 804 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
 805 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
 806 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]]
 807 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]]
 808 // CHECK1-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]]
 809 // CHECK1-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]]
 810 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]]
 811 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META62]]
 812 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META62]]
 813 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META62]]
 814 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META62]]
 815 // CHECK1-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META62]]
 816 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]]
 817 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]]
 818 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
 819 // CHECK1-NEXT:    store ptr [[TMP_I]], ptr [[TMP1_I]], align 8, !noalias [[META62]]
 820 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4:%.*]], ptr [[TMP18]], i32 0, i32 1
 821 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8
 822 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
 823 // CHECK1-NEXT:    store i32 [[TMP22]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META62]]
 824 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META62]]
 825 // CHECK1-NEXT:    [[SUB3_I:%.*]] = sub nsw i32 [[TMP23]], 1
 826 // CHECK1-NEXT:    store i32 [[SUB3_I]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META62]]
 827 // CHECK1-NEXT:    store ptr [[A_I]], ptr [[TMP4_I]], align 8, !noalias [[META62]]
 828 // CHECK1-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[TMP4_I]], align 8, !noalias [[META62]]
 829 // CHECK1-NEXT:    store i32 0, ptr [[TMP24]], align 4
 830 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META62]]
 831 // CHECK1-NEXT:    [[CMP_I:%.*]] = icmp slt i32 0, [[TMP25]]
 832 // CHECK1-NEXT:    br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__7_EXIT:%.*]]
 833 // CHECK1:       taskloop.if.then.i:
 834 // CHECK1-NEXT:    store ptr [[A5_I]], ptr [[TMP6_I]], align 8, !noalias [[META62]]
 835 // CHECK1-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META62]]
 836 // CHECK1-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32
 837 // CHECK1-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]]
 838 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[TMP18]], i32 0, i32 1
 839 // CHECK1-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
 840 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
 841 // CHECK1:       omp.inner.for.cond.i:
 842 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63:![0-9]+]]
 843 // CHECK1-NEXT:    [[CONV7_I:%.*]] = sext i32 [[TMP29]] to i64
 844 // CHECK1-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
 845 // CHECK1-NEXT:    [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP30]]
 846 // CHECK1-NEXT:    br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
 847 // CHECK1:       omp.inner.for.body.i:
 848 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
 849 // CHECK1-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP6_I]], align 8, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
 850 // CHECK1-NEXT:    store i32 [[TMP31]], ptr [[TMP32]], align 4, !llvm.access.group [[ACC_GRP63]]
 851 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
 852 // CHECK1-NEXT:    [[ADD9_I:%.*]] = add nsw i32 [[TMP33]], 1
 853 // CHECK1-NEXT:    store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
 854 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP64:![0-9]+]]
 855 // CHECK1:       omp.inner.for.end.i:
 856 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__7_EXIT]]
 857 // CHECK1:       .omp_outlined..7.exit:
 858 // CHECK1-NEXT:    ret i32 0
 859 //
 860 //
 861 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
 862 // CHECK1-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 863 // CHECK1-NEXT:  entry:
 864 // CHECK1-NEXT:    call void @__cxx_global_var_init()
 865 // CHECK1-NEXT:    ret void
 866 //
 867 //
 868 // CHECK2-LABEL: define {{[^@]+}}@main
 869 // CHECK2-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
 870 // CHECK2-NEXT:  entry:
 871 // CHECK2-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 872 // CHECK2-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
 873 // CHECK2-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
 874 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 875 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
 876 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 877 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8
 878 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
 879 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i8, align 1
 880 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
 881 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8
 882 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED7:%.*]] = alloca i64, align 8
 883 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 884 // CHECK2-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
 885 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
 886 // CHECK2-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 887 // CHECK2-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
 888 // CHECK2-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
 889 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
 890 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 891 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 892 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
 893 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
 894 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined, i64 [[TMP3]])
 895 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
 896 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 897 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 898 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR__CASTED2]], align 4
 899 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED2]], align 8
 900 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP6]])
 901 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
 902 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
 903 // CHECK2-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
 904 // CHECK2-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_3]], align 1
 905 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
 906 // CHECK2-NEXT:    store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_4]], align 4
 907 // CHECK2-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1
 908 // CHECK2-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i1
 909 // CHECK2-NEXT:    [[STOREDV6:%.*]] = zext i1 [[LOADEDV]] to i8
 910 // CHECK2-NEXT:    store i8 [[STOREDV6]], ptr [[DOTCAPTURE_EXPR__CASTED5]], align 1
 911 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED5]], align 8
 912 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
 913 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED7]], align 4
 914 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED7]], align 8
 915 // CHECK2-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1
 916 // CHECK2-NEXT:    [[LOADEDV8:%.*]] = trunc i8 [[TMP13]] to i1
 917 // CHECK2-NEXT:    br i1 [[LOADEDV8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
 918 // CHECK2:       omp_if.then:
 919 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.4, ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]])
 920 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
 921 // CHECK2:       omp_if.else:
 922 // CHECK2-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 923 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
 924 // CHECK2-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
 925 // CHECK2-NEXT:    call void @main.omp_outlined.4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR2:[0-9]+]]
 926 // CHECK2-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 927 // CHECK2-NEXT:    br label [[OMP_IF_END]]
 928 // CHECK2:       omp_if.end:
 929 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
 930 // CHECK2-NEXT:    ret i32 [[TMP14]]
 931 //
 932 //
 933 // CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined
 934 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
 935 // CHECK2-NEXT:  entry:
 936 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 937 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 938 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 939 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
 940 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 941 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 942 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 943 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 944 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 945 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 946 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
 947 // CHECK2-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
 948 // CHECK2-NEXT:    br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
 949 // CHECK2:       omp_if.then:
 950 // CHECK2-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
 951 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
 952 // CHECK2-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, ptr @.omp_task_entry.)
 953 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0
 954 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 4
 955 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[TMP7]], align 8
 956 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 5
 957 // CHECK2-NEXT:    store i64 0, ptr [[TMP8]], align 8
 958 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6
 959 // CHECK2-NEXT:    store i64 9, ptr [[TMP9]], align 8
 960 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7
 961 // CHECK2-NEXT:    store i64 1, ptr [[TMP10]], align 8
 962 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9
 963 // CHECK2-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP11]], i8 0, i64 8, i1 false)
 964 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[TMP10]], align 8
 965 // CHECK2-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP12]], i32 1, i32 0, i64 0, ptr null)
 966 // CHECK2-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
 967 // CHECK2-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
 968 // CHECK2-NEXT:    br label [[OMP_IF_END]]
 969 // CHECK2:       omp_if.end:
 970 // CHECK2-NEXT:    ret void
 971 //
 972 //
 973 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
 974 // CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
 975 // CHECK2-NEXT:  entry:
 976 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 977 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 978 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 979 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 980 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 981 // CHECK2-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
 982 // CHECK2-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
 983 // CHECK2-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
 984 // CHECK2-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
 985 // CHECK2-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
 986 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 987 // CHECK2-NEXT:    [[I_I:%.*]] = alloca i32, align 4
 988 // CHECK2-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
 989 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 990 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 991 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 992 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 993 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 994 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 995 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
 996 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 997 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 998 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 999 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1000 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
1001 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1002 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
1003 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1004 // CHECK2-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
1005 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1006 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
1007 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1008 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
1009 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1010 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1011 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1012 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1013 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1014 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1015 // CHECK2-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1016 // CHECK2-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1017 // CHECK2-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1018 // CHECK2-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1019 // CHECK2-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1020 // CHECK2-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1021 // CHECK2-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1022 // CHECK2-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1023 // CHECK2-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1024 // CHECK2-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1025 // CHECK2-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1026 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1027 // CHECK2-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32
1028 // CHECK2-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1029 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
1030 // CHECK2:       omp.inner.for.cond.i:
1031 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1032 // CHECK2-NEXT:    [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64
1033 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1034 // CHECK2-NEXT:    [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]
1035 // CHECK2-NEXT:    br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1036 // CHECK2:       omp.inner.for.body.i:
1037 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1038 // CHECK2-NEXT:    store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META14]]
1039 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1040 // CHECK2-NEXT:    [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1
1041 // CHECK2-NEXT:    store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1042 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]
1043 // CHECK2:       .omp_outlined..exit:
1044 // CHECK2-NEXT:    ret i32 0
1045 //
1046 //
1047 // CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined.1
1048 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
1049 // CHECK2-NEXT:  entry:
1050 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1051 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1052 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1053 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1
1054 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1055 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1056 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1057 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1058 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1059 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1060 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
1061 // CHECK2-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
1062 // CHECK2-NEXT:    br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1063 // CHECK2:       omp_if.then:
1064 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
1065 // CHECK2-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, ptr @.omp_task_entry..3)
1066 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP5]], i32 0, i32 0
1067 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 5
1068 // CHECK2-NEXT:    store i64 0, ptr [[TMP7]], align 8
1069 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6
1070 // CHECK2-NEXT:    store i64 9, ptr [[TMP8]], align 8
1071 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7
1072 // CHECK2-NEXT:    store i64 1, ptr [[TMP9]], align 8
1073 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9
1074 // CHECK2-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false)
1075 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 8
1076 // CHECK2-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP4]] to i64
1077 // CHECK2-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 1, i64 [[TMP12]], ptr null)
1078 // CHECK2-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
1079 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1080 // CHECK2:       omp_if.end:
1081 // CHECK2-NEXT:    ret void
1082 //
1083 //
1084 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..3
1085 // CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
1086 // CHECK2-NEXT:  entry:
1087 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1088 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1089 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1090 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1091 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1092 // CHECK2-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1093 // CHECK2-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1094 // CHECK2-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1095 // CHECK2-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1096 // CHECK2-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1097 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1098 // CHECK2-NEXT:    [[I_I:%.*]] = alloca i32, align 4
1099 // CHECK2-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1100 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1101 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1102 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1103 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1104 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1105 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1106 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 0
1107 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1108 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1109 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1110 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1111 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
1112 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1113 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
1114 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1115 // CHECK2-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
1116 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1117 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
1118 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1119 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
1120 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
1121 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
1122 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
1123 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])
1124 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
1125 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]]
1126 // CHECK2-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]]
1127 // CHECK2-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]
1128 // CHECK2-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]
1129 // CHECK2-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]]
1130 // CHECK2-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]
1131 // CHECK2-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]]
1132 // CHECK2-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]]
1133 // CHECK2-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]]
1134 // CHECK2-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]]
1135 // CHECK2-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
1136 // CHECK2-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
1137 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]
1138 // CHECK2-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32
1139 // CHECK2-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]]
1140 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
1141 // CHECK2:       omp.inner.for.cond.i:
1142 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32:![0-9]+]]
1143 // CHECK2-NEXT:    [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64
1144 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1145 // CHECK2-NEXT:    [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]
1146 // CHECK2-NEXT:    br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__2_EXIT:%.*]]
1147 // CHECK2:       omp.inner.for.body.i:
1148 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1149 // CHECK2-NEXT:    store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1150 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1151 // CHECK2-NEXT:    [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1
1152 // CHECK2-NEXT:    store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1153 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]
1154 // CHECK2:       .omp_outlined..2.exit:
1155 // CHECK2-NEXT:    ret i32 0
1156 //
1157 //
1158 // CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined.4
1159 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
1160 // CHECK2-NEXT:  entry:
1161 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1162 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1163 // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1164 // CHECK2-NEXT:    [[ARGC_ADDR:%.*]] = alloca ptr, align 8
1165 // CHECK2-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
1166 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1167 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
1168 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8
1169 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1170 // CHECK2-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
1171 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1172 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1173 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
1174 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8
1175 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1176 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1177 // CHECK2-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1178 // CHECK2-NEXT:    store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
1179 // CHECK2-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
1180 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1181 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
1182 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1183 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
1184 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
1185 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1186 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1187 // CHECK2-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])
1188 // CHECK2-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
1189 // CHECK2-NEXT:    br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1190 // CHECK2:       omp_if.then:
1191 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 0
1192 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP7]], align 8
1193 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 1
1194 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
1195 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 2
1196 // CHECK2-NEXT:    store ptr [[TMP2]], ptr [[TMP9]], align 8
1197 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
1198 // CHECK2-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
1199 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP1]], align 4
1200 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR_4]], align 4
1201 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4
1202 // CHECK2-NEXT:    store i32 [[TMP12]], ptr [[DOTCAPTURE_EXPR_5]], align 4
1203 // CHECK2-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP2]], align 8
1204 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP1]], align 4
1205 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
1206 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP13]], i64 [[IDXPROM]]
1207 // CHECK2-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
1208 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP1]], align 4
1209 // CHECK2-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
1210 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[TMP15]], i64 [[IDXPROM7]]
1211 // CHECK2-NEXT:    [[TMP17:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
1212 // CHECK2-NEXT:    [[CONV:%.*]] = sext i8 [[TMP17]] to i32
1213 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTCAPTURE_EXPR_6]], align 4
1214 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1215 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP18]], 0
1216 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1217 // CHECK2-NEXT:    [[CONV10:%.*]] = sext i32 [[DIV]] to i64
1218 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
1219 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
1220 // CHECK2-NEXT:    [[SUB11:%.*]] = sub i32 [[TMP19]], [[TMP20]]
1221 // CHECK2-NEXT:    [[SUB12:%.*]] = sub i32 [[SUB11]], 1
1222 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 [[SUB12]], 1
1223 // CHECK2-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD]], 1
1224 // CHECK2-NEXT:    [[CONV14:%.*]] = zext i32 [[DIV13]] to i64
1225 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV10]], [[CONV14]]
1226 // CHECK2-NEXT:    [[SUB15:%.*]] = sub nsw i64 [[MUL]], 1
1227 // CHECK2-NEXT:    store i64 [[SUB15]], ptr [[DOTCAPTURE_EXPR_9]], align 8
1228 // CHECK2-NEXT:    [[TMP21:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 24, ptr @.omp_task_entry..6)
1229 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP21]], i32 0, i32 0
1230 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP22]], i32 0, i32 0
1231 // CHECK2-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
1232 // CHECK2-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP24]], ptr align 8 [[AGG_CAPTURED]], i64 24, i1 false)
1233 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP21]], i32 0, i32 1
1234 // CHECK2-NEXT:    [[TMP26:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
1235 // CHECK2-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP26]] to i1
1236 // CHECK2-NEXT:    [[TMP27:%.*]] = sext i1 [[LOADEDV]] to i32
1237 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 5
1238 // CHECK2-NEXT:    store i64 0, ptr [[TMP28]], align 8
1239 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 6
1240 // CHECK2-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
1241 // CHECK2-NEXT:    store i64 [[TMP30]], ptr [[TMP29]], align 8
1242 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 7
1243 // CHECK2-NEXT:    store i64 1, ptr [[TMP31]], align 8
1244 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP22]], i32 0, i32 9
1245 // CHECK2-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 8, i1 false)
1246 // CHECK2-NEXT:    [[TMP33:%.*]] = load i64, ptr [[TMP31]], align 8
1247 // CHECK2-NEXT:    [[TMP34:%.*]] = zext i32 [[TMP10]] to i64
1248 // CHECK2-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP21]], i32 [[TMP27]], ptr [[TMP28]], ptr [[TMP29]], i64 [[TMP33]], i32 1, i32 2, i64 [[TMP34]], ptr @.omp_task_dup.)
1249 // CHECK2-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
1250 // CHECK2-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])
1251 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1252 // CHECK2:       omp_if.end:
1253 // CHECK2-NEXT:    ret void
1254 //
1255 //
1256 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
1257 // CHECK2-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
1258 // CHECK2-NEXT:  entry:
1259 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1260 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1261 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1262 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1263 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1264 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP2]], i32 0, i32 0
1265 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1266 // CHECK2-NEXT:    store ptr [[TMP3]], ptr [[TMP4]], align 8
1267 // CHECK2-NEXT:    ret void
1268 //
1269 //
1270 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..6
1271 // CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
1272 // CHECK2-NEXT:  entry:
1273 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1274 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1275 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1276 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1277 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1278 // CHECK2-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1279 // CHECK2-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1280 // CHECK2-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1281 // CHECK2-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1282 // CHECK2-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1283 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1284 // CHECK2-NEXT:    [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1285 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4
1286 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4
1287 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_3_I:%.*]] = alloca i32, align 4
1288 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_6_I:%.*]] = alloca i64, align 8
1289 // CHECK2-NEXT:    [[I_I:%.*]] = alloca i32, align 4
1290 // CHECK2-NEXT:    [[J_I:%.*]] = alloca i32, align 4
1291 // CHECK2-NEXT:    [[I14_I:%.*]] = alloca i32, align 4
1292 // CHECK2-NEXT:    [[J15_I:%.*]] = alloca i32, align 4
1293 // CHECK2-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i64, align 8
1294 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1295 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1296 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1297 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1298 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1299 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1300 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0
1301 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1302 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1303 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1304 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1
1305 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1306 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
1307 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1308 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
1309 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1310 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
1311 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1312 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
1313 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1314 // CHECK2-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1315 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
1316 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])
1317 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
1318 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
1319 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
1320 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META47:![0-9]+]]
1321 // CHECK2-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META47]]
1322 // CHECK2-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META47]]
1323 // CHECK2-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META47]]
1324 // CHECK2-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META47]]
1325 // CHECK2-NEXT:    store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META47]]
1326 // CHECK2-NEXT:    store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META47]]
1327 // CHECK2-NEXT:    store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META47]]
1328 // CHECK2-NEXT:    store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META47]]
1329 // CHECK2-NEXT:    store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META47]]
1330 // CHECK2-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META47]]
1331 // CHECK2-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META47]]
1332 // CHECK2-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META47]]
1333 // CHECK2-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META47]]
1334 // CHECK2-NEXT:    call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
1335 // CHECK2-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8
1336 // CHECK2-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META47]]
1337 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP19]], i32 0, i32 1
1338 // CHECK2-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8
1339 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
1340 // CHECK2-NEXT:    store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
1341 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
1342 // CHECK2-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
1343 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
1344 // CHECK2-NEXT:    store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
1345 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2
1346 // CHECK2-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8
1347 // CHECK2-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8
1348 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
1349 // CHECK2-NEXT:    [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8
1350 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
1351 // CHECK2-NEXT:    [[IDXPROM_I:%.*]] = sext i32 [[TMP35]] to i64
1352 // CHECK2-NEXT:    [[ARRAYIDX_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP32]], i64 [[IDXPROM_I]]
1353 // CHECK2-NEXT:    [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 8
1354 // CHECK2-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
1355 // CHECK2-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8
1356 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
1357 // CHECK2-NEXT:    [[IDXPROM4_I:%.*]] = sext i32 [[TMP39]] to i64
1358 // CHECK2-NEXT:    [[ARRAYIDX5_I:%.*]] = getelementptr inbounds i8, ptr [[TMP36]], i64 [[IDXPROM4_I]]
1359 // CHECK2-NEXT:    [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 1
1360 // CHECK2-NEXT:    [[CONV_I:%.*]] = sext i8 [[TMP40]] to i32
1361 // CHECK2-NEXT:    store i32 [[CONV_I]], ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
1362 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
1363 // CHECK2-NEXT:    [[CONV7_I:%.*]] = sext i32 [[TMP41]] to i64
1364 // CHECK2-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
1365 // CHECK2-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
1366 // CHECK2-NEXT:    [[SUB8_I:%.*]] = sub i32 [[TMP42]], [[TMP43]]
1367 // CHECK2-NEXT:    [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
1368 // CHECK2-NEXT:    [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
1369 // CHECK2-NEXT:    [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
1370 // CHECK2-NEXT:    [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
1371 // CHECK2-NEXT:    store i64 [[SUB12_I]], ptr [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias [[META47]]
1372 // CHECK2-NEXT:    store i32 0, ptr [[I_I]], align 4, !noalias [[META47]]
1373 // CHECK2-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
1374 // CHECK2-NEXT:    store i32 [[TMP44]], ptr [[J_I]], align 4, !noalias [[META47]]
1375 // CHECK2-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
1376 // CHECK2-NEXT:    [[CMP_I:%.*]] = icmp slt i32 0, [[TMP45]]
1377 // CHECK2-NEXT:    br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.*]], label [[TASKLOOP_IF_END_I:%.*]]
1378 // CHECK2:       land.lhs.true.i:
1379 // CHECK2-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
1380 // CHECK2-NEXT:    [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
1381 // CHECK2-NEXT:    [[CMP13_I:%.*]] = icmp slt i32 [[TMP46]], [[TMP47]]
1382 // CHECK2-NEXT:    br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]
1383 // CHECK2:       taskloop.if.then.i:
1384 // CHECK2-NEXT:    [[TMP48:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META47]]
1385 // CHECK2-NEXT:    store i64 [[TMP48]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
1386 // CHECK2-NEXT:    [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
1387 // CHECK2-NEXT:    [[TMP50:%.*]] = load ptr, ptr [[TMP49]], align 8
1388 // CHECK2-NEXT:    [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2
1389 // CHECK2-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8
1390 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
1391 // CHECK2:       omp.inner.for.cond.i:
1392 // CHECK2-NEXT:    [[TMP53:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48:![0-9]+]]
1393 // CHECK2-NEXT:    [[TMP54:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1394 // CHECK2-NEXT:    [[CMP16_I:%.*]] = icmp ule i64 [[TMP53]], [[TMP54]]
1395 // CHECK2-NEXT:    br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
1396 // CHECK2:       omp.inner.for.body.i:
1397 // CHECK2-NEXT:    [[TMP55:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1398 // CHECK2-NEXT:    [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1399 // CHECK2-NEXT:    [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1400 // CHECK2-NEXT:    [[SUB17_I:%.*]] = sub i32 [[TMP56]], [[TMP57]]
1401 // CHECK2-NEXT:    [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
1402 // CHECK2-NEXT:    [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
1403 // CHECK2-NEXT:    [[DIV23_I:%.*]] = sdiv i64 [[TMP55]], [[CONV22_I]]
1404 // CHECK2-NEXT:    [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
1405 // CHECK2-NEXT:    store i32 [[CONV26_I]], ptr [[I14_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1406 // CHECK2-NEXT:    [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1407 // CHECK2-NEXT:    [[CONV27_I:%.*]] = sext i32 [[TMP58]] to i64
1408 // CHECK2-NEXT:    [[TMP59:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1409 // CHECK2-NEXT:    [[TMP60:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1410 // CHECK2-NEXT:    [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1411 // CHECK2-NEXT:    [[TMP62:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1412 // CHECK2-NEXT:    [[SUB28_I:%.*]] = sub i32 [[TMP61]], [[TMP62]]
1413 // CHECK2-NEXT:    [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
1414 // CHECK2-NEXT:    [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
1415 // CHECK2-NEXT:    [[DIV34_I:%.*]] = sdiv i64 [[TMP60]], [[CONV33_I]]
1416 // CHECK2-NEXT:    [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1417 // CHECK2-NEXT:    [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1418 // CHECK2-NEXT:    [[SUB35_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]
1419 // CHECK2-NEXT:    [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
1420 // CHECK2-NEXT:    [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
1421 // CHECK2-NEXT:    [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
1422 // CHECK2-NEXT:    [[SUB42_I:%.*]] = sub nsw i64 [[TMP59]], [[MUL41_I]]
1423 // CHECK2-NEXT:    [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
1424 // CHECK2-NEXT:    [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
1425 // CHECK2-NEXT:    store i32 [[CONV45_I]], ptr [[J15_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1426 // CHECK2-NEXT:    [[TMP65:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1427 // CHECK2-NEXT:    [[ADD46_I:%.*]] = add nsw i64 [[TMP65]], 1
1428 // CHECK2-NEXT:    store i64 [[ADD46_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
1429 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP49:![0-9]+]]
1430 // CHECK2:       omp.inner.for.end.i:
1431 // CHECK2-NEXT:    br label [[TASKLOOP_IF_END_I]]
1432 // CHECK2:       taskloop.if.end.i:
1433 // CHECK2-NEXT:    [[TMP66:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META47]]
1434 // CHECK2-NEXT:    [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
1435 // CHECK2-NEXT:    br i1 [[TMP67]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__5_EXIT:%.*]]
1436 // CHECK2:       .omp.lastprivate.then.i:
1437 // CHECK2-NEXT:    br label [[DOTOMP_OUTLINED__5_EXIT]]
1438 // CHECK2:       .omp_outlined..5.exit:
1439 // CHECK2-NEXT:    ret i32 0
1440 //
1441 //
1442 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_dup.
1443 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] {
1444 // CHECK2-NEXT:  entry:
1445 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1446 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1447 // CHECK2-NEXT:    [[DOTADDR2:%.*]] = alloca i32, align 4
1448 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1449 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1450 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
1451 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1452 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0
1453 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
1454 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
1455 // CHECK2-NEXT:    store i32 [[TMP6]], ptr [[TMP5]], align 8
1456 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1
1457 // CHECK2-NEXT:    ret void
1458 //
1459 //
1460 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
1461 // CHECK2-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
1462 // CHECK2-NEXT:  entry:
1463 // CHECK2-NEXT:    call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)
1464 // CHECK2-NEXT:    ret void
1465 //
1466 //
1467 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ei
1468 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 {
1469 // CHECK2-NEXT:  entry:
1470 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1471 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1472 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1473 // CHECK2-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1474 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1475 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
1476 // CHECK2-NEXT:    call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1477 // CHECK2-NEXT:    ret void
1478 //
1479 //
1480 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ei
1481 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 {
1482 // CHECK2-NEXT:  entry:
1483 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1484 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1485 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1486 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1487 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1488 // CHECK2-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1489 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1490 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
1491 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
1492 // CHECK2-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
1493 // CHECK2-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
1494 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1495 // CHECK2-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1
1496 // CHECK2-NEXT:    [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i8
1497 // CHECK2-NEXT:    store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
1498 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
1499 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @_ZN1SC2Ei.omp_outlined, ptr [[THIS1]], ptr [[C_ADDR]], i64 [[TMP2]])
1500 // CHECK2-NEXT:    ret void
1501 //
1502 //
1503 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ei.omp_outlined
1504 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
1505 // CHECK2-NEXT:  entry:
1506 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1507 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1508 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1509 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1510 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1511 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8
1512 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1513 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1514 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1515 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
1516 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1517 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1518 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1519 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1520 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1521 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1522 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1523 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1524 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1525 // CHECK2-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]])
1526 // CHECK2-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
1527 // CHECK2-NEXT:    br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1528 // CHECK2:       omp_if.then:
1529 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 0
1530 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP6]], align 8
1531 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 1
1532 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
1533 // CHECK2-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
1534 // CHECK2-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
1535 // CHECK2-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i1
1536 // CHECK2-NEXT:    store ptr [[TMP]], ptr [[_TMP1]], align 8
1537 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4
1538 // CHECK2-NEXT:    store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1539 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1540 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
1541 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1542 // CHECK2-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
1543 // CHECK2-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4
1544 // CHECK2-NEXT:    [[TMP11:%.*]] = select i1 [[LOADEDV]], i32 2, i32 0
1545 // CHECK2-NEXT:    [[TMP12:%.*]] = or i32 [[TMP11]], 1
1546 // CHECK2-NEXT:    [[TMP13:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP3]], i32 [[TMP12]], i64 80, i64 16, ptr @.omp_task_entry..8)
1547 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP13]], i32 0, i32 0
1548 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP14]], i32 0, i32 0
1549 // CHECK2-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
1550 // CHECK2-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)
1551 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 5
1552 // CHECK2-NEXT:    store i64 0, ptr [[TMP17]], align 8
1553 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 6
1554 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
1555 // CHECK2-NEXT:    [[CONV:%.*]] = sext i32 [[TMP19]] to i64
1556 // CHECK2-NEXT:    store i64 [[CONV]], ptr [[TMP18]], align 8
1557 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 7
1558 // CHECK2-NEXT:    store i64 1, ptr [[TMP20]], align 8
1559 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 9
1560 // CHECK2-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP21]], i8 0, i64 8, i1 false)
1561 // CHECK2-NEXT:    [[TMP22:%.*]] = load i64, ptr [[TMP20]], align 8
1562 // CHECK2-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP3]], ptr [[TMP13]], i32 1, ptr [[TMP17]], ptr [[TMP18]], i64 [[TMP22]], i32 1, i32 2, i64 4, ptr null)
1563 // CHECK2-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
1564 // CHECK2-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP3]])
1565 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1566 // CHECK2:       omp_if.end:
1567 // CHECK2-NEXT:    ret void
1568 //
1569 //
1570 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry..8
1571 // CHECK2-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
1572 // CHECK2-NEXT:  entry:
1573 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1574 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1575 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1576 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1577 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1578 // CHECK2-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1579 // CHECK2-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1580 // CHECK2-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1581 // CHECK2-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1582 // CHECK2-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1583 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1584 // CHECK2-NEXT:    [[TMP_I:%.*]] = alloca i32, align 4
1585 // CHECK2-NEXT:    [[TMP1_I:%.*]] = alloca ptr, align 8
1586 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4
1587 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4
1588 // CHECK2-NEXT:    [[A_I:%.*]] = alloca i32, align 4
1589 // CHECK2-NEXT:    [[TMP4_I:%.*]] = alloca ptr, align 8
1590 // CHECK2-NEXT:    [[A5_I:%.*]] = alloca i32, align 4
1591 // CHECK2-NEXT:    [[TMP6_I:%.*]] = alloca ptr, align 8
1592 // CHECK2-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1593 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1594 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1595 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1596 // CHECK2-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1597 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1598 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1599 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 0
1600 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1601 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1602 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1603 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1604 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
1605 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1606 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
1607 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1608 // CHECK2-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
1609 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1610 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
1611 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1612 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
1613 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META51:![0-9]+]])
1614 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META54:![0-9]+]])
1615 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
1616 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
1617 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
1618 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]]
1619 // CHECK2-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]]
1620 // CHECK2-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]]
1621 // CHECK2-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]]
1622 // CHECK2-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]]
1623 // CHECK2-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META62]]
1624 // CHECK2-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META62]]
1625 // CHECK2-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META62]]
1626 // CHECK2-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META62]]
1627 // CHECK2-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META62]]
1628 // CHECK2-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]]
1629 // CHECK2-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]]
1630 // CHECK2-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
1631 // CHECK2-NEXT:    store ptr [[TMP_I]], ptr [[TMP1_I]], align 8, !noalias [[META62]]
1632 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4:%.*]], ptr [[TMP18]], i32 0, i32 1
1633 // CHECK2-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8
1634 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
1635 // CHECK2-NEXT:    store i32 [[TMP22]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META62]]
1636 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META62]]
1637 // CHECK2-NEXT:    [[SUB3_I:%.*]] = sub nsw i32 [[TMP23]], 1
1638 // CHECK2-NEXT:    store i32 [[SUB3_I]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META62]]
1639 // CHECK2-NEXT:    store ptr [[A_I]], ptr [[TMP4_I]], align 8, !noalias [[META62]]
1640 // CHECK2-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[TMP4_I]], align 8, !noalias [[META62]]
1641 // CHECK2-NEXT:    store i32 0, ptr [[TMP24]], align 4
1642 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META62]]
1643 // CHECK2-NEXT:    [[CMP_I:%.*]] = icmp slt i32 0, [[TMP25]]
1644 // CHECK2-NEXT:    br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__7_EXIT:%.*]]
1645 // CHECK2:       taskloop.if.then.i:
1646 // CHECK2-NEXT:    store ptr [[A5_I]], ptr [[TMP6_I]], align 8, !noalias [[META62]]
1647 // CHECK2-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META62]]
1648 // CHECK2-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32
1649 // CHECK2-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]]
1650 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[TMP18]], i32 0, i32 1
1651 // CHECK2-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
1652 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
1653 // CHECK2:       omp.inner.for.cond.i:
1654 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63:![0-9]+]]
1655 // CHECK2-NEXT:    [[CONV7_I:%.*]] = sext i32 [[TMP29]] to i64
1656 // CHECK2-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
1657 // CHECK2-NEXT:    [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP30]]
1658 // CHECK2-NEXT:    br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
1659 // CHECK2:       omp.inner.for.body.i:
1660 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
1661 // CHECK2-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP6_I]], align 8, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
1662 // CHECK2-NEXT:    store i32 [[TMP31]], ptr [[TMP32]], align 4, !llvm.access.group [[ACC_GRP63]]
1663 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
1664 // CHECK2-NEXT:    [[ADD9_I:%.*]] = add nsw i32 [[TMP33]], 1
1665 // CHECK2-NEXT:    store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META62]], !llvm.access.group [[ACC_GRP63]]
1666 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP64:![0-9]+]]
1667 // CHECK2:       omp.inner.for.end.i:
1668 // CHECK2-NEXT:    br label [[DOTOMP_OUTLINED__7_EXIT]]
1669 // CHECK2:       .omp_outlined..7.exit:
1670 // CHECK2-NEXT:    ret i32 0
1671 //
1672 //
1673 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
1674 // CHECK2-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
1675 // CHECK2-NEXT:  entry:
1676 // CHECK2-NEXT:    call void @__cxx_global_var_init()
1677 // CHECK2-NEXT:    ret void
1678 //
1679 //
1680 // CHECK3-LABEL: define {{[^@]+}}@main
1681 // CHECK3-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1682 // CHECK3-NEXT:  entry:
1683 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1684 // CHECK3-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
1685 // CHECK3-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
1686 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1687 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1688 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1689 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8
1690 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1691 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i8, align 1
1692 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1693 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED5:%.*]] = alloca i64, align 8
1694 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED7:%.*]] = alloca i64, align 8
1695 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1696 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1697 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1698 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1699 // CHECK3-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1700 // CHECK3-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
1701 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1702 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1703 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1704 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
1705 // CHECK3-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
1706 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined, i64 [[TMP3]])
1707 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1708 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1709 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1710 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR__CASTED2]], align 4
1711 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED2]], align 8
1712 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP6]])
1713 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1714 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
1715 // CHECK3-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
1716 // CHECK3-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_3]], align 1
1717 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1718 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_4]], align 4
1719 // CHECK3-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1
1720 // CHECK3-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP9]] to i1
1721 // CHECK3-NEXT:    [[STOREDV6:%.*]] = zext i1 [[LOADEDV]] to i8
1722 // CHECK3-NEXT:    store i8 [[STOREDV6]], ptr [[DOTCAPTURE_EXPR__CASTED5]], align 1
1723 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED5]], align 8
1724 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1725 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED7]], align 4
1726 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED7]], align 8
1727 // CHECK3-NEXT:    [[TMP13:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_3]], align 1
1728 // CHECK3-NEXT:    [[LOADEDV8:%.*]] = trunc i8 [[TMP13]] to i1
1729 // CHECK3-NEXT:    br i1 [[LOADEDV8]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1730 // CHECK3:       omp_if.then:
1731 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.4, ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]])
1732 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1733 // CHECK3:       omp_if.else:
1734 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1735 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
1736 // CHECK3-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
1737 // CHECK3-NEXT:    call void @main.omp_outlined.4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[I]], ptr [[ARGC_ADDR]], ptr [[ARGV_ADDR]], i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR2:[0-9]+]]
1738 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1739 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1740 // CHECK3:       omp_if.end:
1741 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
1742 // CHECK3-NEXT:    ret i32 [[TMP14]]
1743 //
1744 //
1745 // CHECK3-LABEL: define {{[^@]+}}@main.omp_outlined
1746 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
1747 // CHECK3-NEXT:  entry:
1748 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1749 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1750 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1751 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
1752 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1753 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1754 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1755 // CHECK3-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1756 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1757 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1758 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
1759 // CHECK3-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
1760 // CHECK3-NEXT:    br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1761 // CHECK3:       omp_if.then:
1762 // CHECK3-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
1763 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
1764 // CHECK3-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 33, i64 80, i64 1, ptr @.omp_task_entry.)
1765 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0
1766 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 4
1767 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[TMP7]], align 8
1768 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 5
1769 // CHECK3-NEXT:    store i64 0, ptr [[TMP8]], align 8
1770 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6
1771 // CHECK3-NEXT:    store i64 9, ptr [[TMP9]], align 8
1772 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7
1773 // CHECK3-NEXT:    store i64 1, ptr [[TMP10]], align 8
1774 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9
1775 // CHECK3-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP11]], i8 0, i64 8, i1 false)
1776 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[TMP10]], align 8
1777 // CHECK3-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP12]], i32 1, i32 0, i64 0, ptr null)
1778 // CHECK3-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
1779 // CHECK3-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
1780 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1781 // CHECK3:       omp_if.end:
1782 // CHECK3-NEXT:    ret void
1783 //
1784 //
1785 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
1786 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
1787 // CHECK3-NEXT:  entry:
1788 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1789 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1790 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1791 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1792 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1793 // CHECK3-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1794 // CHECK3-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1795 // CHECK3-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1796 // CHECK3-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1797 // CHECK3-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1798 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1799 // CHECK3-NEXT:    [[I_I:%.*]] = alloca i32, align 4
1800 // CHECK3-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1801 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1802 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1803 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1804 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1805 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1806 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1807 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1808 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1809 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1810 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1811 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1812 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
1813 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1814 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
1815 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1816 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
1817 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1818 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
1819 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1820 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
1821 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1822 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1823 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1824 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1825 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1826 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1827 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1828 // CHECK3-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1829 // CHECK3-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1830 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1831 // CHECK3-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1832 // CHECK3-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1833 // CHECK3-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1834 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1835 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1836 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1837 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1838 // CHECK3-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1839 // CHECK3-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32
1840 // CHECK3-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1841 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
1842 // CHECK3:       omp.inner.for.cond.i:
1843 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1844 // CHECK3-NEXT:    [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64
1845 // CHECK3-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1846 // CHECK3-NEXT:    [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]
1847 // CHECK3-NEXT:    br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1848 // CHECK3:       omp.inner.for.body.i:
1849 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1850 // CHECK3-NEXT:    store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META14]]
1851 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1852 // CHECK3-NEXT:    [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1
1853 // CHECK3-NEXT:    store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1854 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP15:![0-9]+]]
1855 // CHECK3:       .omp_outlined..exit:
1856 // CHECK3-NEXT:    ret i32 0
1857 //
1858 //
1859 // CHECK3-LABEL: define {{[^@]+}}@main.omp_outlined.1
1860 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
1861 // CHECK3-NEXT:  entry:
1862 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1863 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1864 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1865 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1
1866 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1867 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1868 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1869 // CHECK3-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1870 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1871 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1872 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
1873 // CHECK3-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
1874 // CHECK3-NEXT:    br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1875 // CHECK3:       omp_if.then:
1876 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
1877 // CHECK3-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 80, i64 1, ptr @.omp_task_entry..3)
1878 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP5]], i32 0, i32 0
1879 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP6]], i32 0, i32 5
1880 // CHECK3-NEXT:    store i64 0, ptr [[TMP7]], align 8
1881 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 6
1882 // CHECK3-NEXT:    store i64 9, ptr [[TMP8]], align 8
1883 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 7
1884 // CHECK3-NEXT:    store i64 1, ptr [[TMP9]], align 8
1885 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP6]], i32 0, i32 9
1886 // CHECK3-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 8, i1 false)
1887 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP9]], align 8
1888 // CHECK3-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP4]] to i64
1889 // CHECK3-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP5]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 1, i64 [[TMP12]], ptr null)
1890 // CHECK3-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
1891 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1892 // CHECK3:       omp_if.end:
1893 // CHECK3-NEXT:    ret void
1894 //
1895 //
1896 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..3
1897 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
1898 // CHECK3-NEXT:  entry:
1899 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1900 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1901 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1902 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1903 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1904 // CHECK3-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1905 // CHECK3-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1906 // CHECK3-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1907 // CHECK3-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1908 // CHECK3-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1909 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1910 // CHECK3-NEXT:    [[I_I:%.*]] = alloca i32, align 4
1911 // CHECK3-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1912 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1913 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1914 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1915 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1916 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1917 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1918 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 0
1919 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1920 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1921 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1922 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1923 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
1924 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1925 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
1926 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1927 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
1928 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1929 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
1930 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1931 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
1932 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
1933 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
1934 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
1935 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]])
1936 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]])
1937 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]]
1938 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]]
1939 // CHECK3-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]]
1940 // CHECK3-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]]
1941 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]]
1942 // CHECK3-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]
1943 // CHECK3-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]]
1944 // CHECK3-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]]
1945 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]]
1946 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]]
1947 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
1948 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]]
1949 // CHECK3-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]]
1950 // CHECK3-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP19]] to i32
1951 // CHECK3-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]]
1952 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
1953 // CHECK3:       omp.inner.for.cond.i:
1954 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32:![0-9]+]]
1955 // CHECK3-NEXT:    [[CONV1_I:%.*]] = sext i32 [[TMP20]] to i64
1956 // CHECK3-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1957 // CHECK3-NEXT:    [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP21]]
1958 // CHECK3-NEXT:    br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__2_EXIT:%.*]]
1959 // CHECK3:       omp.inner.for.body.i:
1960 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1961 // CHECK3-NEXT:    store i32 [[TMP22]], ptr [[I_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1962 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1963 // CHECK3-NEXT:    [[ADD2_I:%.*]] = add nsw i32 [[TMP23]], 1
1964 // CHECK3-NEXT:    store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]], !llvm.access.group [[ACC_GRP32]]
1965 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP33:![0-9]+]]
1966 // CHECK3:       .omp_outlined..2.exit:
1967 // CHECK3-NEXT:    ret i32 0
1968 //
1969 //
1970 // CHECK3-LABEL: define {{[^@]+}}@main.omp_outlined.4
1971 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARGC:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARGV:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1]] {
1972 // CHECK3-NEXT:  entry:
1973 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1974 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1975 // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1976 // CHECK3-NEXT:    [[ARGC_ADDR:%.*]] = alloca ptr, align 8
1977 // CHECK3-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
1978 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1979 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
1980 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8
1981 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1982 // CHECK3-NEXT:    [[_TMP3:%.*]] = alloca i32, align 4
1983 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1984 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4
1985 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4
1986 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8
1987 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1988 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1989 // CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1990 // CHECK3-NEXT:    store ptr [[ARGC]], ptr [[ARGC_ADDR]], align 8
1991 // CHECK3-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
1992 // CHECK3-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1993 // CHECK3-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
1994 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1995 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARGC_ADDR]], align 8
1996 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
1997 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1998 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1999 // CHECK3-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])
2000 // CHECK3-NEXT:    [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
2001 // CHECK3-NEXT:    br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
2002 // CHECK3:       omp_if.then:
2003 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 0
2004 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP7]], align 8
2005 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 1
2006 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP8]], align 8
2007 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 2
2008 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP9]], align 8
2009 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[AGG_CAPTURED]], i32 0, i32 3
2010 // CHECK3-NEXT:    [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
2011 // CHECK3-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP11]] to i1
2012 // CHECK3-NEXT:    [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
2013 // CHECK3-NEXT:    store i8 [[STOREDV]], ptr [[TMP10]], align 8
2014 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
2015 // CHECK3-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
2016 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[TMP1]], align 4
2017 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_4]], align 4
2018 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP1]], align 4
2019 // CHECK3-NEXT:    store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_5]], align 4
2020 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
2021 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP1]], align 4
2022 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
2023 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP15]], i64 [[IDXPROM]]
2024 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
2025 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP1]], align 4
2026 // CHECK3-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP18]] to i64
2027 // CHECK3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[TMP17]], i64 [[IDXPROM7]]
2028 // CHECK3-NEXT:    [[TMP19:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1
2029 // CHECK3-NEXT:    [[CONV:%.*]] = sext i8 [[TMP19]] to i32
2030 // CHECK3-NEXT:    store i32 [[CONV]], ptr [[DOTCAPTURE_EXPR_6]], align 4
2031 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
2032 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP20]], 0
2033 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2034 // CHECK3-NEXT:    [[CONV10:%.*]] = sext i32 [[DIV]] to i64
2035 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4
2036 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4
2037 // CHECK3-NEXT:    [[SUB11:%.*]] = sub i32 [[TMP21]], [[TMP22]]
2038 // CHECK3-NEXT:    [[SUB12:%.*]] = sub i32 [[SUB11]], 1
2039 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB12]], 1
2040 // CHECK3-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD]], 1
2041 // CHECK3-NEXT:    [[CONV14:%.*]] = zext i32 [[DIV13]] to i64
2042 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV10]], [[CONV14]]
2043 // CHECK3-NEXT:    [[SUB15:%.*]] = sub nsw i64 [[MUL]], 1
2044 // CHECK3-NEXT:    store i64 [[SUB15]], ptr [[DOTCAPTURE_EXPR_9]], align 8
2045 // CHECK3-NEXT:    [[TMP23:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i64 88, i64 32, ptr @.omp_task_entry..6)
2046 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP23]], i32 0, i32 0
2047 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP24]], i32 0, i32 0
2048 // CHECK3-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8
2049 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP26]], ptr align 8 [[AGG_CAPTURED]], i64 32, i1 false)
2050 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP23]], i32 0, i32 1
2051 // CHECK3-NEXT:    [[TMP28:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
2052 // CHECK3-NEXT:    [[LOADEDV16:%.*]] = trunc i8 [[TMP28]] to i1
2053 // CHECK3-NEXT:    [[TMP29:%.*]] = sext i1 [[LOADEDV16]] to i32
2054 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 5
2055 // CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 8
2056 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 6
2057 // CHECK3-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
2058 // CHECK3-NEXT:    store i64 [[TMP32]], ptr [[TMP31]], align 8
2059 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 7
2060 // CHECK3-NEXT:    store i64 1, ptr [[TMP33]], align 8
2061 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP24]], i32 0, i32 9
2062 // CHECK3-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP34]], i8 0, i64 8, i1 false)
2063 // CHECK3-NEXT:    [[TMP35:%.*]] = load i64, ptr [[TMP33]], align 8
2064 // CHECK3-NEXT:    [[TMP36:%.*]] = zext i32 [[TMP12]] to i64
2065 // CHECK3-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP23]], i32 [[TMP29]], ptr [[TMP30]], ptr [[TMP31]], i64 [[TMP35]], i32 1, i32 2, i64 [[TMP36]], ptr @.omp_task_dup.)
2066 // CHECK3-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
2067 // CHECK3-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])
2068 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2069 // CHECK3:       omp_if.end:
2070 // CHECK3-NEXT:    ret void
2071 //
2072 //
2073 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2074 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
2075 // CHECK3-NEXT:  entry:
2076 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2077 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
2078 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2079 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
2080 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2081 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP2]], i32 0, i32 0
2082 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
2083 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[TMP4]], align 8
2084 // CHECK3-NEXT:    ret void
2085 //
2086 //
2087 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..6
2088 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
2089 // CHECK3-NEXT:  entry:
2090 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2091 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
2092 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
2093 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
2094 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
2095 // CHECK3-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
2096 // CHECK3-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
2097 // CHECK3-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
2098 // CHECK3-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
2099 // CHECK3-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
2100 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
2101 // CHECK3-NEXT:    [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
2102 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4
2103 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4
2104 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3_I:%.*]] = alloca i32, align 4
2105 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_6_I:%.*]] = alloca i64, align 8
2106 // CHECK3-NEXT:    [[I_I:%.*]] = alloca i32, align 4
2107 // CHECK3-NEXT:    [[J_I:%.*]] = alloca i32, align 4
2108 // CHECK3-NEXT:    [[I14_I:%.*]] = alloca i32, align 4
2109 // CHECK3-NEXT:    [[J15_I:%.*]] = alloca i32, align 4
2110 // CHECK3-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i64, align 8
2111 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2112 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
2113 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
2114 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
2115 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
2116 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
2117 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0
2118 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
2119 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
2120 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
2121 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1
2122 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
2123 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
2124 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
2125 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
2126 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
2127 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
2128 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
2129 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
2130 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
2131 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
2132 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]])
2133 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META39:![0-9]+]])
2134 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META41:![0-9]+]])
2135 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]])
2136 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]])
2137 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META47:![0-9]+]]
2138 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META47]]
2139 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META47]]
2140 // CHECK3-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META47]]
2141 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META47]]
2142 // CHECK3-NEXT:    store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META47]]
2143 // CHECK3-NEXT:    store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META47]]
2144 // CHECK3-NEXT:    store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META47]]
2145 // CHECK3-NEXT:    store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META47]]
2146 // CHECK3-NEXT:    store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META47]]
2147 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META47]]
2148 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META47]]
2149 // CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META47]]
2150 // CHECK3-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META47]]
2151 // CHECK3-NEXT:    call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2]]
2152 // CHECK3-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8
2153 // CHECK3-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META47]]
2154 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2:%.*]], ptr [[TMP19]], i32 0, i32 1
2155 // CHECK3-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8
2156 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
2157 // CHECK3-NEXT:    store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
2158 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
2159 // CHECK3-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
2160 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
2161 // CHECK3-NEXT:    store i32 [[TMP29]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2162 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2
2163 // CHECK3-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8
2164 // CHECK3-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8
2165 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
2166 // CHECK3-NEXT:    [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8
2167 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
2168 // CHECK3-NEXT:    [[IDXPROM_I:%.*]] = sext i32 [[TMP35]] to i64
2169 // CHECK3-NEXT:    [[ARRAYIDX_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP32]], i64 [[IDXPROM_I]]
2170 // CHECK3-NEXT:    [[TMP36:%.*]] = load ptr, ptr [[ARRAYIDX_I]], align 8
2171 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
2172 // CHECK3-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[TMP37]], align 8
2173 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
2174 // CHECK3-NEXT:    [[IDXPROM4_I:%.*]] = sext i32 [[TMP39]] to i64
2175 // CHECK3-NEXT:    [[ARRAYIDX5_I:%.*]] = getelementptr inbounds i8, ptr [[TMP36]], i64 [[IDXPROM4_I]]
2176 // CHECK3-NEXT:    [[TMP40:%.*]] = load i8, ptr [[ARRAYIDX5_I]], align 1
2177 // CHECK3-NEXT:    [[CONV_I:%.*]] = sext i8 [[TMP40]] to i32
2178 // CHECK3-NEXT:    store i32 [[CONV_I]], ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
2179 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
2180 // CHECK3-NEXT:    [[CONV7_I:%.*]] = sext i32 [[TMP41]] to i64
2181 // CHECK3-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
2182 // CHECK3-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2183 // CHECK3-NEXT:    [[SUB8_I:%.*]] = sub i32 [[TMP42]], [[TMP43]]
2184 // CHECK3-NEXT:    [[SUB9_I:%.*]] = sub i32 [[SUB8_I]], 1
2185 // CHECK3-NEXT:    [[CONV11_I:%.*]] = zext i32 [[SUB8_I]] to i64
2186 // CHECK3-NEXT:    [[MUL_I:%.*]] = mul nsw i64 [[CONV7_I]], [[CONV11_I]]
2187 // CHECK3-NEXT:    [[SUB12_I:%.*]] = sub nsw i64 [[MUL_I]], 1
2188 // CHECK3-NEXT:    store i64 [[SUB12_I]], ptr [[DOTCAPTURE_EXPR_6_I]], align 8, !noalias [[META47]]
2189 // CHECK3-NEXT:    store i32 0, ptr [[I_I]], align 4, !noalias [[META47]]
2190 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2191 // CHECK3-NEXT:    store i32 [[TMP44]], ptr [[J_I]], align 4, !noalias [[META47]]
2192 // CHECK3-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META47]]
2193 // CHECK3-NEXT:    [[CMP_I:%.*]] = icmp slt i32 0, [[TMP45]]
2194 // CHECK3-NEXT:    br i1 [[CMP_I]], label [[LAND_LHS_TRUE_I:%.*]], label [[TASKLOOP_IF_END_I:%.*]]
2195 // CHECK3:       land.lhs.true.i:
2196 // CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2197 // CHECK3-NEXT:    [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
2198 // CHECK3-NEXT:    [[CMP13_I:%.*]] = icmp slt i32 [[TMP46]], [[TMP47]]
2199 // CHECK3-NEXT:    br i1 [[CMP13_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[TASKLOOP_IF_END_I]]
2200 // CHECK3:       taskloop.if.then.i:
2201 // CHECK3-NEXT:    [[TMP48:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META47]]
2202 // CHECK3-NEXT:    store i64 [[TMP48]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
2203 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 1
2204 // CHECK3-NEXT:    [[TMP50:%.*]] = load ptr, ptr [[TMP49]], align 8
2205 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 2
2206 // CHECK3-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8
2207 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_2]], ptr [[TMP19]], i32 0, i32 3
2208 // CHECK3-NEXT:    [[TMP54:%.*]] = load i8, ptr [[TMP53]], align 1
2209 // CHECK3-NEXT:    [[LOADEDV_I:%.*]] = trunc i8 [[TMP54]] to i1
2210 // CHECK3-NEXT:    br i1 [[LOADEDV_I]], label [[OMP_IF_THEN_I:%.*]], label [[OMP_IF_ELSE_I:%.*]]
2211 // CHECK3:       omp_if.then.i:
2212 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
2213 // CHECK3:       omp.inner.for.cond.i:
2214 // CHECK3-NEXT:    [[TMP55:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48:![0-9]+]]
2215 // CHECK3-NEXT:    [[TMP56:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2216 // CHECK3-NEXT:    [[CMP16_I:%.*]] = icmp ule i64 [[TMP55]], [[TMP56]]
2217 // CHECK3-NEXT:    br i1 [[CMP16_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
2218 // CHECK3:       omp.inner.for.body.i:
2219 // CHECK3-NEXT:    [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2220 // CHECK3-NEXT:    [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2221 // CHECK3-NEXT:    [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2222 // CHECK3-NEXT:    [[SUB17_I:%.*]] = sub i32 [[TMP58]], [[TMP59]]
2223 // CHECK3-NEXT:    [[SUB18_I:%.*]] = sub i32 [[SUB17_I]], 1
2224 // CHECK3-NEXT:    [[CONV22_I:%.*]] = zext i32 [[SUB17_I]] to i64
2225 // CHECK3-NEXT:    [[DIV23_I:%.*]] = sdiv i64 [[TMP57]], [[CONV22_I]]
2226 // CHECK3-NEXT:    [[CONV26_I:%.*]] = trunc i64 [[DIV23_I]] to i32
2227 // CHECK3-NEXT:    store i32 [[CONV26_I]], ptr [[I14_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2228 // CHECK3-NEXT:    [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2229 // CHECK3-NEXT:    [[CONV27_I:%.*]] = sext i32 [[TMP60]] to i64
2230 // CHECK3-NEXT:    [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2231 // CHECK3-NEXT:    [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2232 // CHECK3-NEXT:    [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2233 // CHECK3-NEXT:    [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2234 // CHECK3-NEXT:    [[SUB28_I:%.*]] = sub i32 [[TMP63]], [[TMP64]]
2235 // CHECK3-NEXT:    [[SUB29_I:%.*]] = sub i32 [[SUB28_I]], 1
2236 // CHECK3-NEXT:    [[CONV33_I:%.*]] = zext i32 [[SUB28_I]] to i64
2237 // CHECK3-NEXT:    [[DIV34_I:%.*]] = sdiv i64 [[TMP62]], [[CONV33_I]]
2238 // CHECK3-NEXT:    [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2239 // CHECK3-NEXT:    [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2240 // CHECK3-NEXT:    [[SUB35_I:%.*]] = sub i32 [[TMP65]], [[TMP66]]
2241 // CHECK3-NEXT:    [[SUB36_I:%.*]] = sub i32 [[SUB35_I]], 1
2242 // CHECK3-NEXT:    [[CONV40_I:%.*]] = zext i32 [[SUB35_I]] to i64
2243 // CHECK3-NEXT:    [[MUL41_I:%.*]] = mul nsw i64 [[DIV34_I]], [[CONV40_I]]
2244 // CHECK3-NEXT:    [[SUB42_I:%.*]] = sub nsw i64 [[TMP61]], [[MUL41_I]]
2245 // CHECK3-NEXT:    [[ADD44_I:%.*]] = add nsw i64 [[CONV27_I]], [[SUB42_I]]
2246 // CHECK3-NEXT:    [[CONV45_I:%.*]] = trunc i64 [[ADD44_I]] to i32
2247 // CHECK3-NEXT:    store i32 [[CONV45_I]], ptr [[J15_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2248 // CHECK3-NEXT:    [[TMP67:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2249 // CHECK3-NEXT:    [[ADD46_I:%.*]] = add nsw i64 [[TMP67]], 1
2250 // CHECK3-NEXT:    store i64 [[ADD46_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]]
2251 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP49:![0-9]+]]
2252 // CHECK3:       omp.inner.for.end.i:
2253 // CHECK3-NEXT:    br label [[OMP_IF_END_I:%.*]]
2254 // CHECK3:       omp_if.else.i:
2255 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND47_I:%.*]]
2256 // CHECK3:       omp.inner.for.cond47.i:
2257 // CHECK3-NEXT:    [[TMP68:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
2258 // CHECK3-NEXT:    [[TMP69:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META47]]
2259 // CHECK3-NEXT:    [[CMP48_I:%.*]] = icmp ule i64 [[TMP68]], [[TMP69]]
2260 // CHECK3-NEXT:    br i1 [[CMP48_I]], label [[OMP_INNER_FOR_BODY49_I:%.*]], label [[OMP_INNER_FOR_END82_I:%.*]]
2261 // CHECK3:       omp.inner.for.body49.i:
2262 // CHECK3-NEXT:    [[TMP70:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
2263 // CHECK3-NEXT:    [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
2264 // CHECK3-NEXT:    [[TMP72:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2265 // CHECK3-NEXT:    [[SUB50_I:%.*]] = sub i32 [[TMP71]], [[TMP72]]
2266 // CHECK3-NEXT:    [[SUB51_I:%.*]] = sub i32 [[SUB50_I]], 1
2267 // CHECK3-NEXT:    [[CONV55_I:%.*]] = zext i32 [[SUB50_I]] to i64
2268 // CHECK3-NEXT:    [[DIV56_I:%.*]] = sdiv i64 [[TMP70]], [[CONV55_I]]
2269 // CHECK3-NEXT:    [[CONV59_I:%.*]] = trunc i64 [[DIV56_I]] to i32
2270 // CHECK3-NEXT:    store i32 [[CONV59_I]], ptr [[I14_I]], align 4, !noalias [[META47]]
2271 // CHECK3-NEXT:    [[TMP73:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2272 // CHECK3-NEXT:    [[CONV60_I:%.*]] = sext i32 [[TMP73]] to i64
2273 // CHECK3-NEXT:    [[TMP74:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
2274 // CHECK3-NEXT:    [[TMP75:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
2275 // CHECK3-NEXT:    [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
2276 // CHECK3-NEXT:    [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2277 // CHECK3-NEXT:    [[SUB61_I:%.*]] = sub i32 [[TMP76]], [[TMP77]]
2278 // CHECK3-NEXT:    [[SUB62_I:%.*]] = sub i32 [[SUB61_I]], 1
2279 // CHECK3-NEXT:    [[CONV66_I:%.*]] = zext i32 [[SUB61_I]] to i64
2280 // CHECK3-NEXT:    [[DIV67_I:%.*]] = sdiv i64 [[TMP75]], [[CONV66_I]]
2281 // CHECK3-NEXT:    [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_I]], align 4, !noalias [[META47]]
2282 // CHECK3-NEXT:    [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META47]]
2283 // CHECK3-NEXT:    [[SUB68_I:%.*]] = sub i32 [[TMP78]], [[TMP79]]
2284 // CHECK3-NEXT:    [[SUB69_I:%.*]] = sub i32 [[SUB68_I]], 1
2285 // CHECK3-NEXT:    [[CONV73_I:%.*]] = zext i32 [[SUB68_I]] to i64
2286 // CHECK3-NEXT:    [[MUL74_I:%.*]] = mul nsw i64 [[DIV67_I]], [[CONV73_I]]
2287 // CHECK3-NEXT:    [[SUB75_I:%.*]] = sub nsw i64 [[TMP74]], [[MUL74_I]]
2288 // CHECK3-NEXT:    [[ADD77_I:%.*]] = add nsw i64 [[CONV60_I]], [[SUB75_I]]
2289 // CHECK3-NEXT:    [[CONV78_I:%.*]] = trunc i64 [[ADD77_I]] to i32
2290 // CHECK3-NEXT:    store i32 [[CONV78_I]], ptr [[J15_I]], align 4, !noalias [[META47]]
2291 // CHECK3-NEXT:    [[TMP80:%.*]] = load i64, ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
2292 // CHECK3-NEXT:    [[ADD81_I:%.*]] = add nsw i64 [[TMP80]], 1
2293 // CHECK3-NEXT:    store i64 [[ADD81_I]], ptr [[DOTOMP_IV_I]], align 8, !noalias [[META47]]
2294 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND47_I]], !llvm.loop [[LOOP51:![0-9]+]]
2295 // CHECK3:       omp.inner.for.end82.i:
2296 // CHECK3-NEXT:    br label [[OMP_IF_END_I]]
2297 // CHECK3:       omp_if.end.i:
2298 // CHECK3-NEXT:    br label [[TASKLOOP_IF_END_I]]
2299 // CHECK3:       taskloop.if.end.i:
2300 // CHECK3-NEXT:    [[TMP81:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META47]]
2301 // CHECK3-NEXT:    [[TMP82:%.*]] = icmp ne i32 [[TMP81]], 0
2302 // CHECK3-NEXT:    br i1 [[TMP82]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__5_EXIT:%.*]]
2303 // CHECK3:       .omp.lastprivate.then.i:
2304 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__5_EXIT]]
2305 // CHECK3:       .omp_outlined..5.exit:
2306 // CHECK3-NEXT:    ret i32 0
2307 //
2308 //
2309 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_dup.
2310 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR4]] {
2311 // CHECK3-NEXT:  entry:
2312 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2313 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
2314 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca i32, align 4
2315 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2316 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
2317 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
2318 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2319 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0
2320 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
2321 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
2322 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[TMP5]], align 8
2323 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 1
2324 // CHECK3-NEXT:    ret void
2325 //
2326 //
2327 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
2328 // CHECK3-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
2329 // CHECK3-NEXT:  entry:
2330 // CHECK3-NEXT:    call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)
2331 // CHECK3-NEXT:    ret void
2332 //
2333 //
2334 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC1Ei
2335 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8:[0-9]+]] align 2 {
2336 // CHECK3-NEXT:  entry:
2337 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2338 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
2339 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2340 // CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
2341 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2342 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
2343 // CHECK3-NEXT:    call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2344 // CHECK3-NEXT:    ret void
2345 //
2346 //
2347 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ei
2348 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR8]] align 2 {
2349 // CHECK3-NEXT:  entry:
2350 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2351 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
2352 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2353 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2354 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2355 // CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
2356 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2357 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
2358 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
2359 // CHECK3-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
2360 // CHECK3-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
2361 // CHECK3-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2362 // CHECK3-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP1]] to i1
2363 // CHECK3-NEXT:    [[STOREDV2:%.*]] = zext i1 [[LOADEDV]] to i8
2364 // CHECK3-NEXT:    store i8 [[STOREDV2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
2365 // CHECK3-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
2366 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @_ZN1SC2Ei.omp_outlined, ptr [[THIS1]], ptr [[C_ADDR]], i64 [[TMP2]])
2367 // CHECK3-NEXT:    ret void
2368 //
2369 //
2370 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SC2Ei.omp_outlined
2371 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
2372 // CHECK3-NEXT:  entry:
2373 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2374 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2375 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2376 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2377 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2378 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8
2379 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2380 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2381 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2382 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2383 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2384 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2385 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2386 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2387 // CHECK3-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
2388 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2389 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2390 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2391 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2392 // CHECK3-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]])
2393 // CHECK3-NEXT:    [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
2394 // CHECK3-NEXT:    br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
2395 // CHECK3:       omp_if.then:
2396 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 0
2397 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP6]], align 8
2398 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[AGG_CAPTURED]], i32 0, i32 1
2399 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[TMP7]], align 8
2400 // CHECK3-NEXT:    call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
2401 // CHECK3-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
2402 // CHECK3-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP8]] to i1
2403 // CHECK3-NEXT:    store ptr [[TMP]], ptr [[_TMP1]], align 8
2404 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP1]], align 4
2405 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2406 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2407 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP10]], 0
2408 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2409 // CHECK3-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
2410 // CHECK3-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2411 // CHECK3-NEXT:    [[TMP11:%.*]] = select i1 [[LOADEDV]], i32 2, i32 0
2412 // CHECK3-NEXT:    [[TMP12:%.*]] = or i32 [[TMP11]], 1
2413 // CHECK3-NEXT:    [[TMP13:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP3]], i32 [[TMP12]], i64 80, i64 16, ptr @.omp_task_entry..8)
2414 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP13]], i32 0, i32 0
2415 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP14]], i32 0, i32 0
2416 // CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
2417 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)
2418 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 5
2419 // CHECK3-NEXT:    store i64 0, ptr [[TMP17]], align 8
2420 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 6
2421 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2422 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[TMP19]] to i64
2423 // CHECK3-NEXT:    store i64 [[CONV]], ptr [[TMP18]], align 8
2424 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 7
2425 // CHECK3-NEXT:    store i64 1, ptr [[TMP20]], align 8
2426 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 9
2427 // CHECK3-NEXT:    call void @llvm.memset.p0.i64(ptr align 8 [[TMP21]], i8 0, i64 8, i1 false)
2428 // CHECK3-NEXT:    [[TMP22:%.*]] = load i64, ptr [[TMP20]], align 8
2429 // CHECK3-NEXT:    call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP3]], ptr [[TMP13]], i32 1, ptr [[TMP17]], ptr [[TMP18]], i64 [[TMP22]], i32 1, i32 2, i64 4, ptr null)
2430 // CHECK3-NEXT:    call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
2431 // CHECK3-NEXT:    call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP3]])
2432 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2433 // CHECK3:       omp_if.end:
2434 // CHECK3-NEXT:    ret void
2435 //
2436 //
2437 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry..8
2438 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
2439 // CHECK3-NEXT:  entry:
2440 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2441 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
2442 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
2443 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
2444 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
2445 // CHECK3-NEXT:    [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
2446 // CHECK3-NEXT:    [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
2447 // CHECK3-NEXT:    [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
2448 // CHECK3-NEXT:    [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
2449 // CHECK3-NEXT:    [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
2450 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
2451 // CHECK3-NEXT:    [[TMP_I:%.*]] = alloca i32, align 4
2452 // CHECK3-NEXT:    [[TMP1_I:%.*]] = alloca ptr, align 8
2453 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__I:%.*]] = alloca i32, align 4
2454 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2_I:%.*]] = alloca i32, align 4
2455 // CHECK3-NEXT:    [[A_I:%.*]] = alloca i32, align 4
2456 // CHECK3-NEXT:    [[TMP4_I:%.*]] = alloca ptr, align 8
2457 // CHECK3-NEXT:    [[A5_I:%.*]] = alloca i32, align 4
2458 // CHECK3-NEXT:    [[TMP6_I:%.*]] = alloca ptr, align 8
2459 // CHECK3-NEXT:    [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
2460 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2461 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
2462 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
2463 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
2464 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
2465 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
2466 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 0
2467 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
2468 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
2469 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
2470 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
2471 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
2472 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
2473 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
2474 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
2475 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
2476 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
2477 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
2478 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
2479 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
2480 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]])
2481 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]])
2482 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]])
2483 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]])
2484 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]])
2485 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]]
2486 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]]
2487 // CHECK3-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]]
2488 // CHECK3-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]]
2489 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]]
2490 // CHECK3-NEXT:    store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META64]]
2491 // CHECK3-NEXT:    store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META64]]
2492 // CHECK3-NEXT:    store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META64]]
2493 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META64]]
2494 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META64]]
2495 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]]
2496 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]]
2497 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
2498 // CHECK3-NEXT:    store ptr [[TMP_I]], ptr [[TMP1_I]], align 8, !noalias [[META64]]
2499 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4:%.*]], ptr [[TMP18]], i32 0, i32 1
2500 // CHECK3-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8
2501 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
2502 // CHECK3-NEXT:    store i32 [[TMP22]], ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META64]]
2503 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META64]]
2504 // CHECK3-NEXT:    [[SUB3_I:%.*]] = sub nsw i32 [[TMP23]], 1
2505 // CHECK3-NEXT:    store i32 [[SUB3_I]], ptr [[DOTCAPTURE_EXPR_2_I]], align 4, !noalias [[META64]]
2506 // CHECK3-NEXT:    store ptr [[A_I]], ptr [[TMP4_I]], align 8, !noalias [[META64]]
2507 // CHECK3-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[TMP4_I]], align 8, !noalias [[META64]]
2508 // CHECK3-NEXT:    store i32 0, ptr [[TMP24]], align 4
2509 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__I]], align 4, !noalias [[META64]]
2510 // CHECK3-NEXT:    [[CMP_I:%.*]] = icmp slt i32 0, [[TMP25]]
2511 // CHECK3-NEXT:    br i1 [[CMP_I]], label [[TASKLOOP_IF_THEN_I:%.*]], label [[DOTOMP_OUTLINED__7_EXIT:%.*]]
2512 // CHECK3:       taskloop.if.then.i:
2513 // CHECK3-NEXT:    store ptr [[A5_I]], ptr [[TMP6_I]], align 8, !noalias [[META64]]
2514 // CHECK3-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META64]]
2515 // CHECK3-NEXT:    [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32
2516 // CHECK3-NEXT:    store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META64]]
2517 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_4]], ptr [[TMP18]], i32 0, i32 1
2518 // CHECK3-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
2519 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I:%.*]]
2520 // CHECK3:       omp.inner.for.cond.i:
2521 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META64]], !llvm.access.group [[ACC_GRP65:![0-9]+]]
2522 // CHECK3-NEXT:    [[CONV7_I:%.*]] = sext i32 [[TMP29]] to i64
2523 // CHECK3-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META64]], !llvm.access.group [[ACC_GRP65]]
2524 // CHECK3-NEXT:    [[CMP8_I:%.*]] = icmp ule i64 [[CONV7_I]], [[TMP30]]
2525 // CHECK3-NEXT:    br i1 [[CMP8_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
2526 // CHECK3:       omp.inner.for.body.i:
2527 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META64]], !llvm.access.group [[ACC_GRP65]]
2528 // CHECK3-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP6_I]], align 8, !noalias [[META64]], !llvm.access.group [[ACC_GRP65]]
2529 // CHECK3-NEXT:    store i32 [[TMP31]], ptr [[TMP32]], align 4, !llvm.access.group [[ACC_GRP65]]
2530 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META64]], !llvm.access.group [[ACC_GRP65]]
2531 // CHECK3-NEXT:    [[ADD9_I:%.*]] = add nsw i32 [[TMP33]], 1
2532 // CHECK3-NEXT:    store i32 [[ADD9_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META64]], !llvm.access.group [[ACC_GRP65]]
2533 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP66:![0-9]+]]
2534 // CHECK3:       omp.inner.for.end.i:
2535 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__7_EXIT]]
2536 // CHECK3:       .omp_outlined..7.exit:
2537 // CHECK3-NEXT:    ret i32 0
2538 //
2539 //
2540 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
2541 // CHECK3-SAME: () #[[ATTR6]] section "__TEXT,__StaticInit,regular,pure_instructions" {
2542 // CHECK3-NEXT:  entry:
2543 // CHECK3-NEXT:    call void @__cxx_global_var_init()
2544 // CHECK3-NEXT:    ret void
2545 //
2546 //
2547 // CHECK5-LABEL: define {{[^@]+}}@main
2548 // CHECK5-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
2549 // CHECK5-NEXT:  entry:
2550 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2551 // CHECK5-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
2552 // CHECK5-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
2553 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2554 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2555 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2556 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2557 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2558 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2559 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2560 // CHECK5-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
2561 // CHECK5-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i64, align 8
2562 // CHECK5-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i64, align 8
2563 // CHECK5-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
2564 // CHECK5-NEXT:    [[I9:%.*]] = alloca i32, align 4
2565 // CHECK5-NEXT:    [[I20:%.*]] = alloca i32, align 4
2566 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 1
2567 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
2568 // CHECK5-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
2569 // CHECK5-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
2570 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
2571 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
2572 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4
2573 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 8
2574 // CHECK5-NEXT:    [[DOTOMP_LB40:%.*]] = alloca i64, align 8
2575 // CHECK5-NEXT:    [[DOTOMP_UB41:%.*]] = alloca i64, align 8
2576 // CHECK5-NEXT:    [[I42:%.*]] = alloca i32, align 4
2577 // CHECK5-NEXT:    [[J:%.*]] = alloca i32, align 4
2578 // CHECK5-NEXT:    [[DOTOMP_IV45:%.*]] = alloca i64, align 8
2579 // CHECK5-NEXT:    [[I46:%.*]] = alloca i32, align 4
2580 // CHECK5-NEXT:    [[J47:%.*]] = alloca i32, align 4
2581 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2582 // CHECK5-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
2583 // CHECK5-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
2584 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2585 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
2586 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2587 // CHECK5-NEXT:    store i64 9, ptr [[DOTOMP_UB]], align 8
2588 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2589 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
2590 // CHECK5-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2591 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2592 // CHECK5:       omp.inner.for.cond:
2593 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2594 // CHECK5-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
2595 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2596 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
2597 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2598 // CHECK5:       omp.inner.for.body:
2599 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2600 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
2601 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2602 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2603 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2604 // CHECK5:       omp.body.continue:
2605 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2606 // CHECK5:       omp.inner.for.inc:
2607 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2608 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP5]], 1
2609 // CHECK5-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
2610 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
2611 // CHECK5:       omp.inner.for.end:
2612 // CHECK5-NEXT:    store i32 10, ptr [[I]], align 4
2613 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2614 // CHECK5-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2615 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB5]], align 8
2616 // CHECK5-NEXT:    store i64 9, ptr [[DOTOMP_UB6]], align 8
2617 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 8
2618 // CHECK5-NEXT:    [[CONV8:%.*]] = trunc i64 [[TMP7]] to i32
2619 // CHECK5-NEXT:    store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 4
2620 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
2621 // CHECK5:       omp.inner.for.cond10:
2622 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
2623 // CHECK5-NEXT:    [[CONV11:%.*]] = sext i32 [[TMP8]] to i64
2624 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]
2625 // CHECK5-NEXT:    [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]
2626 // CHECK5-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
2627 // CHECK5:       omp.inner.for.body13:
2628 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
2629 // CHECK5-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 1
2630 // CHECK5-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
2631 // CHECK5-NEXT:    store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]
2632 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
2633 // CHECK5:       omp.body.continue16:
2634 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
2635 // CHECK5:       omp.inner.for.inc17:
2636 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
2637 // CHECK5-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP11]], 1
2638 // CHECK5-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
2639 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]
2640 // CHECK5:       omp.inner.for.end19:
2641 // CHECK5-NEXT:    store i32 10, ptr [[I9]], align 4
2642 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2643 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0
2644 // CHECK5-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
2645 // CHECK5-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 1
2646 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2647 // CHECK5-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 4
2648 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2649 // CHECK5-NEXT:    store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 4
2650 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2651 // CHECK5-NEXT:    store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 4
2652 // CHECK5-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
2653 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2654 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
2655 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]
2656 // CHECK5-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
2657 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2658 // CHECK5-NEXT:    [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i64
2659 // CHECK5-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]
2660 // CHECK5-NEXT:    [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 1
2661 // CHECK5-NEXT:    [[CONV30:%.*]] = sext i8 [[TMP20]] to i32
2662 // CHECK5-NEXT:    store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 4
2663 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
2664 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP21]], 0
2665 // CHECK5-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2666 // CHECK5-NEXT:    [[CONV32:%.*]] = sext i32 [[DIV]] to i64
2667 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
2668 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
2669 // CHECK5-NEXT:    [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]
2670 // CHECK5-NEXT:    [[SUB34:%.*]] = sub i32 [[SUB33]], 1
2671 // CHECK5-NEXT:    [[ADD35:%.*]] = add i32 [[SUB34]], 1
2672 // CHECK5-NEXT:    [[DIV36:%.*]] = udiv i32 [[ADD35]], 1
2673 // CHECK5-NEXT:    [[CONV37:%.*]] = zext i32 [[DIV36]] to i64
2674 // CHECK5-NEXT:    [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]
2675 // CHECK5-NEXT:    [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 1
2676 // CHECK5-NEXT:    store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 8
2677 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB40]], align 8
2678 // CHECK5-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 8
2679 // CHECK5-NEXT:    store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 8
2680 // CHECK5-NEXT:    store i32 0, ptr [[I42]], align 4
2681 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
2682 // CHECK5-NEXT:    store i32 [[TMP25]], ptr [[J]], align 4
2683 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
2684 // CHECK5-NEXT:    [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]
2685 // CHECK5-NEXT:    br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
2686 // CHECK5:       land.lhs.true:
2687 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
2688 // CHECK5-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
2689 // CHECK5-NEXT:    [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]
2690 // CHECK5-NEXT:    br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
2691 // CHECK5:       simd.if.then:
2692 // CHECK5-NEXT:    [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 8
2693 // CHECK5-NEXT:    store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 8
2694 // CHECK5-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
2695 // CHECK5-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]
2696 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND48:%.*]]
2697 // CHECK5:       omp.inner.for.cond48:
2698 // CHECK5-NEXT:    [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]
2699 // CHECK5-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]
2700 // CHECK5-NEXT:    [[CMP49:%.*]] = icmp ule i64 [[TMP31]], [[TMP32]]
2701 // CHECK5-NEXT:    br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]
2702 // CHECK5:       omp.inner.for.body50:
2703 // CHECK5-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
2704 // CHECK5-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
2705 // CHECK5-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
2706 // CHECK5-NEXT:    [[SUB51:%.*]] = sub i32 [[TMP34]], [[TMP35]]
2707 // CHECK5-NEXT:    [[SUB52:%.*]] = sub i32 [[SUB51]], 1
2708 // CHECK5-NEXT:    [[ADD53:%.*]] = add i32 [[SUB52]], 1
2709 // CHECK5-NEXT:    [[DIV54:%.*]] = udiv i32 [[ADD53]], 1
2710 // CHECK5-NEXT:    [[MUL55:%.*]] = mul i32 1, [[DIV54]]
2711 // CHECK5-NEXT:    [[CONV56:%.*]] = zext i32 [[MUL55]] to i64
2712 // CHECK5-NEXT:    [[DIV57:%.*]] = sdiv i64 [[TMP33]], [[CONV56]]
2713 // CHECK5-NEXT:    [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 1
2714 // CHECK5-NEXT:    [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]
2715 // CHECK5-NEXT:    [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
2716 // CHECK5-NEXT:    store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]
2717 // CHECK5-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
2718 // CHECK5-NEXT:    [[CONV61:%.*]] = sext i32 [[TMP36]] to i64
2719 // CHECK5-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
2720 // CHECK5-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
2721 // CHECK5-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
2722 // CHECK5-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
2723 // CHECK5-NEXT:    [[SUB62:%.*]] = sub i32 [[TMP39]], [[TMP40]]
2724 // CHECK5-NEXT:    [[SUB63:%.*]] = sub i32 [[SUB62]], 1
2725 // CHECK5-NEXT:    [[ADD64:%.*]] = add i32 [[SUB63]], 1
2726 // CHECK5-NEXT:    [[DIV65:%.*]] = udiv i32 [[ADD64]], 1
2727 // CHECK5-NEXT:    [[MUL66:%.*]] = mul i32 1, [[DIV65]]
2728 // CHECK5-NEXT:    [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
2729 // CHECK5-NEXT:    [[DIV68:%.*]] = sdiv i64 [[TMP38]], [[CONV67]]
2730 // CHECK5-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
2731 // CHECK5-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
2732 // CHECK5-NEXT:    [[SUB69:%.*]] = sub i32 [[TMP41]], [[TMP42]]
2733 // CHECK5-NEXT:    [[SUB70:%.*]] = sub i32 [[SUB69]], 1
2734 // CHECK5-NEXT:    [[ADD71:%.*]] = add i32 [[SUB70]], 1
2735 // CHECK5-NEXT:    [[DIV72:%.*]] = udiv i32 [[ADD71]], 1
2736 // CHECK5-NEXT:    [[MUL73:%.*]] = mul i32 1, [[DIV72]]
2737 // CHECK5-NEXT:    [[CONV74:%.*]] = zext i32 [[MUL73]] to i64
2738 // CHECK5-NEXT:    [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]
2739 // CHECK5-NEXT:    [[SUB76:%.*]] = sub nsw i64 [[TMP37]], [[MUL75]]
2740 // CHECK5-NEXT:    [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 1
2741 // CHECK5-NEXT:    [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]
2742 // CHECK5-NEXT:    [[CONV79:%.*]] = trunc i64 [[ADD78]] to i32
2743 // CHECK5-NEXT:    store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]
2744 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE80:%.*]]
2745 // CHECK5:       omp.body.continue80:
2746 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC81:%.*]]
2747 // CHECK5:       omp.inner.for.inc81:
2748 // CHECK5-NEXT:    [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
2749 // CHECK5-NEXT:    [[ADD82:%.*]] = add nsw i64 [[TMP43]], 1
2750 // CHECK5-NEXT:    store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
2751 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]
2752 // CHECK5:       omp.inner.for.end83:
2753 // CHECK5-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
2754 // CHECK5-NEXT:    [[SUB84:%.*]] = sub nsw i32 [[TMP44]], 0
2755 // CHECK5-NEXT:    [[DIV85:%.*]] = sdiv i32 [[SUB84]], 1
2756 // CHECK5-NEXT:    [[MUL86:%.*]] = mul nsw i32 [[DIV85]], 1
2757 // CHECK5-NEXT:    [[ADD87:%.*]] = add nsw i32 0, [[MUL86]]
2758 // CHECK5-NEXT:    store i32 [[ADD87]], ptr [[I20]], align 4
2759 // CHECK5-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
2760 // CHECK5-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
2761 // CHECK5-NEXT:    [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
2762 // CHECK5-NEXT:    [[SUB88:%.*]] = sub i32 [[TMP46]], [[TMP47]]
2763 // CHECK5-NEXT:    [[SUB89:%.*]] = sub i32 [[SUB88]], 1
2764 // CHECK5-NEXT:    [[ADD90:%.*]] = add i32 [[SUB89]], 1
2765 // CHECK5-NEXT:    [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
2766 // CHECK5-NEXT:    [[MUL92:%.*]] = mul i32 [[DIV91]], 1
2767 // CHECK5-NEXT:    [[ADD93:%.*]] = add i32 [[TMP45]], [[MUL92]]
2768 // CHECK5-NEXT:    store i32 [[ADD93]], ptr [[J47]], align 4
2769 // CHECK5-NEXT:    br label [[SIMD_IF_END]]
2770 // CHECK5:       simd.if.end:
2771 // CHECK5-NEXT:    [[TMP48:%.*]] = load i32, ptr [[RETVAL]], align 4
2772 // CHECK5-NEXT:    ret i32 [[TMP48]]
2773 //
2774 //
2775 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
2776 // CHECK5-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
2777 // CHECK5-NEXT:  entry:
2778 // CHECK5-NEXT:    call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)
2779 // CHECK5-NEXT:    ret void
2780 //
2781 //
2782 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC1Ei
2783 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {
2784 // CHECK5-NEXT:  entry:
2785 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2786 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
2787 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2788 // CHECK5-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
2789 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2790 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
2791 // CHECK5-NEXT:    call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2792 // CHECK5-NEXT:    ret void
2793 //
2794 //
2795 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SC2Ei
2796 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
2797 // CHECK5-NEXT:  entry:
2798 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2799 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
2800 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2801 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2802 // CHECK5-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2803 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2804 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
2805 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2806 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2807 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
2808 // CHECK5-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
2809 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2810 // CHECK5-NEXT:    [[A8:%.*]] = alloca i32, align 4
2811 // CHECK5-NEXT:    [[_TMP9:%.*]] = alloca ptr, align 8
2812 // CHECK5-NEXT:    [[_TMP14:%.*]] = alloca ptr, align 8
2813 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2814 // CHECK5-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
2815 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2816 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
2817 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
2818 // CHECK5-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
2819 // CHECK5-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
2820 // CHECK5-NEXT:    store ptr [[TMP]], ptr [[_TMP2]], align 8
2821 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 4
2822 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2823 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2824 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2825 // CHECK5-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2826 // CHECK5-NEXT:    [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
2827 // CHECK5-NEXT:    store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 4
2828 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2829 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
2830 // CHECK5-NEXT:    [[CONV:%.*]] = sext i32 [[TMP3]] to i64
2831 // CHECK5-NEXT:    store i64 [[CONV]], ptr [[DOTOMP_UB]], align 8
2832 // CHECK5-NEXT:    store ptr [[A]], ptr [[_TMP6]], align 8
2833 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8
2834 // CHECK5-NEXT:    store i32 0, ptr [[TMP4]], align 4
2835 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2836 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
2837 // CHECK5-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
2838 // CHECK5:       simd.if.then:
2839 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2840 // CHECK5-NEXT:    [[CONV7:%.*]] = trunc i64 [[TMP6]] to i32
2841 // CHECK5-NEXT:    store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 4
2842 // CHECK5-NEXT:    store ptr [[A8]], ptr [[_TMP9]], align 8
2843 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2844 // CHECK5:       omp.inner.for.cond:
2845 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
2846 // CHECK5-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP7]] to i64
2847 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP12]]
2848 // CHECK5-NEXT:    [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]
2849 // CHECK5-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2850 // CHECK5:       omp.inner.for.body:
2851 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
2852 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2853 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2854 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !llvm.access.group [[ACC_GRP12]]
2855 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP12]]
2856 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2857 // CHECK5:       omp.body.continue:
2858 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2859 // CHECK5:       omp.inner.for.inc:
2860 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
2861 // CHECK5-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
2862 // CHECK5-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
2863 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
2864 // CHECK5:       omp.inner.for.end:
2865 // CHECK5-NEXT:    [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2866 // CHECK5-NEXT:    store ptr [[A13]], ptr [[_TMP14]], align 8
2867 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2868 // CHECK5-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 0
2869 // CHECK5-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
2870 // CHECK5-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
2871 // CHECK5-NEXT:    [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]
2872 // CHECK5-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8
2873 // CHECK5-NEXT:    store i32 [[ADD18]], ptr [[TMP13]], align 4
2874 // CHECK5-NEXT:    br label [[SIMD_IF_END]]
2875 // CHECK5:       simd.if.end:
2876 // CHECK5-NEXT:    ret void
2877 //
2878 //
2879 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
2880 // CHECK5-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
2881 // CHECK5-NEXT:  entry:
2882 // CHECK5-NEXT:    call void @__cxx_global_var_init()
2883 // CHECK5-NEXT:    ret void
2884 //
2885 //
2886 // CHECK6-LABEL: define {{[^@]+}}@main
2887 // CHECK6-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
2888 // CHECK6-NEXT:  entry:
2889 // CHECK6-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2890 // CHECK6-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
2891 // CHECK6-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
2892 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2893 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2894 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2895 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2896 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2897 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
2898 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2899 // CHECK6-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
2900 // CHECK6-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i64, align 8
2901 // CHECK6-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i64, align 8
2902 // CHECK6-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
2903 // CHECK6-NEXT:    [[I9:%.*]] = alloca i32, align 4
2904 // CHECK6-NEXT:    [[I20:%.*]] = alloca i32, align 4
2905 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 1
2906 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
2907 // CHECK6-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
2908 // CHECK6-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
2909 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
2910 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
2911 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4
2912 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 8
2913 // CHECK6-NEXT:    [[DOTOMP_LB40:%.*]] = alloca i64, align 8
2914 // CHECK6-NEXT:    [[DOTOMP_UB41:%.*]] = alloca i64, align 8
2915 // CHECK6-NEXT:    [[I42:%.*]] = alloca i32, align 4
2916 // CHECK6-NEXT:    [[J:%.*]] = alloca i32, align 4
2917 // CHECK6-NEXT:    [[DOTOMP_IV45:%.*]] = alloca i64, align 8
2918 // CHECK6-NEXT:    [[I46:%.*]] = alloca i32, align 4
2919 // CHECK6-NEXT:    [[J47:%.*]] = alloca i32, align 4
2920 // CHECK6-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2921 // CHECK6-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
2922 // CHECK6-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
2923 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2924 // CHECK6-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
2925 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2926 // CHECK6-NEXT:    store i64 9, ptr [[DOTOMP_UB]], align 8
2927 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2928 // CHECK6-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
2929 // CHECK6-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2930 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2931 // CHECK6:       omp.inner.for.cond:
2932 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2933 // CHECK6-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
2934 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2935 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
2936 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2937 // CHECK6:       omp.inner.for.body:
2938 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2939 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
2940 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2941 // CHECK6-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2942 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2943 // CHECK6:       omp.body.continue:
2944 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2945 // CHECK6:       omp.inner.for.inc:
2946 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2947 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP5]], 1
2948 // CHECK6-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
2949 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
2950 // CHECK6:       omp.inner.for.end:
2951 // CHECK6-NEXT:    store i32 10, ptr [[I]], align 4
2952 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2953 // CHECK6-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2954 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB5]], align 8
2955 // CHECK6-NEXT:    store i64 9, ptr [[DOTOMP_UB6]], align 8
2956 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 8
2957 // CHECK6-NEXT:    [[CONV8:%.*]] = trunc i64 [[TMP7]] to i32
2958 // CHECK6-NEXT:    store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 4
2959 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
2960 // CHECK6:       omp.inner.for.cond10:
2961 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
2962 // CHECK6-NEXT:    [[CONV11:%.*]] = sext i32 [[TMP8]] to i64
2963 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]
2964 // CHECK6-NEXT:    [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]
2965 // CHECK6-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
2966 // CHECK6:       omp.inner.for.body13:
2967 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
2968 // CHECK6-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 1
2969 // CHECK6-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
2970 // CHECK6-NEXT:    store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]
2971 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
2972 // CHECK6:       omp.body.continue16:
2973 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
2974 // CHECK6:       omp.inner.for.inc17:
2975 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
2976 // CHECK6-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP11]], 1
2977 // CHECK6-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
2978 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]
2979 // CHECK6:       omp.inner.for.end19:
2980 // CHECK6-NEXT:    store i32 10, ptr [[I9]], align 4
2981 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2982 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0
2983 // CHECK6-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
2984 // CHECK6-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 1
2985 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2986 // CHECK6-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 4
2987 // CHECK6-NEXT:    [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2988 // CHECK6-NEXT:    store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 4
2989 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2990 // CHECK6-NEXT:    store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 4
2991 // CHECK6-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
2992 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2993 // CHECK6-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
2994 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]
2995 // CHECK6-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
2996 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
2997 // CHECK6-NEXT:    [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i64
2998 // CHECK6-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]
2999 // CHECK6-NEXT:    [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 1
3000 // CHECK6-NEXT:    [[CONV30:%.*]] = sext i8 [[TMP20]] to i32
3001 // CHECK6-NEXT:    store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 4
3002 // CHECK6-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3003 // CHECK6-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP21]], 0
3004 // CHECK6-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3005 // CHECK6-NEXT:    [[CONV32:%.*]] = sext i32 [[DIV]] to i64
3006 // CHECK6-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3007 // CHECK6-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3008 // CHECK6-NEXT:    [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]
3009 // CHECK6-NEXT:    [[SUB34:%.*]] = sub i32 [[SUB33]], 1
3010 // CHECK6-NEXT:    [[ADD35:%.*]] = add i32 [[SUB34]], 1
3011 // CHECK6-NEXT:    [[DIV36:%.*]] = udiv i32 [[ADD35]], 1
3012 // CHECK6-NEXT:    [[CONV37:%.*]] = zext i32 [[DIV36]] to i64
3013 // CHECK6-NEXT:    [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]
3014 // CHECK6-NEXT:    [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 1
3015 // CHECK6-NEXT:    store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 8
3016 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB40]], align 8
3017 // CHECK6-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 8
3018 // CHECK6-NEXT:    store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 8
3019 // CHECK6-NEXT:    store i32 0, ptr [[I42]], align 4
3020 // CHECK6-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3021 // CHECK6-NEXT:    store i32 [[TMP25]], ptr [[J]], align 4
3022 // CHECK6-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3023 // CHECK6-NEXT:    [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]
3024 // CHECK6-NEXT:    br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
3025 // CHECK6:       land.lhs.true:
3026 // CHECK6-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3027 // CHECK6-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3028 // CHECK6-NEXT:    [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]
3029 // CHECK6-NEXT:    br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
3030 // CHECK6:       simd.if.then:
3031 // CHECK6-NEXT:    [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 8
3032 // CHECK6-NEXT:    store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 8
3033 // CHECK6-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
3034 // CHECK6-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]
3035 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND48:%.*]]
3036 // CHECK6:       omp.inner.for.cond48:
3037 // CHECK6-NEXT:    [[TMP31:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]
3038 // CHECK6-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]
3039 // CHECK6-NEXT:    [[CMP49:%.*]] = icmp ule i64 [[TMP31]], [[TMP32]]
3040 // CHECK6-NEXT:    br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]
3041 // CHECK6:       omp.inner.for.body50:
3042 // CHECK6-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3043 // CHECK6-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3044 // CHECK6-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3045 // CHECK6-NEXT:    [[SUB51:%.*]] = sub i32 [[TMP34]], [[TMP35]]
3046 // CHECK6-NEXT:    [[SUB52:%.*]] = sub i32 [[SUB51]], 1
3047 // CHECK6-NEXT:    [[ADD53:%.*]] = add i32 [[SUB52]], 1
3048 // CHECK6-NEXT:    [[DIV54:%.*]] = udiv i32 [[ADD53]], 1
3049 // CHECK6-NEXT:    [[MUL55:%.*]] = mul i32 1, [[DIV54]]
3050 // CHECK6-NEXT:    [[CONV56:%.*]] = zext i32 [[MUL55]] to i64
3051 // CHECK6-NEXT:    [[DIV57:%.*]] = sdiv i64 [[TMP33]], [[CONV56]]
3052 // CHECK6-NEXT:    [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 1
3053 // CHECK6-NEXT:    [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]
3054 // CHECK6-NEXT:    [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
3055 // CHECK6-NEXT:    store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]
3056 // CHECK6-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3057 // CHECK6-NEXT:    [[CONV61:%.*]] = sext i32 [[TMP36]] to i64
3058 // CHECK6-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3059 // CHECK6-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3060 // CHECK6-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3061 // CHECK6-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3062 // CHECK6-NEXT:    [[SUB62:%.*]] = sub i32 [[TMP39]], [[TMP40]]
3063 // CHECK6-NEXT:    [[SUB63:%.*]] = sub i32 [[SUB62]], 1
3064 // CHECK6-NEXT:    [[ADD64:%.*]] = add i32 [[SUB63]], 1
3065 // CHECK6-NEXT:    [[DIV65:%.*]] = udiv i32 [[ADD64]], 1
3066 // CHECK6-NEXT:    [[MUL66:%.*]] = mul i32 1, [[DIV65]]
3067 // CHECK6-NEXT:    [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
3068 // CHECK6-NEXT:    [[DIV68:%.*]] = sdiv i64 [[TMP38]], [[CONV67]]
3069 // CHECK6-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3070 // CHECK6-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3071 // CHECK6-NEXT:    [[SUB69:%.*]] = sub i32 [[TMP41]], [[TMP42]]
3072 // CHECK6-NEXT:    [[SUB70:%.*]] = sub i32 [[SUB69]], 1
3073 // CHECK6-NEXT:    [[ADD71:%.*]] = add i32 [[SUB70]], 1
3074 // CHECK6-NEXT:    [[DIV72:%.*]] = udiv i32 [[ADD71]], 1
3075 // CHECK6-NEXT:    [[MUL73:%.*]] = mul i32 1, [[DIV72]]
3076 // CHECK6-NEXT:    [[CONV74:%.*]] = zext i32 [[MUL73]] to i64
3077 // CHECK6-NEXT:    [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]
3078 // CHECK6-NEXT:    [[SUB76:%.*]] = sub nsw i64 [[TMP37]], [[MUL75]]
3079 // CHECK6-NEXT:    [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 1
3080 // CHECK6-NEXT:    [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]
3081 // CHECK6-NEXT:    [[CONV79:%.*]] = trunc i64 [[ADD78]] to i32
3082 // CHECK6-NEXT:    store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]
3083 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE80:%.*]]
3084 // CHECK6:       omp.body.continue80:
3085 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC81:%.*]]
3086 // CHECK6:       omp.inner.for.inc81:
3087 // CHECK6-NEXT:    [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3088 // CHECK6-NEXT:    [[ADD82:%.*]] = add nsw i64 [[TMP43]], 1
3089 // CHECK6-NEXT:    store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3090 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]
3091 // CHECK6:       omp.inner.for.end83:
3092 // CHECK6-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3093 // CHECK6-NEXT:    [[SUB84:%.*]] = sub nsw i32 [[TMP44]], 0
3094 // CHECK6-NEXT:    [[DIV85:%.*]] = sdiv i32 [[SUB84]], 1
3095 // CHECK6-NEXT:    [[MUL86:%.*]] = mul nsw i32 [[DIV85]], 1
3096 // CHECK6-NEXT:    [[ADD87:%.*]] = add nsw i32 0, [[MUL86]]
3097 // CHECK6-NEXT:    store i32 [[ADD87]], ptr [[I20]], align 4
3098 // CHECK6-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3099 // CHECK6-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3100 // CHECK6-NEXT:    [[TMP47:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3101 // CHECK6-NEXT:    [[SUB88:%.*]] = sub i32 [[TMP46]], [[TMP47]]
3102 // CHECK6-NEXT:    [[SUB89:%.*]] = sub i32 [[SUB88]], 1
3103 // CHECK6-NEXT:    [[ADD90:%.*]] = add i32 [[SUB89]], 1
3104 // CHECK6-NEXT:    [[DIV91:%.*]] = udiv i32 [[ADD90]], 1
3105 // CHECK6-NEXT:    [[MUL92:%.*]] = mul i32 [[DIV91]], 1
3106 // CHECK6-NEXT:    [[ADD93:%.*]] = add i32 [[TMP45]], [[MUL92]]
3107 // CHECK6-NEXT:    store i32 [[ADD93]], ptr [[J47]], align 4
3108 // CHECK6-NEXT:    br label [[SIMD_IF_END]]
3109 // CHECK6:       simd.if.end:
3110 // CHECK6-NEXT:    [[TMP48:%.*]] = load i32, ptr [[RETVAL]], align 4
3111 // CHECK6-NEXT:    ret i32 [[TMP48]]
3112 //
3113 //
3114 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init
3115 // CHECK6-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
3116 // CHECK6-NEXT:  entry:
3117 // CHECK6-NEXT:    call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)
3118 // CHECK6-NEXT:    ret void
3119 //
3120 //
3121 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1Ei
3122 // CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {
3123 // CHECK6-NEXT:  entry:
3124 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3125 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
3126 // CHECK6-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3127 // CHECK6-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
3128 // CHECK6-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3129 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
3130 // CHECK6-NEXT:    call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
3131 // CHECK6-NEXT:    ret void
3132 //
3133 //
3134 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2Ei
3135 // CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
3136 // CHECK6-NEXT:  entry:
3137 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3138 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
3139 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3140 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3141 // CHECK6-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
3142 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
3143 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3144 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3145 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3146 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
3147 // CHECK6-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
3148 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3149 // CHECK6-NEXT:    [[A8:%.*]] = alloca i32, align 4
3150 // CHECK6-NEXT:    [[_TMP9:%.*]] = alloca ptr, align 8
3151 // CHECK6-NEXT:    [[_TMP14:%.*]] = alloca ptr, align 8
3152 // CHECK6-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3153 // CHECK6-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
3154 // CHECK6-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3155 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
3156 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
3157 // CHECK6-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
3158 // CHECK6-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
3159 // CHECK6-NEXT:    store ptr [[TMP]], ptr [[_TMP2]], align 8
3160 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 4
3161 // CHECK6-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 4
3162 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3163 // CHECK6-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3164 // CHECK6-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3165 // CHECK6-NEXT:    [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
3166 // CHECK6-NEXT:    store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 4
3167 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3168 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
3169 // CHECK6-NEXT:    [[CONV:%.*]] = sext i32 [[TMP3]] to i64
3170 // CHECK6-NEXT:    store i64 [[CONV]], ptr [[DOTOMP_UB]], align 8
3171 // CHECK6-NEXT:    store ptr [[A]], ptr [[_TMP6]], align 8
3172 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8
3173 // CHECK6-NEXT:    store i32 0, ptr [[TMP4]], align 4
3174 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3175 // CHECK6-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
3176 // CHECK6-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
3177 // CHECK6:       simd.if.then:
3178 // CHECK6-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3179 // CHECK6-NEXT:    [[CONV7:%.*]] = trunc i64 [[TMP6]] to i32
3180 // CHECK6-NEXT:    store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 4
3181 // CHECK6-NEXT:    store ptr [[A8]], ptr [[_TMP9]], align 8
3182 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3183 // CHECK6:       omp.inner.for.cond:
3184 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
3185 // CHECK6-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP7]] to i64
3186 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP12]]
3187 // CHECK6-NEXT:    [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]
3188 // CHECK6-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3189 // CHECK6:       omp.inner.for.body:
3190 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
3191 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
3192 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3193 // CHECK6-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !llvm.access.group [[ACC_GRP12]]
3194 // CHECK6-NEXT:    store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP12]]
3195 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3196 // CHECK6:       omp.body.continue:
3197 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3198 // CHECK6:       omp.inner.for.inc:
3199 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
3200 // CHECK6-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
3201 // CHECK6-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
3202 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
3203 // CHECK6:       omp.inner.for.end:
3204 // CHECK6-NEXT:    [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3205 // CHECK6-NEXT:    store ptr [[A13]], ptr [[_TMP14]], align 8
3206 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3207 // CHECK6-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 0
3208 // CHECK6-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
3209 // CHECK6-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
3210 // CHECK6-NEXT:    [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]
3211 // CHECK6-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8
3212 // CHECK6-NEXT:    store i32 [[ADD18]], ptr [[TMP13]], align 4
3213 // CHECK6-NEXT:    br label [[SIMD_IF_END]]
3214 // CHECK6:       simd.if.end:
3215 // CHECK6-NEXT:    ret void
3216 //
3217 //
3218 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
3219 // CHECK6-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
3220 // CHECK6-NEXT:  entry:
3221 // CHECK6-NEXT:    call void @__cxx_global_var_init()
3222 // CHECK6-NEXT:    ret void
3223 //
3224 //
3225 // CHECK7-LABEL: define {{[^@]+}}@main
3226 // CHECK7-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
3227 // CHECK7-NEXT:  entry:
3228 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3229 // CHECK7-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
3230 // CHECK7-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
3231 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3232 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3233 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3234 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3235 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3236 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
3237 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
3238 // CHECK7-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
3239 // CHECK7-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i64, align 8
3240 // CHECK7-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i64, align 8
3241 // CHECK7-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
3242 // CHECK7-NEXT:    [[I9:%.*]] = alloca i32, align 4
3243 // CHECK7-NEXT:    [[I20:%.*]] = alloca i32, align 4
3244 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 1
3245 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
3246 // CHECK7-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
3247 // CHECK7-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
3248 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
3249 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
3250 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4
3251 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 8
3252 // CHECK7-NEXT:    [[DOTOMP_LB40:%.*]] = alloca i64, align 8
3253 // CHECK7-NEXT:    [[DOTOMP_UB41:%.*]] = alloca i64, align 8
3254 // CHECK7-NEXT:    [[I42:%.*]] = alloca i32, align 4
3255 // CHECK7-NEXT:    [[J:%.*]] = alloca i32, align 4
3256 // CHECK7-NEXT:    [[DOTOMP_IV45:%.*]] = alloca i64, align 8
3257 // CHECK7-NEXT:    [[I46:%.*]] = alloca i32, align 4
3258 // CHECK7-NEXT:    [[J47:%.*]] = alloca i32, align 4
3259 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3260 // CHECK7-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
3261 // CHECK7-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
3262 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3263 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
3264 // CHECK7-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3265 // CHECK7-NEXT:    store i64 9, ptr [[DOTOMP_UB]], align 8
3266 // CHECK7-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3267 // CHECK7-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
3268 // CHECK7-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
3269 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3270 // CHECK7:       omp.inner.for.cond:
3271 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3272 // CHECK7-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
3273 // CHECK7-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3274 // CHECK7-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
3275 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3276 // CHECK7:       omp.inner.for.body:
3277 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3278 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3279 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3280 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3281 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3282 // CHECK7:       omp.body.continue:
3283 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3284 // CHECK7:       omp.inner.for.inc:
3285 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3286 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP5]], 1
3287 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
3288 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
3289 // CHECK7:       omp.inner.for.end:
3290 // CHECK7-NEXT:    store i32 10, ptr [[I]], align 4
3291 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3292 // CHECK7-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
3293 // CHECK7-NEXT:    store i64 0, ptr [[DOTOMP_LB5]], align 8
3294 // CHECK7-NEXT:    store i64 9, ptr [[DOTOMP_UB6]], align 8
3295 // CHECK7-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 8
3296 // CHECK7-NEXT:    [[CONV8:%.*]] = trunc i64 [[TMP7]] to i32
3297 // CHECK7-NEXT:    store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 4
3298 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
3299 // CHECK7:       omp.inner.for.cond10:
3300 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
3301 // CHECK7-NEXT:    [[CONV11:%.*]] = sext i32 [[TMP8]] to i64
3302 // CHECK7-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]
3303 // CHECK7-NEXT:    [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]
3304 // CHECK7-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
3305 // CHECK7:       omp.inner.for.body13:
3306 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
3307 // CHECK7-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 1
3308 // CHECK7-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
3309 // CHECK7-NEXT:    store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]
3310 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
3311 // CHECK7:       omp.body.continue16:
3312 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
3313 // CHECK7:       omp.inner.for.inc17:
3314 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
3315 // CHECK7-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP11]], 1
3316 // CHECK7-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
3317 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]
3318 // CHECK7:       omp.inner.for.end19:
3319 // CHECK7-NEXT:    store i32 10, ptr [[I9]], align 4
3320 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3321 // CHECK7-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0
3322 // CHECK7-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
3323 // CHECK7-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 1
3324 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3325 // CHECK7-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 4
3326 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3327 // CHECK7-NEXT:    store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 4
3328 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3329 // CHECK7-NEXT:    store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 4
3330 // CHECK7-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
3331 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3332 // CHECK7-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
3333 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]
3334 // CHECK7-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
3335 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3336 // CHECK7-NEXT:    [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i64
3337 // CHECK7-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]
3338 // CHECK7-NEXT:    [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 1
3339 // CHECK7-NEXT:    [[CONV30:%.*]] = sext i8 [[TMP20]] to i32
3340 // CHECK7-NEXT:    store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 4
3341 // CHECK7-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3342 // CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP21]], 0
3343 // CHECK7-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3344 // CHECK7-NEXT:    [[CONV32:%.*]] = sext i32 [[DIV]] to i64
3345 // CHECK7-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3346 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3347 // CHECK7-NEXT:    [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]
3348 // CHECK7-NEXT:    [[SUB34:%.*]] = sub i32 [[SUB33]], 1
3349 // CHECK7-NEXT:    [[ADD35:%.*]] = add i32 [[SUB34]], 1
3350 // CHECK7-NEXT:    [[DIV36:%.*]] = udiv i32 [[ADD35]], 1
3351 // CHECK7-NEXT:    [[CONV37:%.*]] = zext i32 [[DIV36]] to i64
3352 // CHECK7-NEXT:    [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]
3353 // CHECK7-NEXT:    [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 1
3354 // CHECK7-NEXT:    store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 8
3355 // CHECK7-NEXT:    store i64 0, ptr [[DOTOMP_LB40]], align 8
3356 // CHECK7-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 8
3357 // CHECK7-NEXT:    store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 8
3358 // CHECK7-NEXT:    store i32 0, ptr [[I42]], align 4
3359 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3360 // CHECK7-NEXT:    store i32 [[TMP25]], ptr [[J]], align 4
3361 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3362 // CHECK7-NEXT:    [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]
3363 // CHECK7-NEXT:    br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
3364 // CHECK7:       land.lhs.true:
3365 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3366 // CHECK7-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3367 // CHECK7-NEXT:    [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]
3368 // CHECK7-NEXT:    br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
3369 // CHECK7:       simd.if.then:
3370 // CHECK7-NEXT:    [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 8
3371 // CHECK7-NEXT:    store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 8
3372 // CHECK7-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
3373 // CHECK7-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]
3374 // CHECK7-NEXT:    [[TMP31:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_21]], align 1
3375 // CHECK7-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP31]] to i1
3376 // CHECK7-NEXT:    br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3377 // CHECK7:       omp_if.then:
3378 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND48:%.*]]
3379 // CHECK7:       omp.inner.for.cond48:
3380 // CHECK7-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]
3381 // CHECK7-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]
3382 // CHECK7-NEXT:    [[CMP49:%.*]] = icmp ule i64 [[TMP32]], [[TMP33]]
3383 // CHECK7-NEXT:    br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]
3384 // CHECK7:       omp.inner.for.body50:
3385 // CHECK7-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3386 // CHECK7-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3387 // CHECK7-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3388 // CHECK7-NEXT:    [[SUB51:%.*]] = sub i32 [[TMP35]], [[TMP36]]
3389 // CHECK7-NEXT:    [[SUB52:%.*]] = sub i32 [[SUB51]], 1
3390 // CHECK7-NEXT:    [[ADD53:%.*]] = add i32 [[SUB52]], 1
3391 // CHECK7-NEXT:    [[DIV54:%.*]] = udiv i32 [[ADD53]], 1
3392 // CHECK7-NEXT:    [[MUL55:%.*]] = mul i32 1, [[DIV54]]
3393 // CHECK7-NEXT:    [[CONV56:%.*]] = zext i32 [[MUL55]] to i64
3394 // CHECK7-NEXT:    [[DIV57:%.*]] = sdiv i64 [[TMP34]], [[CONV56]]
3395 // CHECK7-NEXT:    [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 1
3396 // CHECK7-NEXT:    [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]
3397 // CHECK7-NEXT:    [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
3398 // CHECK7-NEXT:    store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]
3399 // CHECK7-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3400 // CHECK7-NEXT:    [[CONV61:%.*]] = sext i32 [[TMP37]] to i64
3401 // CHECK7-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3402 // CHECK7-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3403 // CHECK7-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3404 // CHECK7-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3405 // CHECK7-NEXT:    [[SUB62:%.*]] = sub i32 [[TMP40]], [[TMP41]]
3406 // CHECK7-NEXT:    [[SUB63:%.*]] = sub i32 [[SUB62]], 1
3407 // CHECK7-NEXT:    [[ADD64:%.*]] = add i32 [[SUB63]], 1
3408 // CHECK7-NEXT:    [[DIV65:%.*]] = udiv i32 [[ADD64]], 1
3409 // CHECK7-NEXT:    [[MUL66:%.*]] = mul i32 1, [[DIV65]]
3410 // CHECK7-NEXT:    [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
3411 // CHECK7-NEXT:    [[DIV68:%.*]] = sdiv i64 [[TMP39]], [[CONV67]]
3412 // CHECK7-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3413 // CHECK7-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3414 // CHECK7-NEXT:    [[SUB69:%.*]] = sub i32 [[TMP42]], [[TMP43]]
3415 // CHECK7-NEXT:    [[SUB70:%.*]] = sub i32 [[SUB69]], 1
3416 // CHECK7-NEXT:    [[ADD71:%.*]] = add i32 [[SUB70]], 1
3417 // CHECK7-NEXT:    [[DIV72:%.*]] = udiv i32 [[ADD71]], 1
3418 // CHECK7-NEXT:    [[MUL73:%.*]] = mul i32 1, [[DIV72]]
3419 // CHECK7-NEXT:    [[CONV74:%.*]] = zext i32 [[MUL73]] to i64
3420 // CHECK7-NEXT:    [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]
3421 // CHECK7-NEXT:    [[SUB76:%.*]] = sub nsw i64 [[TMP38]], [[MUL75]]
3422 // CHECK7-NEXT:    [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 1
3423 // CHECK7-NEXT:    [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]
3424 // CHECK7-NEXT:    [[CONV79:%.*]] = trunc i64 [[ADD78]] to i32
3425 // CHECK7-NEXT:    store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]
3426 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE80:%.*]]
3427 // CHECK7:       omp.body.continue80:
3428 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC81:%.*]]
3429 // CHECK7:       omp.inner.for.inc81:
3430 // CHECK7-NEXT:    [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3431 // CHECK7-NEXT:    [[ADD82:%.*]] = add nsw i64 [[TMP44]], 1
3432 // CHECK7-NEXT:    store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3433 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]
3434 // CHECK7:       omp.inner.for.end83:
3435 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
3436 // CHECK7:       omp_if.else:
3437 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND84:%.*]]
3438 // CHECK7:       omp.inner.for.cond84:
3439 // CHECK7-NEXT:    [[TMP45:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3440 // CHECK7-NEXT:    [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8
3441 // CHECK7-NEXT:    [[CMP85:%.*]] = icmp ule i64 [[TMP45]], [[TMP46]]
3442 // CHECK7-NEXT:    br i1 [[CMP85]], label [[OMP_INNER_FOR_BODY86:%.*]], label [[OMP_INNER_FOR_END119:%.*]]
3443 // CHECK7:       omp.inner.for.body86:
3444 // CHECK7-NEXT:    [[TMP47:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3445 // CHECK7-NEXT:    [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3446 // CHECK7-NEXT:    [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3447 // CHECK7-NEXT:    [[SUB87:%.*]] = sub i32 [[TMP48]], [[TMP49]]
3448 // CHECK7-NEXT:    [[SUB88:%.*]] = sub i32 [[SUB87]], 1
3449 // CHECK7-NEXT:    [[ADD89:%.*]] = add i32 [[SUB88]], 1
3450 // CHECK7-NEXT:    [[DIV90:%.*]] = udiv i32 [[ADD89]], 1
3451 // CHECK7-NEXT:    [[MUL91:%.*]] = mul i32 1, [[DIV90]]
3452 // CHECK7-NEXT:    [[CONV92:%.*]] = zext i32 [[MUL91]] to i64
3453 // CHECK7-NEXT:    [[DIV93:%.*]] = sdiv i64 [[TMP47]], [[CONV92]]
3454 // CHECK7-NEXT:    [[MUL94:%.*]] = mul nsw i64 [[DIV93]], 1
3455 // CHECK7-NEXT:    [[ADD95:%.*]] = add nsw i64 0, [[MUL94]]
3456 // CHECK7-NEXT:    [[CONV96:%.*]] = trunc i64 [[ADD95]] to i32
3457 // CHECK7-NEXT:    store i32 [[CONV96]], ptr [[I46]], align 4
3458 // CHECK7-NEXT:    [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3459 // CHECK7-NEXT:    [[CONV97:%.*]] = sext i32 [[TMP50]] to i64
3460 // CHECK7-NEXT:    [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3461 // CHECK7-NEXT:    [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3462 // CHECK7-NEXT:    [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3463 // CHECK7-NEXT:    [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3464 // CHECK7-NEXT:    [[SUB98:%.*]] = sub i32 [[TMP53]], [[TMP54]]
3465 // CHECK7-NEXT:    [[SUB99:%.*]] = sub i32 [[SUB98]], 1
3466 // CHECK7-NEXT:    [[ADD100:%.*]] = add i32 [[SUB99]], 1
3467 // CHECK7-NEXT:    [[DIV101:%.*]] = udiv i32 [[ADD100]], 1
3468 // CHECK7-NEXT:    [[MUL102:%.*]] = mul i32 1, [[DIV101]]
3469 // CHECK7-NEXT:    [[CONV103:%.*]] = zext i32 [[MUL102]] to i64
3470 // CHECK7-NEXT:    [[DIV104:%.*]] = sdiv i64 [[TMP52]], [[CONV103]]
3471 // CHECK7-NEXT:    [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3472 // CHECK7-NEXT:    [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3473 // CHECK7-NEXT:    [[SUB105:%.*]] = sub i32 [[TMP55]], [[TMP56]]
3474 // CHECK7-NEXT:    [[SUB106:%.*]] = sub i32 [[SUB105]], 1
3475 // CHECK7-NEXT:    [[ADD107:%.*]] = add i32 [[SUB106]], 1
3476 // CHECK7-NEXT:    [[DIV108:%.*]] = udiv i32 [[ADD107]], 1
3477 // CHECK7-NEXT:    [[MUL109:%.*]] = mul i32 1, [[DIV108]]
3478 // CHECK7-NEXT:    [[CONV110:%.*]] = zext i32 [[MUL109]] to i64
3479 // CHECK7-NEXT:    [[MUL111:%.*]] = mul nsw i64 [[DIV104]], [[CONV110]]
3480 // CHECK7-NEXT:    [[SUB112:%.*]] = sub nsw i64 [[TMP51]], [[MUL111]]
3481 // CHECK7-NEXT:    [[MUL113:%.*]] = mul nsw i64 [[SUB112]], 1
3482 // CHECK7-NEXT:    [[ADD114:%.*]] = add nsw i64 [[CONV97]], [[MUL113]]
3483 // CHECK7-NEXT:    [[CONV115:%.*]] = trunc i64 [[ADD114]] to i32
3484 // CHECK7-NEXT:    store i32 [[CONV115]], ptr [[J47]], align 4
3485 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE116:%.*]]
3486 // CHECK7:       omp.body.continue116:
3487 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC117:%.*]]
3488 // CHECK7:       omp.inner.for.inc117:
3489 // CHECK7-NEXT:    [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3490 // CHECK7-NEXT:    [[ADD118:%.*]] = add nsw i64 [[TMP57]], 1
3491 // CHECK7-NEXT:    store i64 [[ADD118]], ptr [[DOTOMP_IV45]], align 8
3492 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND84]], !llvm.loop [[LOOP12:![0-9]+]]
3493 // CHECK7:       omp.inner.for.end119:
3494 // CHECK7-NEXT:    br label [[OMP_IF_END]]
3495 // CHECK7:       omp_if.end:
3496 // CHECK7-NEXT:    [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3497 // CHECK7-NEXT:    [[SUB120:%.*]] = sub nsw i32 [[TMP58]], 0
3498 // CHECK7-NEXT:    [[DIV121:%.*]] = sdiv i32 [[SUB120]], 1
3499 // CHECK7-NEXT:    [[MUL122:%.*]] = mul nsw i32 [[DIV121]], 1
3500 // CHECK7-NEXT:    [[ADD123:%.*]] = add nsw i32 0, [[MUL122]]
3501 // CHECK7-NEXT:    store i32 [[ADD123]], ptr [[I20]], align 4
3502 // CHECK7-NEXT:    [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3503 // CHECK7-NEXT:    [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3504 // CHECK7-NEXT:    [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3505 // CHECK7-NEXT:    [[SUB124:%.*]] = sub i32 [[TMP60]], [[TMP61]]
3506 // CHECK7-NEXT:    [[SUB125:%.*]] = sub i32 [[SUB124]], 1
3507 // CHECK7-NEXT:    [[ADD126:%.*]] = add i32 [[SUB125]], 1
3508 // CHECK7-NEXT:    [[DIV127:%.*]] = udiv i32 [[ADD126]], 1
3509 // CHECK7-NEXT:    [[MUL128:%.*]] = mul i32 [[DIV127]], 1
3510 // CHECK7-NEXT:    [[ADD129:%.*]] = add i32 [[TMP59]], [[MUL128]]
3511 // CHECK7-NEXT:    store i32 [[ADD129]], ptr [[J47]], align 4
3512 // CHECK7-NEXT:    br label [[SIMD_IF_END]]
3513 // CHECK7:       simd.if.end:
3514 // CHECK7-NEXT:    [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 4
3515 // CHECK7-NEXT:    ret i32 [[TMP62]]
3516 //
3517 //
3518 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
3519 // CHECK7-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
3520 // CHECK7-NEXT:  entry:
3521 // CHECK7-NEXT:    call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)
3522 // CHECK7-NEXT:    ret void
3523 //
3524 //
3525 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC1Ei
3526 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {
3527 // CHECK7-NEXT:  entry:
3528 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3529 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
3530 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3531 // CHECK7-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
3532 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3533 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
3534 // CHECK7-NEXT:    call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
3535 // CHECK7-NEXT:    ret void
3536 //
3537 //
3538 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SC2Ei
3539 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
3540 // CHECK7-NEXT:  entry:
3541 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3542 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
3543 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3544 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3545 // CHECK7-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
3546 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
3547 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3548 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3549 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3550 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
3551 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
3552 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3553 // CHECK7-NEXT:    [[A8:%.*]] = alloca i32, align 4
3554 // CHECK7-NEXT:    [[_TMP9:%.*]] = alloca ptr, align 8
3555 // CHECK7-NEXT:    [[_TMP14:%.*]] = alloca ptr, align 8
3556 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3557 // CHECK7-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
3558 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3559 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
3560 // CHECK7-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
3561 // CHECK7-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
3562 // CHECK7-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
3563 // CHECK7-NEXT:    store ptr [[TMP]], ptr [[_TMP2]], align 8
3564 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 4
3565 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 4
3566 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3567 // CHECK7-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3568 // CHECK7-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3569 // CHECK7-NEXT:    [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
3570 // CHECK7-NEXT:    store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 4
3571 // CHECK7-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3572 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
3573 // CHECK7-NEXT:    [[CONV:%.*]] = sext i32 [[TMP3]] to i64
3574 // CHECK7-NEXT:    store i64 [[CONV]], ptr [[DOTOMP_UB]], align 8
3575 // CHECK7-NEXT:    store ptr [[A]], ptr [[_TMP6]], align 8
3576 // CHECK7-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8
3577 // CHECK7-NEXT:    store i32 0, ptr [[TMP4]], align 4
3578 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3579 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
3580 // CHECK7-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
3581 // CHECK7:       simd.if.then:
3582 // CHECK7-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3583 // CHECK7-NEXT:    [[CONV7:%.*]] = trunc i64 [[TMP6]] to i32
3584 // CHECK7-NEXT:    store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 4
3585 // CHECK7-NEXT:    store ptr [[A8]], ptr [[_TMP9]], align 8
3586 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3587 // CHECK7:       omp.inner.for.cond:
3588 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
3589 // CHECK7-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP7]] to i64
3590 // CHECK7-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP14]]
3591 // CHECK7-NEXT:    [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]
3592 // CHECK7-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3593 // CHECK7:       omp.inner.for.body:
3594 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
3595 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
3596 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3597 // CHECK7-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !llvm.access.group [[ACC_GRP14]]
3598 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP14]]
3599 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3600 // CHECK7:       omp.body.continue:
3601 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3602 // CHECK7:       omp.inner.for.inc:
3603 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
3604 // CHECK7-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
3605 // CHECK7-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
3606 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
3607 // CHECK7:       omp.inner.for.end:
3608 // CHECK7-NEXT:    [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3609 // CHECK7-NEXT:    store ptr [[A13]], ptr [[_TMP14]], align 8
3610 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3611 // CHECK7-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 0
3612 // CHECK7-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
3613 // CHECK7-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
3614 // CHECK7-NEXT:    [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]
3615 // CHECK7-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8
3616 // CHECK7-NEXT:    store i32 [[ADD18]], ptr [[TMP13]], align 4
3617 // CHECK7-NEXT:    br label [[SIMD_IF_END]]
3618 // CHECK7:       simd.if.end:
3619 // CHECK7-NEXT:    ret void
3620 //
3621 //
3622 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
3623 // CHECK7-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
3624 // CHECK7-NEXT:  entry:
3625 // CHECK7-NEXT:    call void @__cxx_global_var_init()
3626 // CHECK7-NEXT:    ret void
3627 //
3628 //
3629 // CHECK8-LABEL: define {{[^@]+}}@main
3630 // CHECK8-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
3631 // CHECK8-NEXT:  entry:
3632 // CHECK8-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3633 // CHECK8-NEXT:    [[ARGC_ADDR:%.*]] = alloca i32, align 4
3634 // CHECK8-NEXT:    [[ARGV_ADDR:%.*]] = alloca ptr, align 8
3635 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3636 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3637 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3638 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3639 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3640 // CHECK8-NEXT:    [[I:%.*]] = alloca i32, align 4
3641 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
3642 // CHECK8-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
3643 // CHECK8-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i64, align 8
3644 // CHECK8-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i64, align 8
3645 // CHECK8-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
3646 // CHECK8-NEXT:    [[I9:%.*]] = alloca i32, align 4
3647 // CHECK8-NEXT:    [[I20:%.*]] = alloca i32, align 4
3648 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_21:%.*]] = alloca i8, align 1
3649 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_22:%.*]] = alloca i32, align 4
3650 // CHECK8-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
3651 // CHECK8-NEXT:    [[_TMP24:%.*]] = alloca i32, align 4
3652 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
3653 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
3654 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_27:%.*]] = alloca i32, align 4
3655 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_31:%.*]] = alloca i64, align 8
3656 // CHECK8-NEXT:    [[DOTOMP_LB40:%.*]] = alloca i64, align 8
3657 // CHECK8-NEXT:    [[DOTOMP_UB41:%.*]] = alloca i64, align 8
3658 // CHECK8-NEXT:    [[I42:%.*]] = alloca i32, align 4
3659 // CHECK8-NEXT:    [[J:%.*]] = alloca i32, align 4
3660 // CHECK8-NEXT:    [[DOTOMP_IV45:%.*]] = alloca i64, align 8
3661 // CHECK8-NEXT:    [[I46:%.*]] = alloca i32, align 4
3662 // CHECK8-NEXT:    [[J47:%.*]] = alloca i32, align 4
3663 // CHECK8-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3664 // CHECK8-NEXT:    store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
3665 // CHECK8-NEXT:    store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
3666 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3667 // CHECK8-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
3668 // CHECK8-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3669 // CHECK8-NEXT:    store i64 9, ptr [[DOTOMP_UB]], align 8
3670 // CHECK8-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3671 // CHECK8-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
3672 // CHECK8-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
3673 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3674 // CHECK8:       omp.inner.for.cond:
3675 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3676 // CHECK8-NEXT:    [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
3677 // CHECK8-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3678 // CHECK8-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
3679 // CHECK8-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3680 // CHECK8:       omp.inner.for.body:
3681 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3682 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3683 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3684 // CHECK8-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3685 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3686 // CHECK8:       omp.body.continue:
3687 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3688 // CHECK8:       omp.inner.for.inc:
3689 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3690 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP5]], 1
3691 // CHECK8-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
3692 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
3693 // CHECK8:       omp.inner.for.end:
3694 // CHECK8-NEXT:    store i32 10, ptr [[I]], align 4
3695 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3696 // CHECK8-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
3697 // CHECK8-NEXT:    store i64 0, ptr [[DOTOMP_LB5]], align 8
3698 // CHECK8-NEXT:    store i64 9, ptr [[DOTOMP_UB6]], align 8
3699 // CHECK8-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB5]], align 8
3700 // CHECK8-NEXT:    [[CONV8:%.*]] = trunc i64 [[TMP7]] to i32
3701 // CHECK8-NEXT:    store i32 [[CONV8]], ptr [[DOTOMP_IV7]], align 4
3702 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
3703 // CHECK8:       omp.inner.for.cond10:
3704 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
3705 // CHECK8-NEXT:    [[CONV11:%.*]] = sext i32 [[TMP8]] to i64
3706 // CHECK8-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB6]], align 8, !llvm.access.group [[ACC_GRP5]]
3707 // CHECK8-NEXT:    [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP9]]
3708 // CHECK8-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
3709 // CHECK8:       omp.inner.for.body13:
3710 // CHECK8-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
3711 // CHECK8-NEXT:    [[MUL14:%.*]] = mul nsw i32 [[TMP10]], 1
3712 // CHECK8-NEXT:    [[ADD15:%.*]] = add nsw i32 0, [[MUL14]]
3713 // CHECK8-NEXT:    store i32 [[ADD15]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP5]]
3714 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
3715 // CHECK8:       omp.body.continue16:
3716 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
3717 // CHECK8:       omp.inner.for.inc17:
3718 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
3719 // CHECK8-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP11]], 1
3720 // CHECK8-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4, !llvm.access.group [[ACC_GRP5]]
3721 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP6:![0-9]+]]
3722 // CHECK8:       omp.inner.for.end19:
3723 // CHECK8-NEXT:    store i32 10, ptr [[I9]], align 4
3724 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3725 // CHECK8-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP12]], 0
3726 // CHECK8-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
3727 // CHECK8-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_21]], align 1
3728 // CHECK8-NEXT:    [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3729 // CHECK8-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR_22]], align 4
3730 // CHECK8-NEXT:    [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3731 // CHECK8-NEXT:    store i32 [[TMP14]], ptr [[DOTCAPTURE_EXPR_25]], align 4
3732 // CHECK8-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3733 // CHECK8-NEXT:    store i32 [[TMP15]], ptr [[DOTCAPTURE_EXPR_26]], align 4
3734 // CHECK8-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
3735 // CHECK8-NEXT:    [[TMP17:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3736 // CHECK8-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64
3737 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP16]], i64 [[IDXPROM]]
3738 // CHECK8-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
3739 // CHECK8-NEXT:    [[TMP19:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
3740 // CHECK8-NEXT:    [[IDXPROM28:%.*]] = sext i32 [[TMP19]] to i64
3741 // CHECK8-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds i8, ptr [[TMP18]], i64 [[IDXPROM28]]
3742 // CHECK8-NEXT:    [[TMP20:%.*]] = load i8, ptr [[ARRAYIDX29]], align 1
3743 // CHECK8-NEXT:    [[CONV30:%.*]] = sext i8 [[TMP20]] to i32
3744 // CHECK8-NEXT:    store i32 [[CONV30]], ptr [[DOTCAPTURE_EXPR_27]], align 4
3745 // CHECK8-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3746 // CHECK8-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP21]], 0
3747 // CHECK8-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3748 // CHECK8-NEXT:    [[CONV32:%.*]] = sext i32 [[DIV]] to i64
3749 // CHECK8-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3750 // CHECK8-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3751 // CHECK8-NEXT:    [[SUB33:%.*]] = sub i32 [[TMP22]], [[TMP23]]
3752 // CHECK8-NEXT:    [[SUB34:%.*]] = sub i32 [[SUB33]], 1
3753 // CHECK8-NEXT:    [[ADD35:%.*]] = add i32 [[SUB34]], 1
3754 // CHECK8-NEXT:    [[DIV36:%.*]] = udiv i32 [[ADD35]], 1
3755 // CHECK8-NEXT:    [[CONV37:%.*]] = zext i32 [[DIV36]] to i64
3756 // CHECK8-NEXT:    [[MUL38:%.*]] = mul nsw i64 [[CONV32]], [[CONV37]]
3757 // CHECK8-NEXT:    [[SUB39:%.*]] = sub nsw i64 [[MUL38]], 1
3758 // CHECK8-NEXT:    store i64 [[SUB39]], ptr [[DOTCAPTURE_EXPR_31]], align 8
3759 // CHECK8-NEXT:    store i64 0, ptr [[DOTOMP_LB40]], align 8
3760 // CHECK8-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_31]], align 8
3761 // CHECK8-NEXT:    store i64 [[TMP24]], ptr [[DOTOMP_UB41]], align 8
3762 // CHECK8-NEXT:    store i32 0, ptr [[I42]], align 4
3763 // CHECK8-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3764 // CHECK8-NEXT:    store i32 [[TMP25]], ptr [[J]], align 4
3765 // CHECK8-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3766 // CHECK8-NEXT:    [[CMP43:%.*]] = icmp slt i32 0, [[TMP26]]
3767 // CHECK8-NEXT:    br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
3768 // CHECK8:       land.lhs.true:
3769 // CHECK8-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3770 // CHECK8-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3771 // CHECK8-NEXT:    [[CMP44:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]]
3772 // CHECK8-NEXT:    br i1 [[CMP44]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
3773 // CHECK8:       simd.if.then:
3774 // CHECK8-NEXT:    [[TMP29:%.*]] = load i64, ptr [[DOTOMP_LB40]], align 8
3775 // CHECK8-NEXT:    store i64 [[TMP29]], ptr [[DOTOMP_IV45]], align 8
3776 // CHECK8-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
3777 // CHECK8-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[TMP30]], i64 8) ]
3778 // CHECK8-NEXT:    [[TMP31:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_21]], align 1
3779 // CHECK8-NEXT:    [[LOADEDV:%.*]] = trunc i8 [[TMP31]] to i1
3780 // CHECK8-NEXT:    br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3781 // CHECK8:       omp_if.then:
3782 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND48:%.*]]
3783 // CHECK8:       omp.inner.for.cond48:
3784 // CHECK8-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]]
3785 // CHECK8-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8, !llvm.access.group [[ACC_GRP9]]
3786 // CHECK8-NEXT:    [[CMP49:%.*]] = icmp ule i64 [[TMP32]], [[TMP33]]
3787 // CHECK8-NEXT:    br i1 [[CMP49]], label [[OMP_INNER_FOR_BODY50:%.*]], label [[OMP_INNER_FOR_END83:%.*]]
3788 // CHECK8:       omp.inner.for.body50:
3789 // CHECK8-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3790 // CHECK8-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3791 // CHECK8-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3792 // CHECK8-NEXT:    [[SUB51:%.*]] = sub i32 [[TMP35]], [[TMP36]]
3793 // CHECK8-NEXT:    [[SUB52:%.*]] = sub i32 [[SUB51]], 1
3794 // CHECK8-NEXT:    [[ADD53:%.*]] = add i32 [[SUB52]], 1
3795 // CHECK8-NEXT:    [[DIV54:%.*]] = udiv i32 [[ADD53]], 1
3796 // CHECK8-NEXT:    [[MUL55:%.*]] = mul i32 1, [[DIV54]]
3797 // CHECK8-NEXT:    [[CONV56:%.*]] = zext i32 [[MUL55]] to i64
3798 // CHECK8-NEXT:    [[DIV57:%.*]] = sdiv i64 [[TMP34]], [[CONV56]]
3799 // CHECK8-NEXT:    [[MUL58:%.*]] = mul nsw i64 [[DIV57]], 1
3800 // CHECK8-NEXT:    [[ADD59:%.*]] = add nsw i64 0, [[MUL58]]
3801 // CHECK8-NEXT:    [[CONV60:%.*]] = trunc i64 [[ADD59]] to i32
3802 // CHECK8-NEXT:    store i32 [[CONV60]], ptr [[I46]], align 4, !llvm.access.group [[ACC_GRP9]]
3803 // CHECK8-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3804 // CHECK8-NEXT:    [[CONV61:%.*]] = sext i32 [[TMP37]] to i64
3805 // CHECK8-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3806 // CHECK8-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3807 // CHECK8-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3808 // CHECK8-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3809 // CHECK8-NEXT:    [[SUB62:%.*]] = sub i32 [[TMP40]], [[TMP41]]
3810 // CHECK8-NEXT:    [[SUB63:%.*]] = sub i32 [[SUB62]], 1
3811 // CHECK8-NEXT:    [[ADD64:%.*]] = add i32 [[SUB63]], 1
3812 // CHECK8-NEXT:    [[DIV65:%.*]] = udiv i32 [[ADD64]], 1
3813 // CHECK8-NEXT:    [[MUL66:%.*]] = mul i32 1, [[DIV65]]
3814 // CHECK8-NEXT:    [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
3815 // CHECK8-NEXT:    [[DIV68:%.*]] = sdiv i64 [[TMP39]], [[CONV67]]
3816 // CHECK8-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4, !llvm.access.group [[ACC_GRP9]]
3817 // CHECK8-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4, !llvm.access.group [[ACC_GRP9]]
3818 // CHECK8-NEXT:    [[SUB69:%.*]] = sub i32 [[TMP42]], [[TMP43]]
3819 // CHECK8-NEXT:    [[SUB70:%.*]] = sub i32 [[SUB69]], 1
3820 // CHECK8-NEXT:    [[ADD71:%.*]] = add i32 [[SUB70]], 1
3821 // CHECK8-NEXT:    [[DIV72:%.*]] = udiv i32 [[ADD71]], 1
3822 // CHECK8-NEXT:    [[MUL73:%.*]] = mul i32 1, [[DIV72]]
3823 // CHECK8-NEXT:    [[CONV74:%.*]] = zext i32 [[MUL73]] to i64
3824 // CHECK8-NEXT:    [[MUL75:%.*]] = mul nsw i64 [[DIV68]], [[CONV74]]
3825 // CHECK8-NEXT:    [[SUB76:%.*]] = sub nsw i64 [[TMP38]], [[MUL75]]
3826 // CHECK8-NEXT:    [[MUL77:%.*]] = mul nsw i64 [[SUB76]], 1
3827 // CHECK8-NEXT:    [[ADD78:%.*]] = add nsw i64 [[CONV61]], [[MUL77]]
3828 // CHECK8-NEXT:    [[CONV79:%.*]] = trunc i64 [[ADD78]] to i32
3829 // CHECK8-NEXT:    store i32 [[CONV79]], ptr [[J47]], align 4, !llvm.access.group [[ACC_GRP9]]
3830 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE80:%.*]]
3831 // CHECK8:       omp.body.continue80:
3832 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC81:%.*]]
3833 // CHECK8:       omp.inner.for.inc81:
3834 // CHECK8-NEXT:    [[TMP44:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3835 // CHECK8-NEXT:    [[ADD82:%.*]] = add nsw i64 [[TMP44]], 1
3836 // CHECK8-NEXT:    store i64 [[ADD82]], ptr [[DOTOMP_IV45]], align 8, !llvm.access.group [[ACC_GRP9]]
3837 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND48]], !llvm.loop [[LOOP10:![0-9]+]]
3838 // CHECK8:       omp.inner.for.end83:
3839 // CHECK8-NEXT:    br label [[OMP_IF_END:%.*]]
3840 // CHECK8:       omp_if.else:
3841 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND84:%.*]]
3842 // CHECK8:       omp.inner.for.cond84:
3843 // CHECK8-NEXT:    [[TMP45:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3844 // CHECK8-NEXT:    [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB41]], align 8
3845 // CHECK8-NEXT:    [[CMP85:%.*]] = icmp ule i64 [[TMP45]], [[TMP46]]
3846 // CHECK8-NEXT:    br i1 [[CMP85]], label [[OMP_INNER_FOR_BODY86:%.*]], label [[OMP_INNER_FOR_END119:%.*]]
3847 // CHECK8:       omp.inner.for.body86:
3848 // CHECK8-NEXT:    [[TMP47:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3849 // CHECK8-NEXT:    [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3850 // CHECK8-NEXT:    [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3851 // CHECK8-NEXT:    [[SUB87:%.*]] = sub i32 [[TMP48]], [[TMP49]]
3852 // CHECK8-NEXT:    [[SUB88:%.*]] = sub i32 [[SUB87]], 1
3853 // CHECK8-NEXT:    [[ADD89:%.*]] = add i32 [[SUB88]], 1
3854 // CHECK8-NEXT:    [[DIV90:%.*]] = udiv i32 [[ADD89]], 1
3855 // CHECK8-NEXT:    [[MUL91:%.*]] = mul i32 1, [[DIV90]]
3856 // CHECK8-NEXT:    [[CONV92:%.*]] = zext i32 [[MUL91]] to i64
3857 // CHECK8-NEXT:    [[DIV93:%.*]] = sdiv i64 [[TMP47]], [[CONV92]]
3858 // CHECK8-NEXT:    [[MUL94:%.*]] = mul nsw i64 [[DIV93]], 1
3859 // CHECK8-NEXT:    [[ADD95:%.*]] = add nsw i64 0, [[MUL94]]
3860 // CHECK8-NEXT:    [[CONV96:%.*]] = trunc i64 [[ADD95]] to i32
3861 // CHECK8-NEXT:    store i32 [[CONV96]], ptr [[I46]], align 4
3862 // CHECK8-NEXT:    [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3863 // CHECK8-NEXT:    [[CONV97:%.*]] = sext i32 [[TMP50]] to i64
3864 // CHECK8-NEXT:    [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3865 // CHECK8-NEXT:    [[TMP52:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3866 // CHECK8-NEXT:    [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3867 // CHECK8-NEXT:    [[TMP54:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3868 // CHECK8-NEXT:    [[SUB98:%.*]] = sub i32 [[TMP53]], [[TMP54]]
3869 // CHECK8-NEXT:    [[SUB99:%.*]] = sub i32 [[SUB98]], 1
3870 // CHECK8-NEXT:    [[ADD100:%.*]] = add i32 [[SUB99]], 1
3871 // CHECK8-NEXT:    [[DIV101:%.*]] = udiv i32 [[ADD100]], 1
3872 // CHECK8-NEXT:    [[MUL102:%.*]] = mul i32 1, [[DIV101]]
3873 // CHECK8-NEXT:    [[CONV103:%.*]] = zext i32 [[MUL102]] to i64
3874 // CHECK8-NEXT:    [[DIV104:%.*]] = sdiv i64 [[TMP52]], [[CONV103]]
3875 // CHECK8-NEXT:    [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3876 // CHECK8-NEXT:    [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3877 // CHECK8-NEXT:    [[SUB105:%.*]] = sub i32 [[TMP55]], [[TMP56]]
3878 // CHECK8-NEXT:    [[SUB106:%.*]] = sub i32 [[SUB105]], 1
3879 // CHECK8-NEXT:    [[ADD107:%.*]] = add i32 [[SUB106]], 1
3880 // CHECK8-NEXT:    [[DIV108:%.*]] = udiv i32 [[ADD107]], 1
3881 // CHECK8-NEXT:    [[MUL109:%.*]] = mul i32 1, [[DIV108]]
3882 // CHECK8-NEXT:    [[CONV110:%.*]] = zext i32 [[MUL109]] to i64
3883 // CHECK8-NEXT:    [[MUL111:%.*]] = mul nsw i64 [[DIV104]], [[CONV110]]
3884 // CHECK8-NEXT:    [[SUB112:%.*]] = sub nsw i64 [[TMP51]], [[MUL111]]
3885 // CHECK8-NEXT:    [[MUL113:%.*]] = mul nsw i64 [[SUB112]], 1
3886 // CHECK8-NEXT:    [[ADD114:%.*]] = add nsw i64 [[CONV97]], [[MUL113]]
3887 // CHECK8-NEXT:    [[CONV115:%.*]] = trunc i64 [[ADD114]] to i32
3888 // CHECK8-NEXT:    store i32 [[CONV115]], ptr [[J47]], align 4
3889 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE116:%.*]]
3890 // CHECK8:       omp.body.continue116:
3891 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC117:%.*]]
3892 // CHECK8:       omp.inner.for.inc117:
3893 // CHECK8-NEXT:    [[TMP57:%.*]] = load i64, ptr [[DOTOMP_IV45]], align 8
3894 // CHECK8-NEXT:    [[ADD118:%.*]] = add nsw i64 [[TMP57]], 1
3895 // CHECK8-NEXT:    store i64 [[ADD118]], ptr [[DOTOMP_IV45]], align 8
3896 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND84]], !llvm.loop [[LOOP12:![0-9]+]]
3897 // CHECK8:       omp.inner.for.end119:
3898 // CHECK8-NEXT:    br label [[OMP_IF_END]]
3899 // CHECK8:       omp_if.end:
3900 // CHECK8-NEXT:    [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_25]], align 4
3901 // CHECK8-NEXT:    [[SUB120:%.*]] = sub nsw i32 [[TMP58]], 0
3902 // CHECK8-NEXT:    [[DIV121:%.*]] = sdiv i32 [[SUB120]], 1
3903 // CHECK8-NEXT:    [[MUL122:%.*]] = mul nsw i32 [[DIV121]], 1
3904 // CHECK8-NEXT:    [[ADD123:%.*]] = add nsw i32 0, [[MUL122]]
3905 // CHECK8-NEXT:    store i32 [[ADD123]], ptr [[I20]], align 4
3906 // CHECK8-NEXT:    [[TMP59:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3907 // CHECK8-NEXT:    [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_27]], align 4
3908 // CHECK8-NEXT:    [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_26]], align 4
3909 // CHECK8-NEXT:    [[SUB124:%.*]] = sub i32 [[TMP60]], [[TMP61]]
3910 // CHECK8-NEXT:    [[SUB125:%.*]] = sub i32 [[SUB124]], 1
3911 // CHECK8-NEXT:    [[ADD126:%.*]] = add i32 [[SUB125]], 1
3912 // CHECK8-NEXT:    [[DIV127:%.*]] = udiv i32 [[ADD126]], 1
3913 // CHECK8-NEXT:    [[MUL128:%.*]] = mul i32 [[DIV127]], 1
3914 // CHECK8-NEXT:    [[ADD129:%.*]] = add i32 [[TMP59]], [[MUL128]]
3915 // CHECK8-NEXT:    store i32 [[ADD129]], ptr [[J47]], align 4
3916 // CHECK8-NEXT:    br label [[SIMD_IF_END]]
3917 // CHECK8:       simd.if.end:
3918 // CHECK8-NEXT:    [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 4
3919 // CHECK8-NEXT:    ret i32 [[TMP62]]
3920 //
3921 //
3922 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init
3923 // CHECK8-SAME: () #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
3924 // CHECK8-NEXT:  entry:
3925 // CHECK8-NEXT:    call void @_ZN1SC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @s, i32 noundef 1)
3926 // CHECK8-NEXT:    ret void
3927 //
3928 //
3929 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC1Ei
3930 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {
3931 // CHECK8-NEXT:  entry:
3932 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3933 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
3934 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3935 // CHECK8-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
3936 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3937 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
3938 // CHECK8-NEXT:    call void @_ZN1SC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
3939 // CHECK8-NEXT:    ret void
3940 //
3941 //
3942 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SC2Ei
3943 // CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[C:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
3944 // CHECK8-NEXT:  entry:
3945 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3946 // CHECK8-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
3947 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3948 // CHECK8-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3949 // CHECK8-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
3950 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
3951 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
3952 // CHECK8-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3953 // CHECK8-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3954 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
3955 // CHECK8-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
3956 // CHECK8-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3957 // CHECK8-NEXT:    [[A8:%.*]] = alloca i32, align 4
3958 // CHECK8-NEXT:    [[_TMP9:%.*]] = alloca ptr, align 8
3959 // CHECK8-NEXT:    [[_TMP14:%.*]] = alloca ptr, align 8
3960 // CHECK8-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3961 // CHECK8-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
3962 // CHECK8-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3963 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, ptr [[C_ADDR]], align 4
3964 // CHECK8-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
3965 // CHECK8-NEXT:    [[STOREDV:%.*]] = zext i1 [[TOBOOL]] to i8
3966 // CHECK8-NEXT:    store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR_]], align 1
3967 // CHECK8-NEXT:    store ptr [[TMP]], ptr [[_TMP2]], align 8
3968 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 4
3969 // CHECK8-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_3]], align 4
3970 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3971 // CHECK8-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3972 // CHECK8-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3973 // CHECK8-NEXT:    [[SUB5:%.*]] = sub nsw i32 [[DIV]], 1
3974 // CHECK8-NEXT:    store i32 [[SUB5]], ptr [[DOTCAPTURE_EXPR_4]], align 4
3975 // CHECK8-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3976 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
3977 // CHECK8-NEXT:    [[CONV:%.*]] = sext i32 [[TMP3]] to i64
3978 // CHECK8-NEXT:    store i64 [[CONV]], ptr [[DOTOMP_UB]], align 8
3979 // CHECK8-NEXT:    store ptr [[A]], ptr [[_TMP6]], align 8
3980 // CHECK8-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[_TMP6]], align 8
3981 // CHECK8-NEXT:    store i32 0, ptr [[TMP4]], align 4
3982 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
3983 // CHECK8-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
3984 // CHECK8-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
3985 // CHECK8:       simd.if.then:
3986 // CHECK8-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3987 // CHECK8-NEXT:    [[CONV7:%.*]] = trunc i64 [[TMP6]] to i32
3988 // CHECK8-NEXT:    store i32 [[CONV7]], ptr [[DOTOMP_IV]], align 4
3989 // CHECK8-NEXT:    store ptr [[A8]], ptr [[_TMP9]], align 8
3990 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3991 // CHECK8:       omp.inner.for.cond:
3992 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
3993 // CHECK8-NEXT:    [[CONV10:%.*]] = sext i32 [[TMP7]] to i64
3994 // CHECK8-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP14]]
3995 // CHECK8-NEXT:    [[CMP11:%.*]] = icmp ule i64 [[CONV10]], [[TMP8]]
3996 // CHECK8-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3997 // CHECK8:       omp.inner.for.body:
3998 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
3999 // CHECK8-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
4000 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4001 // CHECK8-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP9]], align 8, !llvm.access.group [[ACC_GRP14]]
4002 // CHECK8-NEXT:    store i32 [[ADD]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP14]]
4003 // CHECK8-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4004 // CHECK8:       omp.body.continue:
4005 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4006 // CHECK8:       omp.inner.for.inc:
4007 // CHECK8-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4008 // CHECK8-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP11]], 1
4009 // CHECK8-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4010 // CHECK8-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
4011 // CHECK8:       omp.inner.for.end:
4012 // CHECK8-NEXT:    [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
4013 // CHECK8-NEXT:    store ptr [[A13]], ptr [[_TMP14]], align 8
4014 // CHECK8-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
4015 // CHECK8-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP12]], 0
4016 // CHECK8-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
4017 // CHECK8-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
4018 // CHECK8-NEXT:    [[ADD18:%.*]] = add nsw i32 0, [[MUL17]]
4019 // CHECK8-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP14]], align 8
4020 // CHECK8-NEXT:    store i32 [[ADD18]], ptr [[TMP13]], align 4
4021 // CHECK8-NEXT:    br label [[SIMD_IF_END]]
4022 // CHECK8:       simd.if.end:
4023 // CHECK8-NEXT:    ret void
4024 //
4025 //
4026 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_parallel_master_taskloop_simd_codegen.cpp
4027 // CHECK8-SAME: () #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
4028 // CHECK8-NEXT:  entry:
4029 // CHECK8-NEXT:    call void @__cxx_global_var_init()
4030 // CHECK8-NEXT:    ret void
4031 //