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[clang] Implement lifetime analysis for lifetime_capture_by(X) (#115921)
[llvm-project.git] / clang / test / OpenMP / parallel_master_taskloop_simd_firstprivate_codegen.cpp
blobd81e575b93b463018bd967c192bf85b983cd391e
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s
3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s
5 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=LAMBDA %s
6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=BLOCKS %s
7 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -check-prefix=ARRAY %s
8
9 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
12 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s
13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s
14 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s
15 // expected-no-diagnostics
16
17 #ifndef ARRAY
18 #ifndef HEADER
19 #define HEADER
20
21 template <class T>
22 struct S {
23 T f;
24 S(T a) : f(a) {}
25 S() : f() {}
26 S(const S &s, T t = T()) : f(s.f + t) {}
27 operator T() { return T(); }
28 ~S() {}
29 };
30
31 volatile double g;
32
33 template <typename T>
34 T tmain() {
35 S<T> ttt;
36 S<T> test(ttt);
37 T t_var __attribute__((aligned(128))) = T();
38 T vec[] = {1, 2};
39 S<T> s_arr[] = {1, 2};
40 S<T> var(3);
41 #pragma omp parallel master taskloop simd firstprivate(t_var, vec, s_arr, s_arr, var, var)
42 for (int i = 0; i < 10; ++i) {
43 vec[0] = t_var;
44 s_arr[0] = var;
45 }
46 return T();
47 }
48
49 int main() {
50 static int sivar;
51 #ifdef LAMBDA
52 [&]() {
53
54
55 #pragma omp parallel master taskloop simd firstprivate(g, sivar)
56 for (int i = 0; i < 10; ++i) {
57
58 g = 1;
59 sivar = 11;
60 [&]() {
61 g = 2;
62 sivar = 22;
63 }();
64 }
65 }();
66 return 0;
67 #elif defined(BLOCKS)
68 ^{
69
70 #pragma omp parallel master taskloop simd firstprivate(g, sivar)
71 for (int i = 0; i < 10; ++i) {
72
73 g = 1;
74 sivar = 11;
75 ^{
76 g = 2;
77 sivar = 22;
78 }();
79 }
80 }();
81 return 0;
82 #else
83 S<double> ttt;
84 S<double> test(ttt);
85 int t_var = 0;
86 int vec[] = {1, 2};
87 S<double> s_arr[] = {1, 2};
88 S<double> var(3);
89 #pragma omp parallel master taskloop simd firstprivate(var, t_var, s_arr, vec, s_arr, var, sivar)
90 for (int i = 0; i < 10; ++i) {
91 vec[0] = t_var;
92 s_arr[0] = var;
93 sivar = 33;
94 }
95 return tmain<int>();
96 #endif
97 }
98
99
100
101 // Store original variables in capture struct.
102
103 // Allocate task.
104 // Returns struct kmp_task_t {
105 // [[KMP_TASK_T]] task_data;
106 // [[KMP_TASK_MAIN_TY]] privates;
107 // };
108
109 // Fill kmp_task_t->shareds by copying from original capture argument.
110
111 // Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
112 // Also copy address of private copy to the corresponding shareds reference.
113
114 // Constructors for s_arr and var.
115 // s_arr;
116
117 // var;
118
119 // t_var;
120
121 // vec;
122
123 // sivar;
124
125 // Provide pointer to destructor function, which will destroy private variables at the end of the task.
126
127 // Start task.
128
129
130
131
132
133
134 // Privates actually are used.
135
136
137
138
139
140
141
142
143 // Store original variables in capture struct.
144
145 // Allocate task.
146 // Returns struct kmp_task_t {
147 // [[KMP_TASK_T_TY]] task_data;
148 // [[KMP_TASK_TMAIN_TY]] privates;
149 // };
150
151 // Fill kmp_task_t->shareds by copying from original capture argument.
152
153 // Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
154
155 // t_var;
156
157 // vec;
158
159 // Constructors for s_arr and var.
160 // a_arr;
161
162 // var;
163
164 // Provide pointer to destructor function, which will destroy private variables at the end of the task.
165
166 // Start task.
167
168
169
170 // Privates actually are used.
171
172
173
174
175
176
177 #endif
178 #else
179 struct St {
180 int a, b;
181 St() : a(0), b(0) {}
182 St(const St &) {}
183 ~St() {}
184 };
185
186 void array_func(int n, float a[n], St s[2]) {
187 #pragma omp parallel master taskloop simd firstprivate(a, s)
188 for (int i = 0; i < 10; ++i)
189 ;
190 }
191 #endif
192
193 // CHECK-LABEL: define {{[^@]+}}@main
194 // CHECK-SAME: () #[[ATTR0:[0-9]+]] {
195 // CHECK-NEXT: entry:
196 // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
197 // CHECK-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
198 // CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
199 // CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
200 // CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
201 // CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
202 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
203 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
204 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
205 // CHECK-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]])
206 // CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
207 // CHECK-NEXT: store i32 0, ptr [[T_VAR]], align 4
208 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
209 // CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[S_ARR]], double noundef 1.000000e+00)
210 // CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
211 // CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
212 // CHECK-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
213 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4
214 // CHECK-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
215 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
216 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])
217 // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
218 // CHECK-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
219 // CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
220 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
221 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
222 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
223 // CHECK: arraydestroy.body:
224 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
225 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
226 // CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
227 // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
228 // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
229 // CHECK: arraydestroy.done1:
230 // CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
231 // CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
232 // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4
233 // CHECK-NEXT: ret i32 [[TMP3]]
234 //
235 //
236 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
237 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
238 // CHECK-NEXT: entry:
239 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
240 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
241 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
242 // CHECK-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]])
243 // CHECK-NEXT: ret void
244 //
245 //
246 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
247 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
248 // CHECK-NEXT: entry:
249 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
250 // CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
251 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
252 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
253 // CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
254 // CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8
255 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
256 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
257 // CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8
258 // CHECK-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
259 // CHECK-NEXT: ret void
260 //
261 //
262 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
263 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
264 // CHECK-NEXT: entry:
265 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
266 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
267 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
268 // CHECK-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
269 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
270 // CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
271 // CHECK-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
272 // CHECK-NEXT: ret void
273 //
274 //
275 // CHECK-LABEL: define {{[^@]+}}@main.omp_outlined
276 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] {
277 // CHECK-NEXT: entry:
278 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
279 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
280 // CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
281 // CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
282 // CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
283 // CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
284 // CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
285 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
286 // CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
287 // CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
288 // CHECK-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
289 // CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
290 // CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
291 // CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
292 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
293 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
294 // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
295 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
296 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
297 // CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])
298 // CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
299 // CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
300 // CHECK: omp_if.then:
301 // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
302 // CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8
303 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
304 // CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8
305 // CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
306 // CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 120, i64 16, ptr @.omp_task_entry.)
307 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP9]], i32 0, i32 0
308 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0
309 // CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8
310 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)
311 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP9]], i32 0, i32 1
312 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP13]], i32 0, i32 0
313 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i32 0, i32 0
314 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
315 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP15]]
316 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
317 // CHECK: omp.arraycpy.body:
318 // CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
319 // CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
320 // CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00)
321 // CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
322 // CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
323 // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP15]]
324 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
325 // CHECK: omp.arraycpy.done1:
326 // CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 1
327 // CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP16]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP2]], double noundef 0.000000e+00)
328 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 2
329 // CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
330 // CHECK-NEXT: store i32 [[TMP18]], ptr [[TMP17]], align 8
331 // CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 3
332 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP19]], ptr align 4 [[TMP0]], i64 8, i1 false)
333 // CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP13]], i32 0, i32 4
334 // CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
335 // CHECK-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4
336 // CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3
337 // CHECK-NEXT: store ptr @.omp_task_destructor., ptr [[TMP22]], align 8
338 // CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 5
339 // CHECK-NEXT: store i64 0, ptr [[TMP23]], align 8
340 // CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 6
341 // CHECK-NEXT: store i64 9, ptr [[TMP24]], align 8
342 // CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 7
343 // CHECK-NEXT: store i64 1, ptr [[TMP25]], align 8
344 // CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 9
345 // CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 8, i1 false)
346 // CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[TMP25]], align 8
347 // CHECK-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP9]], i32 1, ptr [[TMP23]], ptr [[TMP24]], i64 [[TMP27]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.)
348 // CHECK-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
349 // CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])
350 // CHECK-NEXT: br label [[OMP_IF_END]]
351 // CHECK: omp_if.end:
352 // CHECK-NEXT: ret void
353 //
354 //
355 // CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map.
356 // CHECK-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]], ptr noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] {
357 // CHECK-NEXT: entry:
358 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
359 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
360 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
361 // CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8
362 // CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8
363 // CHECK-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8
364 // CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
365 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
366 // CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
367 // CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
368 // CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
369 // CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTADDR5]], align 8
370 // CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR]], align 8
371 // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0
372 // CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
373 // CHECK-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8
374 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1
375 // CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
376 // CHECK-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8
377 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 2
378 // CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
379 // CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP12]], align 8
380 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 3
381 // CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
382 // CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP14]], align 8
383 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 4
384 // CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR5]], align 8
385 // CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP16]], align 8
386 // CHECK-NEXT: ret void
387 //
388 //
389 // CHECK-LABEL: define {{[^@]+}}@.omp_task_entry.
390 // CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
391 // CHECK-NEXT: entry:
392 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
393 // CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
394 // CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
395 // CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
396 // CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
397 // CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
398 // CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
399 // CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
400 // CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
401 // CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
402 // CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
403 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
404 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
405 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
406 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
407 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR4_I:%.*]] = alloca ptr, align 8
408 // CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4
409 // CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
410 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
411 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
412 // CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
413 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
414 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
415 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
416 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
417 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
418 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
419 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
420 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
421 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
422 // CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
423 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
424 // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
425 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
426 // CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
427 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
428 // CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
429 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
430 // CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
431 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
432 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
433 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
434 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
435 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
436 // CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
437 // CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
438 // CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
439 // CHECK-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
440 // CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
441 // CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
442 // CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
443 // CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
444 // CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
445 // CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
446 // CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
447 // CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
448 // CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
449 // CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
450 // CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
451 // CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
452 // CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
453 // CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]]
454 // CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]]
455 // CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META14]]
456 // CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
457 // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32
458 // CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
459 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
460 // CHECK: omp.inner.for.cond.i:
461 // CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
462 // CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP28]] to i64
463 // CHECK-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
464 // CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP29]]
465 // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
466 // CHECK: omp.inner.for.body.i:
467 // CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
468 // CHECK-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
469 // CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]]
470 // CHECK-NEXT: store i32 [[TMP31]], ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP15]]
471 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP24]], ptr align 8 [[TMP22]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]]
472 // CHECK-NEXT: store i32 33, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]]
473 // CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
474 // CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP32]], 1
475 // CHECK-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
476 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
477 // CHECK: .omp_outlined..exit:
478 // CHECK-NEXT: ret i32 0
479 //
480 //
481 // CHECK-LABEL: define {{[^@]+}}@.omp_task_dup.
482 // CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
483 // CHECK-NEXT: entry:
484 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
485 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
486 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
487 // CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
488 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
489 // CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
490 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
491 // CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
492 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP4]], i32 0, i32 0
493 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0
494 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
495 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
496 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP8]], i32 0, i32 0
497 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP7]], i32 0, i32 0
498 // CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
499 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i32 0, i32 0
500 // CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
501 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]]
502 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
503 // CHECK: omp.arraycpy.body:
504 // CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
505 // CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
506 // CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00)
507 // CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
508 // CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
509 // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]]
510 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
511 // CHECK: omp.arraycpy.done3:
512 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP8]], i32 0, i32 1
513 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP7]], i32 0, i32 1
514 // CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8
515 // CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP13]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP15]], double noundef 0.000000e+00)
516 // CHECK-NEXT: ret void
517 //
518 //
519 // CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor.
520 // CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
521 // CHECK-NEXT: entry:
522 // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
523 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
524 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
525 // CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
526 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
527 // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
528 // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1
529 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
530 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
531 // CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]]
532 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0
533 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
534 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
535 // CHECK: arraydestroy.body:
536 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
537 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
538 // CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
539 // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
540 // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
541 // CHECK: arraydestroy.done2:
542 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
543 // CHECK-NEXT: ret i32 [[TMP7]]
544 //
545 //
546 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
547 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
548 // CHECK-NEXT: entry:
549 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
550 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
551 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
552 // CHECK-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
553 // CHECK-NEXT: ret void
554 //
555 //
556 // CHECK-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
557 // CHECK-SAME: () #[[ATTR1]] {
558 // CHECK-NEXT: entry:
559 // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
560 // CHECK-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
561 // CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
562 // CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
563 // CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
564 // CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
565 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
566 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
567 // CHECK-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]])
568 // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
569 // CHECK-NEXT: store i32 0, ptr [[T_VAR]], align 128
570 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
571 // CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
572 // CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
573 // CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
574 // CHECK-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
575 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128
576 // CHECK-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
577 // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
578 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])
579 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
580 // CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
581 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
582 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
583 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
584 // CHECK: arraydestroy.body:
585 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
586 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
587 // CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
588 // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
589 // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
590 // CHECK: arraydestroy.done1:
591 // CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
592 // CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
593 // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4
594 // CHECK-NEXT: ret i32 [[TMP3]]
595 //
596 //
597 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
598 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
599 // CHECK-NEXT: entry:
600 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
601 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
602 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
603 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
604 // CHECK-NEXT: store double 0.000000e+00, ptr [[F]], align 8
605 // CHECK-NEXT: ret void
606 //
607 //
608 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
609 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
610 // CHECK-NEXT: entry:
611 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
612 // CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
613 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
614 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
615 // CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
616 // CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8
617 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
618 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
619 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
620 // CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
621 // CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8
622 // CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8
623 // CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
624 // CHECK-NEXT: store double [[ADD]], ptr [[F]], align 8
625 // CHECK-NEXT: ret void
626 //
627 //
628 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
629 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
630 // CHECK-NEXT: entry:
631 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
632 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
633 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
634 // CHECK-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
635 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
636 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
637 // CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
638 // CHECK-NEXT: store double [[TMP0]], ptr [[F]], align 8
639 // CHECK-NEXT: ret void
640 //
641 //
642 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
643 // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
644 // CHECK-NEXT: entry:
645 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
646 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
647 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
648 // CHECK-NEXT: ret void
649 //
650 //
651 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
652 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
653 // CHECK-NEXT: entry:
654 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
655 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
656 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
657 // CHECK-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
658 // CHECK-NEXT: ret void
659 //
660 //
661 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
662 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
663 // CHECK-NEXT: entry:
664 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
665 // CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
666 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
667 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
668 // CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
669 // CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
670 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
671 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
672 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4
673 // CHECK-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
674 // CHECK-NEXT: ret void
675 //
676 //
677 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
678 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
679 // CHECK-NEXT: entry:
680 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
681 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
682 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
683 // CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
684 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
685 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
686 // CHECK-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
687 // CHECK-NEXT: ret void
688 //
689 //
690 // CHECK-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
691 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
692 // CHECK-NEXT: entry:
693 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
694 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
695 // CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
696 // CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
697 // CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
698 // CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
699 // CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
700 // CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
701 // CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
702 // CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
703 // CHECK-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
704 // CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
705 // CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
706 // CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
707 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
708 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
709 // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
710 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
711 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
712 // CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])
713 // CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
714 // CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
715 // CHECK: omp_if.then:
716 // CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0
717 // CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8
718 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 1
719 // CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8
720 // CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
721 // CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, ptr @.omp_task_entry..3)
722 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP9]], i32 0, i32 0
723 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0
724 // CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 128
725 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)
726 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP9]], i32 0, i32 2
727 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP13]], i32 0, i32 0
728 // CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
729 // CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 128
730 // CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 1
731 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP16]], ptr align 4 [[TMP0]], i64 8, i1 false)
732 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 2
733 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0
734 // CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
735 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP18]]
736 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
737 // CHECK: omp.arraycpy.body:
738 // CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
739 // CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
740 // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0)
741 // CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
742 // CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
743 // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]]
744 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
745 // CHECK: omp.arraycpy.done1:
746 // CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 3
747 // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP19]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0)
748 // CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3
749 // CHECK-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP20]], align 8
750 // CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 5
751 // CHECK-NEXT: store i64 0, ptr [[TMP21]], align 8
752 // CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 6
753 // CHECK-NEXT: store i64 9, ptr [[TMP22]], align 16
754 // CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 7
755 // CHECK-NEXT: store i64 1, ptr [[TMP23]], align 8
756 // CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 9
757 // CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP24]], i8 0, i64 8, i1 false)
758 // CHECK-NEXT: [[TMP25:%.*]] = load i64, ptr [[TMP23]], align 8
759 // CHECK-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP9]], i32 1, ptr [[TMP21]], ptr [[TMP22]], i64 [[TMP25]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..4)
760 // CHECK-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
761 // CHECK-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])
762 // CHECK-NEXT: br label [[OMP_IF_END]]
763 // CHECK: omp_if.end:
764 // CHECK-NEXT: ret void
765 //
766 //
767 // CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map..2
768 // CHECK-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6]] {
769 // CHECK-NEXT: entry:
770 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
771 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
772 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
773 // CHECK-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8
774 // CHECK-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8
775 // CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
776 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
777 // CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
778 // CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
779 // CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
780 // CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
781 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0
782 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
783 // CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
784 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1
785 // CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
786 // CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8
787 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2
788 // CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
789 // CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8
790 // CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3
791 // CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
792 // CHECK-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8
793 // CHECK-NEXT: ret void
794 //
795 //
796 // CHECK-LABEL: define {{[^@]+}}@.omp_task_entry..3
797 // CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
798 // CHECK-NEXT: entry:
799 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
800 // CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
801 // CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
802 // CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
803 // CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
804 // CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
805 // CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
806 // CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
807 // CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
808 // CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
809 // CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
810 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
811 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
812 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
813 // CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
814 // CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4
815 // CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
816 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
817 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
818 // CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
819 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
820 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
821 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
822 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0
823 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
824 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
825 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128
826 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2
827 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
828 // CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
829 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
830 // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 16
831 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
832 // CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
833 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
834 // CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64
835 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
836 // CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
837 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
838 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
839 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
840 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
841 // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
842 // CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]]
843 // CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]]
844 // CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
845 // CHECK-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
846 // CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]]
847 // CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]]
848 // CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]]
849 // CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META32]]
850 // CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META32]]
851 // CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META32]]
852 // CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
853 // CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
854 // CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
855 // CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
856 // CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
857 // CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]]
858 // CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]]
859 // CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]]
860 // CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META32]]
861 // CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]]
862 // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32
863 // CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]]
864 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
865 // CHECK: omp.inner.for.cond.i:
866 // CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33:![0-9]+]]
867 // CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP27]] to i64
868 // CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
869 // CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP28]]
870 // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
871 // CHECK: omp.inner.for.body.i:
872 // CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
873 // CHECK-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
874 // CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 128, !llvm.access.group [[ACC_GRP33]]
875 // CHECK-NEXT: store i32 [[TMP30]], ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP33]]
876 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP24]], ptr align 4 [[TMP25]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]]
877 // CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
878 // CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP31]], 1
879 // CHECK-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
880 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]]
881 // CHECK: .omp_outlined..1.exit:
882 // CHECK-NEXT: ret i32 0
883 //
884 //
885 // CHECK-LABEL: define {{[^@]+}}@.omp_task_dup..4
886 // CHECK-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
887 // CHECK-NEXT: entry:
888 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
889 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
890 // CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
891 // CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
892 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
893 // CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
894 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
895 // CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
896 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP4]], i32 0, i32 0
897 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0
898 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128
899 // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2
900 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP8]], i32 0, i32 2
901 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP7]], i32 0, i32 0
902 // CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
903 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP9]], i32 0, i32 0
904 // CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
905 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]]
906 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
907 // CHECK: omp.arraycpy.body:
908 // CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
909 // CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
910 // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0)
911 // CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
912 // CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
913 // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]]
914 // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
915 // CHECK: omp.arraycpy.done3:
916 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP8]], i32 0, i32 3
917 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP7]], i32 0, i32 1
918 // CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8
919 // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]], i32 noundef 0)
920 // CHECK-NEXT: ret void
921 //
922 //
923 // CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor..5
924 // CHECK-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
925 // CHECK-NEXT: entry:
926 // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
927 // CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
928 // CHECK-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
929 // CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
930 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
931 // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
932 // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2
933 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2
934 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3
935 // CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]]
936 // CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0
937 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
938 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
939 // CHECK: arraydestroy.body:
940 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
941 // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
942 // CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
943 // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
944 // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
945 // CHECK: arraydestroy.done2:
946 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
947 // CHECK-NEXT: ret i32 [[TMP7]]
948 //
949 //
950 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
951 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
952 // CHECK-NEXT: entry:
953 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
954 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
955 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
956 // CHECK-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
957 // CHECK-NEXT: ret void
958 //
959 //
960 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
961 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
962 // CHECK-NEXT: entry:
963 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
964 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
965 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
966 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
967 // CHECK-NEXT: store i32 0, ptr [[F]], align 4
968 // CHECK-NEXT: ret void
969 //
970 //
971 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
972 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
973 // CHECK-NEXT: entry:
974 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
975 // CHECK-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
976 // CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
977 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
978 // CHECK-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
979 // CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
980 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
981 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
982 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
983 // CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
984 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
985 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4
986 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
987 // CHECK-NEXT: store i32 [[ADD]], ptr [[F]], align 4
988 // CHECK-NEXT: ret void
989 //
990 //
991 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
992 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
993 // CHECK-NEXT: entry:
994 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
995 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
996 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
997 // CHECK-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
998 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
999 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1000 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1001 // CHECK-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
1002 // CHECK-NEXT: ret void
1003 //
1004 //
1005 // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1006 // CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1007 // CHECK-NEXT: entry:
1008 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1009 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1010 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1011 // CHECK-NEXT: ret void
1012 //
1013 //
1014 // LAMBDA-LABEL: define {{[^@]+}}@main
1015 // LAMBDA-SAME: () #[[ATTR0:[0-9]+]] {
1016 // LAMBDA-NEXT: entry:
1017 // LAMBDA-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1018 // LAMBDA-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1019 // LAMBDA-NEXT: store i32 0, ptr [[RETVAL]], align 4
1020 // LAMBDA-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1021 // LAMBDA-NEXT: ret i32 0
1022 //
1023 //
1024 // LAMBDA-LABEL: define {{[^@]+}}@.omp_task_privates_map.
1025 // LAMBDA-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] {
1026 // LAMBDA-NEXT: entry:
1027 // LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1028 // LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1029 // LAMBDA-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
1030 // LAMBDA-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1031 // LAMBDA-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1032 // LAMBDA-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
1033 // LAMBDA-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1034 // LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
1035 // LAMBDA-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1036 // LAMBDA-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8
1037 // LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
1038 // LAMBDA-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
1039 // LAMBDA-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
1040 // LAMBDA-NEXT: ret void
1041 //
1042 //
1043 // LAMBDA-LABEL: define {{[^@]+}}@.omp_task_entry.
1044 // LAMBDA-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
1045 // LAMBDA-NEXT: entry:
1046 // LAMBDA-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1047 // LAMBDA-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1048 // LAMBDA-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1049 // LAMBDA-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1050 // LAMBDA-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1051 // LAMBDA-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1052 // LAMBDA-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1053 // LAMBDA-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1054 // LAMBDA-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1055 // LAMBDA-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1056 // LAMBDA-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1057 // LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1058 // LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
1059 // LAMBDA-NEXT: [[I_I:%.*]] = alloca i32, align 4
1060 // LAMBDA-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1061 // LAMBDA-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
1062 // LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1063 // LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1064 // LAMBDA-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1065 // LAMBDA-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1066 // LAMBDA-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1067 // LAMBDA-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1068 // LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1069 // LAMBDA-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1070 // LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1071 // LAMBDA-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1072 // LAMBDA-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1073 // LAMBDA-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1074 // LAMBDA-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
1075 // LAMBDA-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1076 // LAMBDA-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
1077 // LAMBDA-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1078 // LAMBDA-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
1079 // LAMBDA-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1080 // LAMBDA-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
1081 // LAMBDA-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1082 // LAMBDA-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1083 // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1084 // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1085 // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1086 // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1087 // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1088 // LAMBDA-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1089 // LAMBDA-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1090 // LAMBDA-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1091 // LAMBDA-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1092 // LAMBDA-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1093 // LAMBDA-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1094 // LAMBDA-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1095 // LAMBDA-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1096 // LAMBDA-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1097 // LAMBDA-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1098 // LAMBDA-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1099 // LAMBDA-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1100 // LAMBDA-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1101 // LAMBDA-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1102 // LAMBDA-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]
1103 // LAMBDA-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
1104 // LAMBDA-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
1105 // LAMBDA-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1106 // LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32
1107 // LAMBDA-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1108 // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
1109 // LAMBDA: omp.inner.for.cond.i:
1110 // LAMBDA-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
1111 // LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64
1112 // LAMBDA-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1113 // LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]]
1114 // LAMBDA-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1115 // LAMBDA: omp.inner.for.body.i:
1116 // LAMBDA-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1117 // LAMBDA-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1118 // LAMBDA-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]]
1119 // LAMBDA-NEXT: store i32 11, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]]
1120 // LAMBDA-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1121 // LAMBDA-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1
1122 // LAMBDA-NEXT: store ptr [[TMP23]], ptr [[TMP28]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1123 // LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]]
1124 // LAMBDA-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1125 // LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1
1126 // LAMBDA-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1127 // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
1128 // LAMBDA: .omp_outlined..exit:
1129 // LAMBDA-NEXT: ret i32 0
1130 //
1131 //
1132 // BLOCKS-LABEL: define {{[^@]+}}@main
1133 // BLOCKS-SAME: () #[[ATTR1:[0-9]+]] {
1134 // BLOCKS-NEXT: entry:
1135 // BLOCKS-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1136 // BLOCKS-NEXT: store i32 0, ptr [[RETVAL]], align 4
1137 // BLOCKS-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
1138 // BLOCKS-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)
1139 // BLOCKS-NEXT: ret i32 0
1140 //
1141 //
1142 // BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke
1143 // BLOCKS-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
1144 // BLOCKS-NEXT: entry:
1145 // BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1146 // BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1147 // BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1148 // BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1149 // BLOCKS-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)
1150 // BLOCKS-NEXT: ret void
1151 //
1152 //
1153 // BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
1154 // BLOCKS-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
1155 // BLOCKS-NEXT: entry:
1156 // BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1157 // BLOCKS-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1158 // BLOCKS-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
1159 // BLOCKS-NEXT: [[TMP:%.*]] = alloca i32, align 4
1160 // BLOCKS-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1161 // BLOCKS-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1162 // BLOCKS-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1163 // BLOCKS-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1164 // BLOCKS-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
1165 // BLOCKS-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
1166 // BLOCKS-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1167 // BLOCKS: omp_if.then:
1168 // BLOCKS-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
1169 // BLOCKS-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, ptr @.omp_task_entry.)
1170 // BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP4]], i32 0, i32 0
1171 // BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP4]], i32 0, i32 1
1172 // BLOCKS-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0
1173 // BLOCKS-NEXT: [[TMP8:%.*]] = load volatile double, ptr @g, align 8
1174 // BLOCKS-NEXT: store volatile double [[TMP8]], ptr [[TMP7]], align 8
1175 // BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1
1176 // BLOCKS-NEXT: [[TMP10:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
1177 // BLOCKS-NEXT: store i32 [[TMP10]], ptr [[TMP9]], align 8
1178 // BLOCKS-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 5
1179 // BLOCKS-NEXT: store i64 0, ptr [[TMP11]], align 8
1180 // BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 6
1181 // BLOCKS-NEXT: store i64 9, ptr [[TMP12]], align 8
1182 // BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 7
1183 // BLOCKS-NEXT: store i64 1, ptr [[TMP13]], align 8
1184 // BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP5]], i32 0, i32 9
1185 // BLOCKS-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP14]], i8 0, i64 8, i1 false)
1186 // BLOCKS-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP13]], align 8
1187 // BLOCKS-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP4]], i32 1, ptr [[TMP11]], ptr [[TMP12]], i64 [[TMP15]], i32 1, i32 0, i64 0, ptr null)
1188 // BLOCKS-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
1189 // BLOCKS-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
1190 // BLOCKS-NEXT: br label [[OMP_IF_END]]
1191 // BLOCKS: omp_if.end:
1192 // BLOCKS-NEXT: ret void
1193 //
1194 //
1195 // BLOCKS-LABEL: define {{[^@]+}}@_block_invoke
1196 // BLOCKS-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
1197 // BLOCKS-NEXT: entry:
1198 // BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1199 // BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1200 // BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1201 // BLOCKS-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1202 // BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
1203 // BLOCKS-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8
1204 // BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
1205 // BLOCKS-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8
1206 // BLOCKS-NEXT: ret void
1207 //
1208 //
1209 // BLOCKS-LABEL: define {{[^@]+}}@.omp_task_privates_map.
1210 // BLOCKS-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] {
1211 // BLOCKS-NEXT: entry:
1212 // BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1213 // BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1214 // BLOCKS-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
1215 // BLOCKS-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1216 // BLOCKS-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1217 // BLOCKS-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
1218 // BLOCKS-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1219 // BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
1220 // BLOCKS-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1221 // BLOCKS-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8
1222 // BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
1223 // BLOCKS-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
1224 // BLOCKS-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
1225 // BLOCKS-NEXT: ret void
1226 //
1227 //
1228 // BLOCKS-LABEL: define {{[^@]+}}@.omp_task_entry.
1229 // BLOCKS-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
1230 // BLOCKS-NEXT: entry:
1231 // BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1232 // BLOCKS-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1233 // BLOCKS-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1234 // BLOCKS-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1235 // BLOCKS-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1236 // BLOCKS-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1237 // BLOCKS-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1238 // BLOCKS-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1239 // BLOCKS-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1240 // BLOCKS-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1241 // BLOCKS-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1242 // BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1243 // BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
1244 // BLOCKS-NEXT: [[I_I:%.*]] = alloca i32, align 4
1245 // BLOCKS-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1246 // BLOCKS-NEXT: [[BLOCK_I:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8
1247 // BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1248 // BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1249 // BLOCKS-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1250 // BLOCKS-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1251 // BLOCKS-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1252 // BLOCKS-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1253 // BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1254 // BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1255 // BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1256 // BLOCKS-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1257 // BLOCKS-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1258 // BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1259 // BLOCKS-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
1260 // BLOCKS-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1261 // BLOCKS-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
1262 // BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1263 // BLOCKS-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
1264 // BLOCKS-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1265 // BLOCKS-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
1266 // BLOCKS-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1267 // BLOCKS-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1268 // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1269 // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1270 // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1271 // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1272 // BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1273 // BLOCKS-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1274 // BLOCKS-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1275 // BLOCKS-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1276 // BLOCKS-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1277 // BLOCKS-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1278 // BLOCKS-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1279 // BLOCKS-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1280 // BLOCKS-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1281 // BLOCKS-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1282 // BLOCKS-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1283 // BLOCKS-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1284 // BLOCKS-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1285 // BLOCKS-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1286 // BLOCKS-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1287 // BLOCKS-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]
1288 // BLOCKS-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
1289 // BLOCKS-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
1290 // BLOCKS-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1291 // BLOCKS-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32
1292 // BLOCKS-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1293 // BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
1294 // BLOCKS: omp.inner.for.cond.i:
1295 // BLOCKS-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
1296 // BLOCKS-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64
1297 // BLOCKS-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1298 // BLOCKS-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]]
1299 // BLOCKS-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1300 // BLOCKS: omp.inner.for.body.i:
1301 // BLOCKS-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1302 // BLOCKS-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1303 // BLOCKS-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]]
1304 // BLOCKS-NEXT: store i32 11, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]]
1305 // BLOCKS-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1306 // BLOCKS-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 1
1307 // BLOCKS-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1308 // BLOCKS-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 2
1309 // BLOCKS-NEXT: store i32 0, ptr [[BLOCK_RESERVED_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1310 // BLOCKS-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 3
1311 // BLOCKS-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1312 // BLOCKS-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 4
1313 // BLOCKS-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1314 // BLOCKS-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 5
1315 // BLOCKS-NEXT: [[TMP28:%.*]] = load volatile double, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]]
1316 // BLOCKS-NEXT: store volatile double [[TMP28]], ptr [[BLOCK_CAPTURED_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1317 // BLOCKS-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 6
1318 // BLOCKS-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]]
1319 // BLOCKS-NEXT: store i32 [[TMP29]], ptr [[BLOCK_CAPTURED3_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1320 // BLOCKS-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK_I]], i32 0, i32 3
1321 // BLOCKS-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1322 // BLOCKS-NEXT: call void [[TMP31]](ptr noundef [[BLOCK_I]]) #[[ATTR4]], !llvm.access.group [[ACC_GRP15]]
1323 // BLOCKS-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1324 // BLOCKS-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP32]], 1
1325 // BLOCKS-NEXT: store i32 [[ADD4_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1326 // BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
1327 // BLOCKS: .omp_outlined..exit:
1328 // BLOCKS-NEXT: ret i32 0
1329 //
1330 //
1331 // ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
1332 // ARRAY-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
1333 // ARRAY-NEXT: entry:
1334 // ARRAY-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1335 // ARRAY-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
1336 // ARRAY-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1337 // ARRAY-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1338 // ARRAY-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
1339 // ARRAY-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1340 // ARRAY-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1341 // ARRAY-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1342 // ARRAY-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1343 // ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1344 // ARRAY-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 3, ptr @_Z10array_funciPfP2St.omp_outlined, i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]])
1345 // ARRAY-NEXT: ret void
1346 //
1347 //
1348 // ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St.omp_outlined
1349 // ARRAY-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR1:[0-9]+]] {
1350 // ARRAY-NEXT: entry:
1351 // ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1352 // ARRAY-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1353 // ARRAY-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1354 // ARRAY-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
1355 // ARRAY-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1356 // ARRAY-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
1357 // ARRAY-NEXT: [[TMP:%.*]] = alloca i32, align 4
1358 // ARRAY-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1359 // ARRAY-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1360 // ARRAY-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1361 // ARRAY-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
1362 // ARRAY-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1363 // ARRAY-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1364 // ARRAY-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1365 // ARRAY-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1366 // ARRAY-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP2]])
1367 // ARRAY-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
1368 // ARRAY-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1369 // ARRAY: omp_if.then:
1370 // ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
1371 // ARRAY-NEXT: store i64 [[TMP0]], ptr [[TMP5]], align 8
1372 // ARRAY-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP2]])
1373 // ARRAY-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i64 96, i64 8, ptr @.omp_task_entry.)
1374 // ARRAY-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP6]], i32 0, i32 0
1375 // ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0
1376 // ARRAY-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
1377 // ARRAY-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false)
1378 // ARRAY-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP6]], i32 0, i32 1
1379 // ARRAY-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP10]], i32 0, i32 0
1380 // ARRAY-NEXT: [[TMP12:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1381 // ARRAY-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
1382 // ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP10]], i32 0, i32 1
1383 // ARRAY-NEXT: [[TMP14:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1384 // ARRAY-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
1385 // ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 5
1386 // ARRAY-NEXT: store i64 0, ptr [[TMP15]], align 8
1387 // ARRAY-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 6
1388 // ARRAY-NEXT: store i64 9, ptr [[TMP16]], align 8
1389 // ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 7
1390 // ARRAY-NEXT: store i64 1, ptr [[TMP17]], align 8
1391 // ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 9
1392 // ARRAY-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP18]], i8 0, i64 8, i1 false)
1393 // ARRAY-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP17]], align 8
1394 // ARRAY-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP2]], ptr [[TMP6]], i32 1, ptr [[TMP15]], ptr [[TMP16]], i64 [[TMP19]], i32 1, i32 0, i64 0, ptr null)
1395 // ARRAY-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP2]])
1396 // ARRAY-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP2]])
1397 // ARRAY-NEXT: br label [[OMP_IF_END]]
1398 // ARRAY: omp_if.end:
1399 // ARRAY-NEXT: ret void
1400 //
1401 //
1402 // ARRAY-LABEL: define {{[^@]+}}@.omp_task_privates_map.
1403 // ARRAY-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] {
1404 // ARRAY-NEXT: entry:
1405 // ARRAY-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1406 // ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1407 // ARRAY-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
1408 // ARRAY-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1409 // ARRAY-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1410 // ARRAY-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
1411 // ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1412 // ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
1413 // ARRAY-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1414 // ARRAY-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8
1415 // ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
1416 // ARRAY-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
1417 // ARRAY-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
1418 // ARRAY-NEXT: ret void
1419 //
1420 //
1421 // ARRAY-LABEL: define {{[^@]+}}@.omp_task_entry.
1422 // ARRAY-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
1423 // ARRAY-NEXT: entry:
1424 // ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1425 // ARRAY-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1426 // ARRAY-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1427 // ARRAY-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1428 // ARRAY-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1429 // ARRAY-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1430 // ARRAY-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1431 // ARRAY-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1432 // ARRAY-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1433 // ARRAY-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1434 // ARRAY-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1435 // ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1436 // ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
1437 // ARRAY-NEXT: [[I_I:%.*]] = alloca i32, align 4
1438 // ARRAY-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1439 // ARRAY-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1440 // ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1441 // ARRAY-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1442 // ARRAY-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1443 // ARRAY-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1444 // ARRAY-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1445 // ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1446 // ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1447 // ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1448 // ARRAY-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1449 // ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1450 // ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1451 // ARRAY-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
1452 // ARRAY-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1453 // ARRAY-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
1454 // ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1455 // ARRAY-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
1456 // ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1457 // ARRAY-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
1458 // ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1459 // ARRAY-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1460 // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1461 // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1462 // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1463 // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1464 // ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1465 // ARRAY-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1466 // ARRAY-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1467 // ARRAY-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1468 // ARRAY-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1469 // ARRAY-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1470 // ARRAY-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1471 // ARRAY-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1472 // ARRAY-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1473 // ARRAY-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1474 // ARRAY-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1475 // ARRAY-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1476 // ARRAY-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1477 // ARRAY-NEXT: [[TMP20:%.*]] = load i64, ptr [[TMP19]], align 8
1478 // ARRAY-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1479 // ARRAY-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1480 // ARRAY-NEXT: call void [[TMP21]](ptr [[TMP22]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]
1481 // ARRAY-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
1482 // ARRAY-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
1483 // ARRAY-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1484 // ARRAY-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP25]] to i32
1485 // ARRAY-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1486 // ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
1487 // ARRAY: omp.inner.for.cond.i:
1488 // ARRAY-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
1489 // ARRAY-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP26]] to i64
1490 // ARRAY-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1491 // ARRAY-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP27]]
1492 // ARRAY-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1493 // ARRAY: omp.inner.for.body.i:
1494 // ARRAY-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1495 // ARRAY-NEXT: store i32 [[TMP28]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1496 // ARRAY-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1497 // ARRAY-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1
1498 // ARRAY-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1499 // ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
1500 // ARRAY: .omp_outlined..exit:
1501 // ARRAY-NEXT: ret i32 0
1502 //
1503 //
1504 // SIMD-ONLY0-LABEL: define {{[^@]+}}@main
1505 // SIMD-ONLY0-SAME: () #[[ATTR0:[0-9]+]] {
1506 // SIMD-ONLY0-NEXT: entry:
1507 // SIMD-ONLY0-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1508 // SIMD-ONLY0-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1509 // SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
1510 // SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1511 // SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1512 // SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
1513 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
1514 // SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca i32, align 4
1515 // SIMD-ONLY0-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1516 // SIMD-ONLY0-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1517 // SIMD-ONLY0-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1518 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4
1519 // SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4
1520 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]])
1521 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
1522 // SIMD-ONLY0-NEXT: store i32 0, ptr [[T_VAR]], align 4
1523 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
1524 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[S_ARR]], double noundef 1.000000e+00)
1525 // SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
1526 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
1527 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
1528 // SIMD-ONLY0-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1529 // SIMD-ONLY0-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
1530 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1531 // SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1532 // SIMD-ONLY0-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
1533 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1534 // SIMD-ONLY0: omp.inner.for.cond:
1535 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1536 // SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
1537 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
1538 // SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]]
1539 // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1540 // SIMD-ONLY0: omp.inner.for.body:
1541 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1542 // SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1543 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1544 // SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1545 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1546 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0
1547 // SIMD-ONLY0-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
1548 // SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
1549 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX2]], ptr align 8 [[VAR]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]]
1550 // SIMD-ONLY0-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
1551 // SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1552 // SIMD-ONLY0: omp.body.continue:
1553 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1554 // SIMD-ONLY0: omp.inner.for.inc:
1555 // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1556 // SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
1557 // SIMD-ONLY0-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1558 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1559 // SIMD-ONLY0: omp.inner.for.end:
1560 // SIMD-ONLY0-NEXT: store i32 10, ptr [[I]], align 4
1561 // SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1562 // SIMD-ONLY0-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
1563 // SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]]
1564 // SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1565 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1566 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1567 // SIMD-ONLY0: arraydestroy.body:
1568 // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1569 // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1570 // SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1571 // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1572 // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
1573 // SIMD-ONLY0: arraydestroy.done4:
1574 // SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]]
1575 // SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]]
1576 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
1577 // SIMD-ONLY0-NEXT: ret i32 [[TMP7]]
1578 //
1579 //
1580 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
1581 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
1582 // SIMD-ONLY0-NEXT: entry:
1583 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1584 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1585 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1586 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]])
1587 // SIMD-ONLY0-NEXT: ret void
1588 //
1589 //
1590 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
1591 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1592 // SIMD-ONLY0-NEXT: entry:
1593 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1594 // SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1595 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
1596 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1597 // SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1598 // SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8
1599 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1600 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1601 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8
1602 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
1603 // SIMD-ONLY0-NEXT: ret void
1604 //
1605 //
1606 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
1607 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1608 // SIMD-ONLY0-NEXT: entry:
1609 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1610 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
1611 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1612 // SIMD-ONLY0-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
1613 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1614 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
1615 // SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
1616 // SIMD-ONLY0-NEXT: ret void
1617 //
1618 //
1619 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1620 // SIMD-ONLY0-SAME: () #[[ATTR1]] {
1621 // SIMD-ONLY0-NEXT: entry:
1622 // SIMD-ONLY0-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1623 // SIMD-ONLY0-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1624 // SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
1625 // SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
1626 // SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1627 // SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1628 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
1629 // SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca i32, align 4
1630 // SIMD-ONLY0-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1631 // SIMD-ONLY0-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1632 // SIMD-ONLY0-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1633 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4
1634 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]])
1635 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
1636 // SIMD-ONLY0-NEXT: store i32 0, ptr [[T_VAR]], align 128
1637 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1638 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
1639 // SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
1640 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1641 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
1642 // SIMD-ONLY0-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1643 // SIMD-ONLY0-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
1644 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1645 // SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1646 // SIMD-ONLY0-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
1647 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1648 // SIMD-ONLY0: omp.inner.for.cond:
1649 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1650 // SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
1651 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]
1652 // SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]]
1653 // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1654 // SIMD-ONLY0: omp.inner.for.body:
1655 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1656 // SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1657 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1658 // SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1659 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]]
1660 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0
1661 // SIMD-ONLY0-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
1662 // SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
1663 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
1664 // SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1665 // SIMD-ONLY0: omp.body.continue:
1666 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1667 // SIMD-ONLY0: omp.inner.for.inc:
1668 // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1669 // SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
1670 // SIMD-ONLY0-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1671 // SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1672 // SIMD-ONLY0: omp.inner.for.end:
1673 // SIMD-ONLY0-NEXT: store i32 10, ptr [[I]], align 4
1674 // SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4
1675 // SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]]
1676 // SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1677 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1678 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1679 // SIMD-ONLY0: arraydestroy.body:
1680 // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1681 // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1682 // SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1683 // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1684 // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
1685 // SIMD-ONLY0: arraydestroy.done4:
1686 // SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
1687 // SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]]
1688 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
1689 // SIMD-ONLY0-NEXT: ret i32 [[TMP7]]
1690 //
1691 //
1692 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
1693 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1694 // SIMD-ONLY0-NEXT: entry:
1695 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1696 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1697 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1698 // SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
1699 // SIMD-ONLY0-NEXT: ret void
1700 //
1701 //
1702 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
1703 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1704 // SIMD-ONLY0-NEXT: entry:
1705 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1706 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1707 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1708 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1709 // SIMD-ONLY0-NEXT: store double 0.000000e+00, ptr [[F]], align 8
1710 // SIMD-ONLY0-NEXT: ret void
1711 //
1712 //
1713 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
1714 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1715 // SIMD-ONLY0-NEXT: entry:
1716 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1717 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1718 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1719 // SIMD-ONLY0-NEXT: ret void
1720 //
1721 //
1722 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
1723 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1724 // SIMD-ONLY0-NEXT: entry:
1725 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1726 // SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1727 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
1728 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1729 // SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1730 // SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8
1731 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1732 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1733 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1734 // SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
1735 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8
1736 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8
1737 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
1738 // SIMD-ONLY0-NEXT: store double [[ADD]], ptr [[F]], align 8
1739 // SIMD-ONLY0-NEXT: ret void
1740 //
1741 //
1742 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
1743 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1744 // SIMD-ONLY0-NEXT: entry:
1745 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1746 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
1747 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1748 // SIMD-ONLY0-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
1749 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1750 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1751 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
1752 // SIMD-ONLY0-NEXT: store double [[TMP0]], ptr [[F]], align 8
1753 // SIMD-ONLY0-NEXT: ret void
1754 //
1755 //
1756 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1757 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1758 // SIMD-ONLY0-NEXT: entry:
1759 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1760 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1761 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1762 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1763 // SIMD-ONLY0-NEXT: ret void
1764 //
1765 //
1766 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
1767 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1768 // SIMD-ONLY0-NEXT: entry:
1769 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1770 // SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1771 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
1772 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1773 // SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1774 // SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
1775 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1776 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1777 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4
1778 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
1779 // SIMD-ONLY0-NEXT: ret void
1780 //
1781 //
1782 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1783 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1784 // SIMD-ONLY0-NEXT: entry:
1785 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1786 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1787 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1788 // SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
1789 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1790 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1791 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1792 // SIMD-ONLY0-NEXT: ret void
1793 //
1794 //
1795 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1796 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1797 // SIMD-ONLY0-NEXT: entry:
1798 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1799 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1800 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1801 // SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
1802 // SIMD-ONLY0-NEXT: ret void
1803 //
1804 //
1805 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1806 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1807 // SIMD-ONLY0-NEXT: entry:
1808 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1809 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1810 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1811 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1812 // SIMD-ONLY0-NEXT: store i32 0, ptr [[F]], align 4
1813 // SIMD-ONLY0-NEXT: ret void
1814 //
1815 //
1816 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
1817 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1818 // SIMD-ONLY0-NEXT: entry:
1819 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1820 // SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1821 // SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
1822 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1823 // SIMD-ONLY0-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1824 // SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
1825 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1826 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1827 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1828 // SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
1829 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
1830 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4
1831 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1832 // SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[F]], align 4
1833 // SIMD-ONLY0-NEXT: ret void
1834 //
1835 //
1836 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1837 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1838 // SIMD-ONLY0-NEXT: entry:
1839 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1840 // SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1841 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1842 // SIMD-ONLY0-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
1843 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1844 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1845 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1846 // SIMD-ONLY0-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
1847 // SIMD-ONLY0-NEXT: ret void
1848 //
1849 //
1850 // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1851 // SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1852 // SIMD-ONLY0-NEXT: entry:
1853 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1854 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1855 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1856 // SIMD-ONLY0-NEXT: ret void
1857 //
1858 //
1859 // SIMD-ONLY1-LABEL: define {{[^@]+}}@main
1860 // SIMD-ONLY1-SAME: () #[[ATTR0:[0-9]+]] {
1861 // SIMD-ONLY1-NEXT: entry:
1862 // SIMD-ONLY1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1863 // SIMD-ONLY1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1864 // SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
1865 // SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1866 // SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1867 // SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
1868 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
1869 // SIMD-ONLY1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1870 // SIMD-ONLY1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1871 // SIMD-ONLY1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1872 // SIMD-ONLY1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1873 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4
1874 // SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4
1875 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]])
1876 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]], ptr noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
1877 // SIMD-ONLY1-NEXT: store i32 0, ptr [[T_VAR]], align 4
1878 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
1879 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[S_ARR]], double noundef 1.000000e+00)
1880 // SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
1881 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
1882 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
1883 // SIMD-ONLY1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1884 // SIMD-ONLY1-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
1885 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1886 // SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1887 // SIMD-ONLY1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
1888 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1889 // SIMD-ONLY1: omp.inner.for.cond:
1890 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1891 // SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
1892 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
1893 // SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]]
1894 // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1895 // SIMD-ONLY1: omp.inner.for.body:
1896 // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1897 // SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1898 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1899 // SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1900 // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1901 // SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0
1902 // SIMD-ONLY1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
1903 // SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
1904 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX2]], ptr align 8 [[VAR]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]]
1905 // SIMD-ONLY1-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
1906 // SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1907 // SIMD-ONLY1: omp.body.continue:
1908 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1909 // SIMD-ONLY1: omp.inner.for.inc:
1910 // SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1911 // SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
1912 // SIMD-ONLY1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1913 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1914 // SIMD-ONLY1: omp.inner.for.end:
1915 // SIMD-ONLY1-NEXT: store i32 10, ptr [[I]], align 4
1916 // SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1917 // SIMD-ONLY1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
1918 // SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]]
1919 // SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1920 // SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1921 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1922 // SIMD-ONLY1: arraydestroy.body:
1923 // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1924 // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1925 // SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1926 // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1927 // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
1928 // SIMD-ONLY1: arraydestroy.done4:
1929 // SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]]
1930 // SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]]
1931 // SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
1932 // SIMD-ONLY1-NEXT: ret i32 [[TMP7]]
1933 //
1934 //
1935 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
1936 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
1937 // SIMD-ONLY1-NEXT: entry:
1938 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1939 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1940 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1941 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]])
1942 // SIMD-ONLY1-NEXT: ret void
1943 //
1944 //
1945 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
1946 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1947 // SIMD-ONLY1-NEXT: entry:
1948 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1949 // SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1950 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
1951 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1952 // SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1953 // SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8
1954 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1955 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1956 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[T_ADDR]], align 8
1957 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
1958 // SIMD-ONLY1-NEXT: ret void
1959 //
1960 //
1961 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
1962 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1963 // SIMD-ONLY1-NEXT: entry:
1964 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1965 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
1966 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1967 // SIMD-ONLY1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
1968 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1969 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
1970 // SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
1971 // SIMD-ONLY1-NEXT: ret void
1972 //
1973 //
1974 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1975 // SIMD-ONLY1-SAME: () #[[ATTR1]] {
1976 // SIMD-ONLY1-NEXT: entry:
1977 // SIMD-ONLY1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1978 // SIMD-ONLY1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1979 // SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
1980 // SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
1981 // SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1982 // SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1983 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
1984 // SIMD-ONLY1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1985 // SIMD-ONLY1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1986 // SIMD-ONLY1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1987 // SIMD-ONLY1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1988 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4
1989 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]])
1990 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
1991 // SIMD-ONLY1-NEXT: store i32 0, ptr [[T_VAR]], align 128
1992 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1993 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
1994 // SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
1995 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1996 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
1997 // SIMD-ONLY1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1998 // SIMD-ONLY1-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
1999 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2000 // SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2001 // SIMD-ONLY1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2002 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2003 // SIMD-ONLY1: omp.inner.for.cond:
2004 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
2005 // SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
2006 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]
2007 // SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]]
2008 // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2009 // SIMD-ONLY1: omp.inner.for.body:
2010 // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2011 // SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2012 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2013 // SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2014 // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]]
2015 // SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0
2016 // SIMD-ONLY1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
2017 // SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
2018 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
2019 // SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2020 // SIMD-ONLY1: omp.body.continue:
2021 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2022 // SIMD-ONLY1: omp.inner.for.inc:
2023 // SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2024 // SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1
2025 // SIMD-ONLY1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2026 // SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2027 // SIMD-ONLY1: omp.inner.for.end:
2028 // SIMD-ONLY1-NEXT: store i32 10, ptr [[I]], align 4
2029 // SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4
2030 // SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]]
2031 // SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2032 // SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
2033 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2034 // SIMD-ONLY1: arraydestroy.body:
2035 // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2036 // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2037 // SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
2038 // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2039 // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
2040 // SIMD-ONLY1: arraydestroy.done4:
2041 // SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
2042 // SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]]
2043 // SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
2044 // SIMD-ONLY1-NEXT: ret i32 [[TMP7]]
2045 //
2046 //
2047 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
2048 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2049 // SIMD-ONLY1-NEXT: entry:
2050 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2051 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2052 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2053 // SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
2054 // SIMD-ONLY1-NEXT: ret void
2055 //
2056 //
2057 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
2058 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2059 // SIMD-ONLY1-NEXT: entry:
2060 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2061 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2062 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2063 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2064 // SIMD-ONLY1-NEXT: store double 0.000000e+00, ptr [[F]], align 8
2065 // SIMD-ONLY1-NEXT: ret void
2066 //
2067 //
2068 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
2069 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2070 // SIMD-ONLY1-NEXT: entry:
2071 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2072 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2073 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2074 // SIMD-ONLY1-NEXT: ret void
2075 //
2076 //
2077 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
2078 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2079 // SIMD-ONLY1-NEXT: entry:
2080 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2081 // SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
2082 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
2083 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2084 // SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
2085 // SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8
2086 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2087 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2088 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2089 // SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
2090 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8
2091 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8
2092 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
2093 // SIMD-ONLY1-NEXT: store double [[ADD]], ptr [[F]], align 8
2094 // SIMD-ONLY1-NEXT: ret void
2095 //
2096 //
2097 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
2098 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2099 // SIMD-ONLY1-NEXT: entry:
2100 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2101 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
2102 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2103 // SIMD-ONLY1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
2104 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2105 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2106 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
2107 // SIMD-ONLY1-NEXT: store double [[TMP0]], ptr [[F]], align 8
2108 // SIMD-ONLY1-NEXT: ret void
2109 //
2110 //
2111 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2112 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2113 // SIMD-ONLY1-NEXT: entry:
2114 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2115 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2116 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2117 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2118 // SIMD-ONLY1-NEXT: ret void
2119 //
2120 //
2121 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
2122 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2123 // SIMD-ONLY1-NEXT: entry:
2124 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2125 // SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
2126 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
2127 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2128 // SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
2129 // SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
2130 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2131 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2132 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_ADDR]], align 4
2133 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
2134 // SIMD-ONLY1-NEXT: ret void
2135 //
2136 //
2137 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2138 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2139 // SIMD-ONLY1-NEXT: entry:
2140 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2141 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2142 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2143 // SIMD-ONLY1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2144 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2145 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2146 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2147 // SIMD-ONLY1-NEXT: ret void
2148 //
2149 //
2150 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2151 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2152 // SIMD-ONLY1-NEXT: entry:
2153 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2154 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2155 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2156 // SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
2157 // SIMD-ONLY1-NEXT: ret void
2158 //
2159 //
2160 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2161 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2162 // SIMD-ONLY1-NEXT: entry:
2163 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2164 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2165 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2166 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2167 // SIMD-ONLY1-NEXT: store i32 0, ptr [[F]], align 4
2168 // SIMD-ONLY1-NEXT: ret void
2169 //
2170 //
2171 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
2172 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2173 // SIMD-ONLY1-NEXT: entry:
2174 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2175 // SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
2176 // SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
2177 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2178 // SIMD-ONLY1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
2179 // SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4
2180 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2181 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2182 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
2183 // SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
2184 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
2185 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4
2186 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2187 // SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[F]], align 4
2188 // SIMD-ONLY1-NEXT: ret void
2189 //
2190 //
2191 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2192 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2193 // SIMD-ONLY1-NEXT: entry:
2194 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2195 // SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2196 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2197 // SIMD-ONLY1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2198 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2199 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2200 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2201 // SIMD-ONLY1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
2202 // SIMD-ONLY1-NEXT: ret void
2203 //
2204 //
2205 // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2206 // SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2207 // SIMD-ONLY1-NEXT: entry:
2208 // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2209 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2210 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2211 // SIMD-ONLY1-NEXT: ret void
2212 //
2213 //
2214 // SIMD-ONLY2-LABEL: define {{[^@]+}}@main
2215 // SIMD-ONLY2-SAME: () #[[ATTR0:[0-9]+]] {
2216 // SIMD-ONLY2-NEXT: entry:
2217 // SIMD-ONLY2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2218 // SIMD-ONLY2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2219 // SIMD-ONLY2-NEXT: store i32 0, ptr [[RETVAL]], align 4
2220 // SIMD-ONLY2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2221 // SIMD-ONLY2-NEXT: ret i32 0
2222 //
2223 //
2224 // SIMD-ONLY3-LABEL: define {{[^@]+}}@main
2225 // SIMD-ONLY3-SAME: () #[[ATTR1:[0-9]+]] {
2226 // SIMD-ONLY3-NEXT: entry:
2227 // SIMD-ONLY3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2228 // SIMD-ONLY3-NEXT: store i32 0, ptr [[RETVAL]], align 4
2229 // SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
2230 // SIMD-ONLY3-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)
2231 // SIMD-ONLY3-NEXT: ret i32 0
2232 //
2233 //
2234 // SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke
2235 // SIMD-ONLY3-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
2236 // SIMD-ONLY3-NEXT: entry:
2237 // SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
2238 // SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
2239 // SIMD-ONLY3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2240 // SIMD-ONLY3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2241 // SIMD-ONLY3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2242 // SIMD-ONLY3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2243 // SIMD-ONLY3-NEXT: [[I:%.*]] = alloca i32, align 4
2244 // SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8
2245 // SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2246 // SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
2247 // SIMD-ONLY3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
2248 // SIMD-ONLY3-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
2249 // SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2250 // SIMD-ONLY3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2251 // SIMD-ONLY3-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2252 // SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2253 // SIMD-ONLY3: omp.inner.for.cond:
2254 // SIMD-ONLY3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
2255 // SIMD-ONLY3-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
2256 // SIMD-ONLY3-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
2257 // SIMD-ONLY3-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]]
2258 // SIMD-ONLY3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2259 // SIMD-ONLY3: omp.inner.for.body:
2260 // SIMD-ONLY3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2261 // SIMD-ONLY3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2262 // SIMD-ONLY3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2263 // SIMD-ONLY3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2264 // SIMD-ONLY3-NEXT: store double 1.000000e+00, ptr @g, align 8, !llvm.access.group [[ACC_GRP2]]
2265 // SIMD-ONLY3-NEXT: store i32 11, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
2266 // SIMD-ONLY3-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 0
2267 // SIMD-ONLY3-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8, !llvm.access.group [[ACC_GRP2]]
2268 // SIMD-ONLY3-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 1
2269 // SIMD-ONLY3-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8, !llvm.access.group [[ACC_GRP2]]
2270 // SIMD-ONLY3-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 2
2271 // SIMD-ONLY3-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !llvm.access.group [[ACC_GRP2]]
2272 // SIMD-ONLY3-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 3
2273 // SIMD-ONLY3-NEXT: store ptr @__main_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8, !llvm.access.group [[ACC_GRP2]]
2274 // SIMD-ONLY3-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 4
2275 // SIMD-ONLY3-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8, !llvm.access.group [[ACC_GRP2]]
2276 // SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 5
2277 // SIMD-ONLY3-NEXT: [[TMP4:%.*]] = load volatile double, ptr @g, align 8, !llvm.access.group [[ACC_GRP2]]
2278 // SIMD-ONLY3-NEXT: store volatile double [[TMP4]], ptr [[BLOCK_CAPTURED]], align 8, !llvm.access.group [[ACC_GRP2]]
2279 // SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 6
2280 // SIMD-ONLY3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
2281 // SIMD-ONLY3-NEXT: store i32 [[TMP5]], ptr [[BLOCK_CAPTURED2]], align 8, !llvm.access.group [[ACC_GRP2]]
2282 // SIMD-ONLY3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
2283 // SIMD-ONLY3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !llvm.access.group [[ACC_GRP2]]
2284 // SIMD-ONLY3-NEXT: call void [[TMP7]](ptr noundef [[BLOCK]]), !llvm.access.group [[ACC_GRP2]]
2285 // SIMD-ONLY3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2286 // SIMD-ONLY3: omp.body.continue:
2287 // SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2288 // SIMD-ONLY3: omp.inner.for.inc:
2289 // SIMD-ONLY3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2290 // SIMD-ONLY3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2291 // SIMD-ONLY3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2292 // SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2293 // SIMD-ONLY3: omp.inner.for.end:
2294 // SIMD-ONLY3-NEXT: store i32 10, ptr [[I]], align 4
2295 // SIMD-ONLY3-NEXT: ret void
2296 //
2297 //
2298 // SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke_2
2299 // SIMD-ONLY3-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
2300 // SIMD-ONLY3-NEXT: entry:
2301 // SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
2302 // SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
2303 // SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2304 // SIMD-ONLY3-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
2305 // SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
2306 // SIMD-ONLY3-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8
2307 // SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
2308 // SIMD-ONLY3-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8
2309 // SIMD-ONLY3-NEXT: ret void
2310 //
2311 //
2312 // SIMD-ONLY4-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
2313 // SIMD-ONLY4-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
2314 // SIMD-ONLY4-NEXT: entry:
2315 // SIMD-ONLY4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2316 // SIMD-ONLY4-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
2317 // SIMD-ONLY4-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
2318 // SIMD-ONLY4-NEXT: [[TMP:%.*]] = alloca i32, align 4
2319 // SIMD-ONLY4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2320 // SIMD-ONLY4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2321 // SIMD-ONLY4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2322 // SIMD-ONLY4-NEXT: [[I:%.*]] = alloca i32, align 4
2323 // SIMD-ONLY4-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
2324 // SIMD-ONLY4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
2325 // SIMD-ONLY4-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
2326 // SIMD-ONLY4-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2327 // SIMD-ONLY4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2328 // SIMD-ONLY4-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
2329 // SIMD-ONLY4-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
2330 // SIMD-ONLY4-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2331 // SIMD-ONLY4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32
2332 // SIMD-ONLY4-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2333 // SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2334 // SIMD-ONLY4: omp.inner.for.cond:
2335 // SIMD-ONLY4-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
2336 // SIMD-ONLY4-NEXT: [[CONV1:%.*]] = sext i32 [[TMP3]] to i64
2337 // SIMD-ONLY4-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
2338 // SIMD-ONLY4-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP4]]
2339 // SIMD-ONLY4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2340 // SIMD-ONLY4: omp.inner.for.body:
2341 // SIMD-ONLY4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2342 // SIMD-ONLY4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
2343 // SIMD-ONLY4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2344 // SIMD-ONLY4-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2345 // SIMD-ONLY4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2346 // SIMD-ONLY4: omp.body.continue:
2347 // SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2348 // SIMD-ONLY4: omp.inner.for.inc:
2349 // SIMD-ONLY4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2350 // SIMD-ONLY4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
2351 // SIMD-ONLY4-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2352 // SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2353 // SIMD-ONLY4: omp.inner.for.end:
2354 // SIMD-ONLY4-NEXT: store i32 10, ptr [[I]], align 4
2355 // SIMD-ONLY4-NEXT: ret void
2356 //
LLVM monorepo