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[clang] Implement lifetime analysis for lifetime_capture_by(X) (#115921)
[llvm-project.git] / clang / test / OpenMP / parallel_master_taskloop_simd_lastprivate_codegen.cpp
blobb5d2053e54cc2d7fd5995e72bff17a3584717fef
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
7 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
8 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6
9
10 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
14 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10
15 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
16 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -DLOOP -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12
17 // expected-no-diagnostics
18
19 #if !defined(ARRAY) && !defined(LOOP)
20 #ifndef HEADER
21 #define HEADER
22
23 template <class T>
24 struct S {
25 T f;
26 S(T a) : f(a) {}
27 S() : f() {}
28 S(const S &s, T t = T()) : f(s.f + t) {}
29 operator T() { return T(); }
30 ~S() {}
31 };
32
33 volatile double g;
34
35 template <typename T>
36 T tmain() {
37 S<T> ttt;
38 S<T> test;
39 T t_var __attribute__((aligned(128))) = T();
40 T vec[] = {1, 2};
41 S<T> s_arr[] = {1, 2};
42 S<T> var(3);
43 #pragma omp parallel master taskloop simd lastprivate(t_var, vec, s_arr, s_arr, var, var)
44 for (int i = 0; i < 10; ++i) {
45 vec[0] = t_var;
46 s_arr[0] = var;
47 }
48 return T();
49 }
50
51 int main() {
52 static int sivar;
53 #ifdef LAMBDA
54 [&]() {
55
56 #pragma omp parallel master taskloop simd lastprivate(g, sivar)
57 for (int i = 0; i < 10; ++i) {
58
59 g = 1;
60 sivar = 11;
61 [&]() {
62 g = 2;
63 sivar = 22;
64 }();
65 }
66 }();
67 return 0;
68 #elif defined(BLOCKS)
69 ^{
70 #pragma omp parallel master taskloop simd lastprivate(g, sivar)
71 for (int i = 0; i < 10; ++i) {
72
73 g = 1;
74 sivar = 11;
75 ^{
76 g = 2;
77 sivar = 22;
78 }();
79 }
80 }();
81 return 0;
82 #else
83 S<double> ttt;
84 S<double> test;
85 int t_var = 0;
86 int vec[] = {1, 2};
87 S<double> s_arr[] = {1, 2};
88 S<double> var(3);
89 #pragma omp parallel master taskloop simd lastprivate(var, t_var, s_arr, vec, s_arr, var, sivar)
90 for (int i = 0; i < 10; ++i) {
91 vec[0] = t_var;
92 s_arr[0] = var;
93 sivar = 33;
94 }
95 return tmain<int>();
96 #endif
97 }
98
99
100
101 // Store original variables in capture struct.
102
103 // Allocate task.
104 // Returns struct kmp_task_t {
105 // [[KMP_TASK_T]] task_data;
106 // [[KMP_TASK_MAIN_TY]] privates;
107 // };
108
109 // Fill kmp_task_t->shareds by copying from original capture argument.
110
111 // Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
112 // Also copy address of private copy to the corresponding shareds reference.
113
114 // Constructors for s_arr and var.
115 // s_arr;
116
117 // var;
118
119 // t_var;
120 // vec;
121 // sivar;
122
123 // Provide pointer to destructor function, which will destroy private variables at the end of the task.
124
125 // Start task.
126
127
128
129
130
131
132 // Privates actually are used.
133
134
135
136
137
138
139
140
141 // Store original variables in capture struct.
142
143 // Allocate task.
144 // Returns struct kmp_task_t {
145 // [[KMP_TASK_T_TY]] task_data;
146 // [[KMP_TASK_TMAIN_TY]] privates;
147 // };
148
149 // Fill kmp_task_t->shareds by copying from original capture argument.
150
151 // Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
152
153 // t_var;
154 // vec;
155
156 // Constructors for s_arr and var.
157 // a_arr;
158
159 // var;
160
161 // Provide pointer to destructor function, which will destroy private variables at the end of the task.
162
163 // Start task.
164
165 // No destructors must be called for private copies of s_arr and var.
166
167
168
169 // Privates actually are used.
170
171
172
173
174
175
176 #endif
177 #elif defined(ARRAY)
178 struct St {
179 int a, b;
180 St() : a(0), b(0) {}
181 St(const St &) {}
182 ~St() {}
183 };
184
185 void array_func(int n, float a[n], St s[2]) {
186 #pragma omp parallel master taskloop simd lastprivate(a, s)
187 for (int i = 0; i < 10; ++i)
188 ;
189 }
190 #else
191
192 void loop() {
193 int i, j;
194 #pragma omp parallel master taskloop simd linear(i, j)
195 for (i = 0; i < 10; ++i)
196 ++j;
197 }
198 #endif
199
200 // CHECK1-LABEL: define {{[^@]+}}@main
201 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
202 // CHECK1-NEXT: entry:
203 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
204 // CHECK1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
205 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
206 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
207 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
208 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
209 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
210 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
211 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]])
212 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]])
213 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4
214 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
215 // CHECK1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[S_ARR]], double noundef 1.000000e+00)
216 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
217 // CHECK1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
218 // CHECK1-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
219 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]])
220 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
221 // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
222 // CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
223 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
224 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
225 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
226 // CHECK1: arraydestroy.body:
227 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
228 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
229 // CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
230 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
231 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
232 // CHECK1: arraydestroy.done1:
233 // CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
234 // CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
235 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
236 // CHECK1-NEXT: ret i32 [[TMP1]]
237 //
238 //
239 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
240 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
241 // CHECK1-NEXT: entry:
242 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
243 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
244 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
245 // CHECK1-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]])
246 // CHECK1-NEXT: ret void
247 //
248 //
249 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
250 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
251 // CHECK1-NEXT: entry:
252 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
253 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
254 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
255 // CHECK1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
256 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
257 // CHECK1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
258 // CHECK1-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
259 // CHECK1-NEXT: ret void
260 //
261 //
262 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined
263 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] {
264 // CHECK1-NEXT: entry:
265 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
266 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
267 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
268 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
269 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
270 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
271 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
272 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
273 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
274 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
275 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
276 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
277 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
278 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
279 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
280 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
281 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
282 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
283 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
284 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
285 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP5]])
286 // CHECK1-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP6]], 0
287 // CHECK1-NEXT: br i1 [[TMP7]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
288 // CHECK1: omp_if.then:
289 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
290 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP8]], align 8
291 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
292 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP9]], align 8
293 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
294 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8
295 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 3
296 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP11]], align 8
297 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 4
298 // CHECK1-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP12]], align 8
299 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP5]])
300 // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP5]], i32 9, i64 120, i64 40, ptr @.omp_task_entry.)
301 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP13]], i32 0, i32 0
302 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP14]], i32 0, i32 0
303 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
304 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 40, i1 false)
305 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP13]], i32 0, i32 1
306 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP17]], i32 0, i32 0
307 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP18]], i32 0, i32 0
308 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
309 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
310 // CHECK1: arrayctor.loop:
311 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
312 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]])
313 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
314 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
315 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
316 // CHECK1: arrayctor.cont:
317 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP17]], i32 0, i32 1
318 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP19]])
319 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 3
320 // CHECK1-NEXT: store ptr @.omp_task_destructor., ptr [[TMP20]], align 8
321 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 5
322 // CHECK1-NEXT: store i64 0, ptr [[TMP21]], align 8
323 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 6
324 // CHECK1-NEXT: store i64 9, ptr [[TMP22]], align 8
325 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 7
326 // CHECK1-NEXT: store i64 1, ptr [[TMP23]], align 8
327 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP14]], i32 0, i32 9
328 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP24]], i8 0, i64 8, i1 false)
329 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[TMP23]], align 8
330 // CHECK1-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[TMP13]], i32 1, ptr [[TMP21]], ptr [[TMP22]], i64 [[TMP25]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.)
331 // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP5]])
332 // CHECK1-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP5]])
333 // CHECK1-NEXT: br label [[OMP_IF_END]]
334 // CHECK1: omp_if.end:
335 // CHECK1-NEXT: ret void
336 //
337 //
338 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
339 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]], ptr noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] {
340 // CHECK1-NEXT: entry:
341 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
342 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
343 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
344 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8
345 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8
346 // CHECK1-NEXT: [[DOTADDR5:%.*]] = alloca ptr, align 8
347 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
348 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
349 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
350 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
351 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
352 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTADDR5]], align 8
353 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR]], align 8
354 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP6]], i32 0, i32 0
355 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
356 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8
357 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 1
358 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
359 // CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8
360 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 2
361 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
362 // CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP12]], align 8
363 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 3
364 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
365 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP14]], align 8
366 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP6]], i32 0, i32 4
367 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTADDR5]], align 8
368 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP16]], align 8
369 // CHECK1-NEXT: ret void
370 //
371 //
372 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
373 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
374 // CHECK1-NEXT: entry:
375 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
376 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
377 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
378 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
379 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
380 // CHECK1-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
381 // CHECK1-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
382 // CHECK1-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
383 // CHECK1-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
384 // CHECK1-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
385 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
386 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
387 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
388 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
389 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
390 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR4_I:%.*]] = alloca ptr, align 8
391 // CHECK1-NEXT: [[I_I:%.*]] = alloca i32, align 4
392 // CHECK1-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
393 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
394 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
395 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
396 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
397 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
398 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
399 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
400 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
401 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
402 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
403 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
404 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
405 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
406 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
407 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
408 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
409 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
410 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
411 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
412 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
413 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
414 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
415 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
416 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
417 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
418 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
419 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
420 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
421 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
422 // CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
423 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
424 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
425 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
426 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
427 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
428 // CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
429 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
430 // CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
431 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
432 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
433 // CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]], ptr [[DOTLASTPRIV_PTR_ADDR2_I]], ptr [[DOTLASTPRIV_PTR_ADDR3_I]], ptr [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
434 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 3
435 // CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8
436 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 1
437 // CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8
438 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2
439 // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8
440 // CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP19]], align 8
441 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2
442 // CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8
443 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 3
444 // CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8
445 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 4
446 // CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8
447 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
448 // CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
449 // CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]]
450 // CHECK1-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]]
451 // CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META14]]
452 // CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
453 // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP40]] to i32
454 // CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
455 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
456 // CHECK1: omp.inner.for.cond.i:
457 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
458 // CHECK1-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP41]] to i64
459 // CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
460 // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP42]]
461 // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
462 // CHECK1: omp.inner.for.body.i:
463 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
464 // CHECK1-NEXT: store i32 [[TMP43]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
465 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP36]], align 4, !llvm.access.group [[ACC_GRP15]]
466 // CHECK1-NEXT: store i32 [[TMP44]], ptr [[TMP38]], align 4, !llvm.access.group [[ACC_GRP15]]
467 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP37]], ptr align 8 [[TMP35]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]]
468 // CHECK1-NEXT: store i32 33, ptr [[TMP39]], align 4, !llvm.access.group [[ACC_GRP15]]
469 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
470 // CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP45]], 1
471 // CHECK1-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
472 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
473 // CHECK1: omp.inner.for.end.i:
474 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
475 // CHECK1-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0
476 // CHECK1-NEXT: br i1 [[TMP47]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
477 // CHECK1: .omp.lastprivate.then.i:
478 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP23]], ptr align 8 [[TMP35]], i64 8, i1 false)
479 // CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[TMP36]], align 4
480 // CHECK1-NEXT: store i32 [[TMP48]], ptr [[TMP25]], align 4
481 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP27]], i64 2
482 // CHECK1-NEXT: br label [[OMP_ARRAYCPY_BODY_I:%.*]]
483 // CHECK1: omp.arraycpy.body.i:
484 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST_I:%.*]] = phi ptr [ [[TMP37]], [[DOTOMP_LASTPRIVATE_THEN_I]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT_I:%.*]], [[OMP_ARRAYCPY_BODY_I]] ]
485 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST_I:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_THEN_I]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT_I:%.*]], [[OMP_ARRAYCPY_BODY_I]] ]
486 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[OMP_ARRAYCPY_DESTELEMENTPAST_I]], ptr align 8 [[OMP_ARRAYCPY_SRCELEMENTPAST_I]], i64 8, i1 false)
487 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT_I]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST_I]], i32 1
488 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT_I]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST_I]], i32 1
489 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE_I:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT_I]], [[TMP49]]
490 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE_I]], label [[OMP_ARRAYCPY_DONE8_I:%.*]], label [[OMP_ARRAYCPY_BODY_I]]
491 // CHECK1: omp.arraycpy.done8.i:
492 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP28]], ptr align 4 [[TMP38]], i64 8, i1 false)
493 // CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP39]], align 4
494 // CHECK1-NEXT: store i32 [[TMP50]], ptr [[TMP34]], align 4
495 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
496 // CHECK1: .omp_outlined..exit:
497 // CHECK1-NEXT: ret i32 0
498 //
499 //
500 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup.
501 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
502 // CHECK1-NEXT: entry:
503 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
504 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
505 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
506 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
507 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
508 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
509 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
510 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
511 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
512 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
513 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 8
514 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
515 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP7]], i32 0, i32 0
516 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP8]], i32 0, i32 0
517 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
518 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
519 // CHECK1: arrayctor.loop:
520 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
521 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]])
522 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
523 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
524 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
525 // CHECK1: arrayctor.cont:
526 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP7]], i32 0, i32 1
527 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP9]])
528 // CHECK1-NEXT: ret void
529 //
530 //
531 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_destructor.
532 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
533 // CHECK1-NEXT: entry:
534 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
535 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
536 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
537 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
538 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
539 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
540 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1
541 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
542 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
543 // CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]]
544 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0
545 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
546 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
547 // CHECK1: arraydestroy.body:
548 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
549 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
550 // CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
551 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
552 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
553 // CHECK1: arraydestroy.done2:
554 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
555 // CHECK1-NEXT: ret i32 [[TMP7]]
556 //
557 //
558 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
559 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
560 // CHECK1-NEXT: entry:
561 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
562 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
563 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
564 // CHECK1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
565 // CHECK1-NEXT: ret void
566 //
567 //
568 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
569 // CHECK1-SAME: () #[[ATTR1]] {
570 // CHECK1-NEXT: entry:
571 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
572 // CHECK1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
573 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
574 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
575 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
576 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
577 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
578 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]])
579 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
580 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 128
581 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
582 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
583 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
584 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
585 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
586 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]])
587 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
588 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
589 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
590 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
591 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
592 // CHECK1: arraydestroy.body:
593 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
594 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
595 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
596 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
597 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
598 // CHECK1: arraydestroy.done1:
599 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
600 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
601 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
602 // CHECK1-NEXT: ret i32 [[TMP1]]
603 //
604 //
605 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
606 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
607 // CHECK1-NEXT: entry:
608 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
609 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
610 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
611 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
612 // CHECK1-NEXT: store double 0.000000e+00, ptr [[F]], align 8
613 // CHECK1-NEXT: ret void
614 //
615 //
616 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
617 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
618 // CHECK1-NEXT: entry:
619 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
620 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
621 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
622 // CHECK1-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
623 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
624 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
625 // CHECK1-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
626 // CHECK1-NEXT: store double [[TMP0]], ptr [[F]], align 8
627 // CHECK1-NEXT: ret void
628 //
629 //
630 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
631 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
632 // CHECK1-NEXT: entry:
633 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
634 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
635 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
636 // CHECK1-NEXT: ret void
637 //
638 //
639 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
640 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
641 // CHECK1-NEXT: entry:
642 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
643 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
644 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
645 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
646 // CHECK1-NEXT: ret void
647 //
648 //
649 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
650 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
651 // CHECK1-NEXT: entry:
652 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
653 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
654 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
655 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
656 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
657 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
658 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
659 // CHECK1-NEXT: ret void
660 //
661 //
662 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
663 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
664 // CHECK1-NEXT: entry:
665 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
666 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
667 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
668 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
669 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
670 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
671 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
672 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
673 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
674 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
675 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
676 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
677 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
678 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
679 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
680 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
681 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
682 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
683 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
684 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
685 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP5]])
686 // CHECK1-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP6]], 0
687 // CHECK1-NEXT: br i1 [[TMP7]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
688 // CHECK1: omp_if.then:
689 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 0
690 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP8]], align 8
691 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 1
692 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP9]], align 8
693 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 2
694 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP10]], align 8
695 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[AGG_CAPTURED]], i32 0, i32 3
696 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP11]], align 8
697 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP5]])
698 // CHECK1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP5]], i32 9, i64 256, i64 32, ptr @.omp_task_entry..3)
699 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP12]], i32 0, i32 0
700 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP13]], i32 0, i32 0
701 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 128
702 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP15]], ptr align 8 [[AGG_CAPTURED]], i64 32, i1 false)
703 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP12]], i32 0, i32 2
704 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP16]], i32 0, i32 2
705 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0
706 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
707 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
708 // CHECK1: arrayctor.loop:
709 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
710 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
711 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
712 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
713 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
714 // CHECK1: arrayctor.cont:
715 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP16]], i32 0, i32 3
716 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]])
717 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 3
718 // CHECK1-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP19]], align 8
719 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 5
720 // CHECK1-NEXT: store i64 0, ptr [[TMP20]], align 8
721 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 6
722 // CHECK1-NEXT: store i64 9, ptr [[TMP21]], align 16
723 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 7
724 // CHECK1-NEXT: store i64 1, ptr [[TMP22]], align 8
725 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 9
726 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP23]], i8 0, i64 8, i1 false)
727 // CHECK1-NEXT: [[TMP24:%.*]] = load i64, ptr [[TMP22]], align 8
728 // CHECK1-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[TMP12]], i32 1, ptr [[TMP20]], ptr [[TMP21]], i64 [[TMP24]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..4)
729 // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP5]])
730 // CHECK1-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP5]])
731 // CHECK1-NEXT: br label [[OMP_IF_END]]
732 // CHECK1: omp_if.end:
733 // CHECK1-NEXT: ret void
734 //
735 //
736 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map..2
737 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6]] {
738 // CHECK1-NEXT: entry:
739 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
740 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
741 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
742 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8
743 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8
744 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
745 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
746 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
747 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
748 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
749 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
750 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0
751 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
752 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
753 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1
754 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
755 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8
756 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2
757 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
758 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8
759 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3
760 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
761 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8
762 // CHECK1-NEXT: ret void
763 //
764 //
765 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry..3
766 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
767 // CHECK1-NEXT: entry:
768 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
769 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
770 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
771 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
772 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
773 // CHECK1-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
774 // CHECK1-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
775 // CHECK1-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
776 // CHECK1-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
777 // CHECK1-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
778 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
779 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
780 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
781 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
782 // CHECK1-NEXT: [[DOTLASTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
783 // CHECK1-NEXT: [[I_I:%.*]] = alloca i32, align 4
784 // CHECK1-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
785 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
786 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
787 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
788 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
789 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
790 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
791 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0
792 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
793 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
794 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128
795 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2
796 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
797 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
798 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
799 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 16
800 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
801 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
802 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
803 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64
804 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
805 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
806 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
807 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
808 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
809 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
810 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
811 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]]
812 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]]
813 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
814 // CHECK1-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
815 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]]
816 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]]
817 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]]
818 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META32]]
819 // CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META32]]
820 // CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META32]]
821 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
822 // CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]]
823 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]]
824 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]]
825 // CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]], ptr [[DOTLASTPRIV_PTR_ADDR2_I]], ptr [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
826 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP19]], i32 0, i32 1
827 // CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8
828 // CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP19]], align 8
829 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 2
830 // CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8
831 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 2
832 // CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
833 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 3
834 // CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8
835 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 3
836 // CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8
837 // CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]]
838 // CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]]
839 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]]
840 // CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META32]]
841 // CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]]
842 // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP37]] to i32
843 // CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]]
844 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
845 // CHECK1: omp.inner.for.cond.i:
846 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33:![0-9]+]]
847 // CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP38]] to i64
848 // CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
849 // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP39]]
850 // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
851 // CHECK1: omp.inner.for.body.i:
852 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
853 // CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
854 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP33]], align 128, !llvm.access.group [[ACC_GRP33]]
855 // CHECK1-NEXT: store i32 [[TMP41]], ptr [[TMP34]], align 4, !llvm.access.group [[ACC_GRP33]]
856 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[TMP36]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]]
857 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
858 // CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP42]], 1
859 // CHECK1-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]]
860 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]]
861 // CHECK1: omp.inner.for.end.i:
862 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META32]]
863 // CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
864 // CHECK1-NEXT: br i1 [[TMP44]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
865 // CHECK1: .omp.lastprivate.then.i:
866 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[TMP33]], align 128
867 // CHECK1-NEXT: store i32 [[TMP45]], ptr [[TMP23]], align 128
868 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP24]], ptr align 4 [[TMP34]], i64 8, i1 false)
869 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[TMP26]], i64 2
870 // CHECK1-NEXT: br label [[OMP_ARRAYCPY_BODY_I:%.*]]
871 // CHECK1: omp.arraycpy.body.i:
872 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST_I:%.*]] = phi ptr [ [[TMP35]], [[DOTOMP_LASTPRIVATE_THEN_I]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT_I:%.*]], [[OMP_ARRAYCPY_BODY_I]] ]
873 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST_I:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_THEN_I]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT_I:%.*]], [[OMP_ARRAYCPY_BODY_I]] ]
874 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST_I]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST_I]], i64 4, i1 false)
875 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT_I]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST_I]], i32 1
876 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT_I]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST_I]], i32 1
877 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE_I:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT_I]], [[TMP46]]
878 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE_I]], label [[OMP_ARRAYCPY_DONE7_I:%.*]], label [[OMP_ARRAYCPY_BODY_I]]
879 // CHECK1: omp.arraycpy.done7.i:
880 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP30]], ptr align 4 [[TMP36]], i64 4, i1 false)
881 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]]
882 // CHECK1: .omp_outlined..1.exit:
883 // CHECK1-NEXT: ret i32 0
884 //
885 //
886 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_dup..4
887 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
888 // CHECK1-NEXT: entry:
889 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
890 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
891 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
892 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
893 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
894 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
895 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
896 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0
897 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
898 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
899 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 64
900 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2
901 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP7]], i32 0, i32 2
902 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP8]], i32 0, i32 0
903 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
904 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
905 // CHECK1: arrayctor.loop:
906 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
907 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
908 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
909 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
910 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
911 // CHECK1: arrayctor.cont:
912 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP7]], i32 0, i32 3
913 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]])
914 // CHECK1-NEXT: ret void
915 //
916 //
917 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_destructor..5
918 // CHECK1-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
919 // CHECK1-NEXT: entry:
920 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
921 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
922 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
923 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
924 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
925 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
926 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2
927 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2
928 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3
929 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]]
930 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0
931 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
932 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
933 // CHECK1: arraydestroy.body:
934 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
935 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
936 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
937 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
938 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
939 // CHECK1: arraydestroy.done2:
940 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4
941 // CHECK1-NEXT: ret i32 [[TMP7]]
942 //
943 //
944 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
945 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
946 // CHECK1-NEXT: entry:
947 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
948 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
949 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
950 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
951 // CHECK1-NEXT: ret void
952 //
953 //
954 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
955 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
956 // CHECK1-NEXT: entry:
957 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
958 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
959 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
960 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
961 // CHECK1-NEXT: store i32 0, ptr [[F]], align 4
962 // CHECK1-NEXT: ret void
963 //
964 //
965 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
966 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
967 // CHECK1-NEXT: entry:
968 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
969 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
970 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
971 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
972 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
973 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
974 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
975 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
976 // CHECK1-NEXT: ret void
977 //
978 //
979 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
980 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
981 // CHECK1-NEXT: entry:
982 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
983 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
984 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
985 // CHECK1-NEXT: ret void
986 //
987 //
988 // CHECK3-LABEL: define {{[^@]+}}@main
989 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
990 // CHECK3-NEXT: entry:
991 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
992 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
993 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
994 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
995 // CHECK3-NEXT: ret i32 0
996 //
997 //
998 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
999 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] {
1000 // CHECK3-NEXT: entry:
1001 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1002 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1003 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
1004 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1005 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1006 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
1007 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1008 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
1009 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1010 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8
1011 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
1012 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
1013 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
1014 // CHECK3-NEXT: ret void
1015 //
1016 //
1017 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
1018 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
1019 // CHECK3-NEXT: entry:
1020 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1021 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1022 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1023 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1024 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1025 // CHECK3-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1026 // CHECK3-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1027 // CHECK3-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1028 // CHECK3-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1029 // CHECK3-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1030 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1031 // CHECK3-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1032 // CHECK3-NEXT: [[DOTLASTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
1033 // CHECK3-NEXT: [[I_I:%.*]] = alloca i32, align 4
1034 // CHECK3-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1035 // CHECK3-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
1036 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1037 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1038 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1039 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1040 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1041 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1042 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1043 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1044 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1045 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1046 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1047 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1048 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
1049 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1050 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
1051 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1052 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
1053 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1054 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
1055 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1056 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1057 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1058 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1059 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1060 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1061 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1062 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1063 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1064 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1065 // CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1066 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1067 // CHECK3-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1068 // CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1069 // CHECK3-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1070 // CHECK3-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1071 // CHECK3-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1072 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1073 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1074 // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1075 // CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1076 // CHECK3-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]
1077 // CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8
1078 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1
1079 // CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
1080 // CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
1081 // CHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
1082 // CHECK3-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1083 // CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32
1084 // CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1085 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
1086 // CHECK3: omp.inner.for.cond.i:
1087 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
1088 // CHECK3-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP28]] to i64
1089 // CHECK3-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1090 // CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP29]]
1091 // CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
1092 // CHECK3: omp.inner.for.body.i:
1093 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1094 // CHECK3-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1095 // CHECK3-NEXT: store double 1.000000e+00, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP15]]
1096 // CHECK3-NEXT: store i32 11, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]]
1097 // CHECK3-NEXT: store ptr [[TMP25]], ptr [[REF_TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1098 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1
1099 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1100 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]]
1101 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1102 // CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP32]], 1
1103 // CHECK3-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1104 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
1105 // CHECK3: omp.inner.for.end.i:
1106 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1107 // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1108 // CHECK3-NEXT: br i1 [[TMP34]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1109 // CHECK3: .omp.lastprivate.then.i:
1110 // CHECK3-NEXT: [[TMP35:%.*]] = load double, ptr [[TMP25]], align 8
1111 // CHECK3-NEXT: store volatile double [[TMP35]], ptr [[TMP22]], align 8
1112 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP26]], align 4
1113 // CHECK3-NEXT: store i32 [[TMP36]], ptr [[TMP24]], align 4
1114 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
1115 // CHECK3: .omp_outlined..exit:
1116 // CHECK3-NEXT: ret i32 0
1117 //
1118 //
1119 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_dup.
1120 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR6]] {
1121 // CHECK3-NEXT: entry:
1122 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1123 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1124 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
1125 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1126 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1127 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
1128 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1129 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1130 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
1131 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
1132 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 8
1133 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1134 // CHECK3-NEXT: ret void
1135 //
1136 //
1137 // CHECK4-LABEL: define {{[^@]+}}@main
1138 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] {
1139 // CHECK4-NEXT: entry:
1140 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1141 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4
1142 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
1143 // CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)
1144 // CHECK4-NEXT: ret i32 0
1145 //
1146 //
1147 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
1148 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
1149 // CHECK4-NEXT: entry:
1150 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1151 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1152 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1153 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1154 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)
1155 // CHECK4-NEXT: ret void
1156 //
1157 //
1158 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
1159 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
1160 // CHECK4-NEXT: entry:
1161 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1162 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1163 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
1164 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1165 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1166 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1167 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1168 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1169 // CHECK4-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP1]])
1170 // CHECK4-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
1171 // CHECK4-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1172 // CHECK4: omp_if.then:
1173 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
1174 // CHECK4-NEXT: store ptr @g, ptr [[TMP4]], align 8
1175 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
1176 // CHECK4-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP5]], align 8
1177 // CHECK4-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
1178 // CHECK4-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 16, ptr @.omp_task_entry.)
1179 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP6]], i32 0, i32 0
1180 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0
1181 // CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
1182 // CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)
1183 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP6]], i32 0, i32 1
1184 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 5
1185 // CHECK4-NEXT: store i64 0, ptr [[TMP11]], align 8
1186 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 6
1187 // CHECK4-NEXT: store i64 9, ptr [[TMP12]], align 8
1188 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 7
1189 // CHECK4-NEXT: store i64 1, ptr [[TMP13]], align 8
1190 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP7]], i32 0, i32 9
1191 // CHECK4-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP14]], i8 0, i64 8, i1 false)
1192 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP13]], align 8
1193 // CHECK4-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[TMP6]], i32 1, ptr [[TMP11]], ptr [[TMP12]], i64 [[TMP15]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.)
1194 // CHECK4-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP1]])
1195 // CHECK4-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP1]])
1196 // CHECK4-NEXT: br label [[OMP_IF_END]]
1197 // CHECK4: omp_if.end:
1198 // CHECK4-NEXT: ret void
1199 //
1200 //
1201 // CHECK4-LABEL: define {{[^@]+}}@_block_invoke
1202 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
1203 // CHECK4-NEXT: entry:
1204 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1205 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1206 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1207 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1208 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
1209 // CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8
1210 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
1211 // CHECK4-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8
1212 // CHECK4-NEXT: ret void
1213 //
1214 //
1215 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.
1216 // CHECK4-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] {
1217 // CHECK4-NEXT: entry:
1218 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1219 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1220 // CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
1221 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1222 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1223 // CHECK4-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
1224 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1225 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
1226 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1227 // CHECK4-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8
1228 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
1229 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
1230 // CHECK4-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
1231 // CHECK4-NEXT: ret void
1232 //
1233 //
1234 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
1235 // CHECK4-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
1236 // CHECK4-NEXT: entry:
1237 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1238 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1239 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1240 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1241 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1242 // CHECK4-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1243 // CHECK4-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1244 // CHECK4-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1245 // CHECK4-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1246 // CHECK4-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1247 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1248 // CHECK4-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1249 // CHECK4-NEXT: [[DOTLASTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
1250 // CHECK4-NEXT: [[I_I:%.*]] = alloca i32, align 4
1251 // CHECK4-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1252 // CHECK4-NEXT: [[BLOCK_I:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8
1253 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1254 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1255 // CHECK4-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1256 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1257 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1258 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1259 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1260 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1261 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1262 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1263 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1264 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1265 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
1266 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1267 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
1268 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1269 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
1270 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1271 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
1272 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1273 // CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1274 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1275 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1276 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1277 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1278 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1279 // CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1280 // CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1281 // CHECK4-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1282 // CHECK4-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1283 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1284 // CHECK4-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1285 // CHECK4-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1286 // CHECK4-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1287 // CHECK4-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1288 // CHECK4-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1289 // CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1290 // CHECK4-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1291 // CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1292 // CHECK4-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1293 // CHECK4-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]
1294 // CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8
1295 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1
1296 // CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
1297 // CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
1298 // CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
1299 // CHECK4-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1300 // CHECK4-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32
1301 // CHECK4-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1302 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
1303 // CHECK4: omp.inner.for.cond.i:
1304 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
1305 // CHECK4-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP28]] to i64
1306 // CHECK4-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1307 // CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP29]]
1308 // CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
1309 // CHECK4: omp.inner.for.body.i:
1310 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1311 // CHECK4-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1312 // CHECK4-NEXT: store double 1.000000e+00, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP15]]
1313 // CHECK4-NEXT: store i32 11, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]]
1314 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1315 // CHECK4-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 1
1316 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1317 // CHECK4-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 2
1318 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1319 // CHECK4-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 3
1320 // CHECK4-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1321 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 4
1322 // CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1323 // CHECK4-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 5
1324 // CHECK4-NEXT: [[TMP31:%.*]] = load volatile double, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP15]]
1325 // CHECK4-NEXT: store volatile double [[TMP31]], ptr [[BLOCK_CAPTURED_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1326 // CHECK4-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 6
1327 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]]
1328 // CHECK4-NEXT: store i32 [[TMP32]], ptr [[BLOCK_CAPTURED3_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1329 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK_I]], i32 0, i32 3
1330 // CHECK4-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1331 // CHECK4-NEXT: call void [[TMP34]](ptr noundef [[BLOCK_I]]) #[[ATTR4]], !llvm.access.group [[ACC_GRP15]]
1332 // CHECK4-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1333 // CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP35]], 1
1334 // CHECK4-NEXT: store i32 [[ADD4_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1335 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
1336 // CHECK4: omp.inner.for.end.i:
1337 // CHECK4-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1338 // CHECK4-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
1339 // CHECK4-NEXT: br i1 [[TMP37]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1340 // CHECK4: .omp.lastprivate.then.i:
1341 // CHECK4-NEXT: [[TMP38:%.*]] = load double, ptr [[TMP25]], align 8
1342 // CHECK4-NEXT: store volatile double [[TMP38]], ptr [[TMP22]], align 8
1343 // CHECK4-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP26]], align 4
1344 // CHECK4-NEXT: store i32 [[TMP39]], ptr [[TMP24]], align 4
1345 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
1346 // CHECK4: .omp_outlined..exit:
1347 // CHECK4-NEXT: ret i32 0
1348 //
1349 //
1350 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_dup.
1351 // CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
1352 // CHECK4-NEXT: entry:
1353 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1354 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1355 // CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
1356 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1357 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1358 // CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
1359 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1360 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1361 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
1362 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
1363 // CHECK4-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 8
1364 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1365 // CHECK4-NEXT: ret void
1366 //
1367 //
1368 // CHECK5-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
1369 // CHECK5-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
1370 // CHECK5-NEXT: entry:
1371 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1372 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
1373 // CHECK5-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1374 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1375 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
1376 // CHECK5-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1377 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1378 // CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1379 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 3, ptr @_Z10array_funciPfP2St.omp_outlined, i64 [[TMP1]], ptr [[A_ADDR]], ptr [[S_ADDR]])
1380 // CHECK5-NEXT: ret void
1381 //
1382 //
1383 // CHECK5-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St.omp_outlined
1384 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[S:%.*]]) #[[ATTR1:[0-9]+]] {
1385 // CHECK5-NEXT: entry:
1386 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1387 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1388 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1389 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
1390 // CHECK5-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
1391 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
1392 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
1393 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1394 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1395 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1396 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
1397 // CHECK5-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
1398 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1399 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1400 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1401 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1402 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1403 // CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]])
1404 // CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
1405 // CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1406 // CHECK5: omp_if.then:
1407 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
1408 // CHECK5-NEXT: store i64 [[TMP0]], ptr [[TMP7]], align 8
1409 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
1410 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP8]], align 8
1411 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
1412 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP9]], align 8
1413 // CHECK5-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
1414 // CHECK5-NEXT: [[TMP10:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 1, i64 96, i64 24, ptr @.omp_task_entry.)
1415 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP10]], i32 0, i32 0
1416 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP11]], i32 0, i32 0
1417 // CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
1418 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP13]], ptr align 8 [[AGG_CAPTURED]], i64 24, i1 false)
1419 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP10]], i32 0, i32 1
1420 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP11]], i32 0, i32 5
1421 // CHECK5-NEXT: store i64 0, ptr [[TMP15]], align 8
1422 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP11]], i32 0, i32 6
1423 // CHECK5-NEXT: store i64 9, ptr [[TMP16]], align 8
1424 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP11]], i32 0, i32 7
1425 // CHECK5-NEXT: store i64 1, ptr [[TMP17]], align 8
1426 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP11]], i32 0, i32 9
1427 // CHECK5-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP18]], i8 0, i64 8, i1 false)
1428 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP17]], align 8
1429 // CHECK5-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP4]], ptr [[TMP10]], i32 1, ptr [[TMP15]], ptr [[TMP16]], i64 [[TMP19]], i32 1, i32 0, i64 0, ptr @.omp_task_dup.)
1430 // CHECK5-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]])
1431 // CHECK5-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP4]])
1432 // CHECK5-NEXT: br label [[OMP_IF_END]]
1433 // CHECK5: omp_if.end:
1434 // CHECK5-NEXT: ret void
1435 //
1436 //
1437 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map.
1438 // CHECK5-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] {
1439 // CHECK5-NEXT: entry:
1440 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1441 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1442 // CHECK5-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
1443 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1444 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1445 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
1446 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1447 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0
1448 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1449 // CHECK5-NEXT: store ptr [[TMP4]], ptr [[TMP5]], align 8
1450 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1
1451 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
1452 // CHECK5-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
1453 // CHECK5-NEXT: ret void
1454 //
1455 //
1456 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.
1457 // CHECK5-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
1458 // CHECK5-NEXT: entry:
1459 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1460 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1461 // CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1462 // CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1463 // CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1464 // CHECK5-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1465 // CHECK5-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1466 // CHECK5-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1467 // CHECK5-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1468 // CHECK5-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1469 // CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1470 // CHECK5-NEXT: [[DOTLASTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1471 // CHECK5-NEXT: [[DOTLASTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
1472 // CHECK5-NEXT: [[I_I:%.*]] = alloca i32, align 4
1473 // CHECK5-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1474 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1475 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1476 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1477 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1478 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1479 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1480 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1481 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1482 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1483 // CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1484 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1485 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1486 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8
1487 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1488 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 8
1489 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1490 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 8
1491 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1492 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8
1493 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1494 // CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8
1495 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1496 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1497 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1498 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1499 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1500 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1501 // CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1502 // CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1503 // CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1504 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1505 // CHECK5-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1506 // CHECK5-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1507 // CHECK5-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1508 // CHECK5-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1509 // CHECK5-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1510 // CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1511 // CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1512 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[TMP19]], align 8
1513 // CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1514 // CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1515 // CHECK5-NEXT: call void [[TMP21]](ptr [[TMP22]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]
1516 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1
1517 // CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8
1518 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2
1519 // CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8
1520 // CHECK5-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]]
1521 // CHECK5-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]]
1522 // CHECK5-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1523 // CHECK5-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32
1524 // CHECK5-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1525 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
1526 // CHECK5: omp.inner.for.cond.i:
1527 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
1528 // CHECK5-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP30]] to i64
1529 // CHECK5-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1530 // CHECK5-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP31]]
1531 // CHECK5-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
1532 // CHECK5: omp.inner.for.body.i:
1533 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1534 // CHECK5-NEXT: store i32 [[TMP32]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1535 // CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1536 // CHECK5-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP33]], 1
1537 // CHECK5-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1538 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
1539 // CHECK5: omp.inner.for.end.i:
1540 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1541 // CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1542 // CHECK5-NEXT: br i1 [[TMP35]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1543 // CHECK5: .omp.lastprivate.then.i:
1544 // CHECK5-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP27]], align 8
1545 // CHECK5-NEXT: store ptr [[TMP36]], ptr [[TMP24]], align 8
1546 // CHECK5-NEXT: [[TMP37:%.*]] = load ptr, ptr [[TMP28]], align 8
1547 // CHECK5-NEXT: store ptr [[TMP37]], ptr [[TMP26]], align 8
1548 // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
1549 // CHECK5: .omp_outlined..exit:
1550 // CHECK5-NEXT: ret i32 0
1551 //
1552 //
1553 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_dup.
1554 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR5]] {
1555 // CHECK5-NEXT: entry:
1556 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
1557 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1558 // CHECK5-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
1559 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1560 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1561 // CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4
1562 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1563 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1564 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8
1565 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4
1566 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 8
1567 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1568 // CHECK5-NEXT: ret void
1569 //
1570 //
1571 // CHECK6-LABEL: define {{[^@]+}}@_Z4loopv
1572 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
1573 // CHECK6-NEXT: entry:
1574 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
1575 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4
1576 // CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @_Z4loopv.omp_outlined, ptr [[I]], ptr [[J]])
1577 // CHECK6-NEXT: ret void
1578 //
1579 //
1580 // CHECK6-LABEL: define {{[^@]+}}@_Z4loopv.omp_outlined
1581 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[J:%.*]]) #[[ATTR1:[0-9]+]] {
1582 // CHECK6-NEXT: entry:
1583 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1584 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1585 // CHECK6-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8
1586 // CHECK6-NEXT: [[J_ADDR:%.*]] = alloca ptr, align 8
1587 // CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
1588 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
1589 // CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1590 // CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1591 // CHECK6-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8
1592 // CHECK6-NEXT: store ptr [[J]], ptr [[J_ADDR]], align 8
1593 // CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1594 // CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[J_ADDR]], align 8
1595 // CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1596 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1597 // CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]])
1598 // CHECK6-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0
1599 // CHECK6-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
1600 // CHECK6: omp_if.then:
1601 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
1602 // CHECK6-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8
1603 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
1604 // CHECK6-NEXT: store ptr [[TMP1]], ptr [[TMP7]], align 8
1605 // CHECK6-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
1606 // CHECK6-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP3]], i32 1, i64 80, i64 16, ptr @.omp_task_entry.)
1607 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP8]], i32 0, i32 0
1608 // CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP9]], i32 0, i32 0
1609 // CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
1610 // CHECK6-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP11]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false)
1611 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP9]], i32 0, i32 5
1612 // CHECK6-NEXT: store i64 0, ptr [[TMP12]], align 8
1613 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP9]], i32 0, i32 6
1614 // CHECK6-NEXT: store i64 9, ptr [[TMP13]], align 8
1615 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP9]], i32 0, i32 7
1616 // CHECK6-NEXT: store i64 1, ptr [[TMP14]], align 8
1617 // CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP9]], i32 0, i32 9
1618 // CHECK6-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP15]], i8 0, i64 8, i1 false)
1619 // CHECK6-NEXT: [[TMP16:%.*]] = load i64, ptr [[TMP14]], align 8
1620 // CHECK6-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP3]], ptr [[TMP8]], i32 1, ptr [[TMP12]], ptr [[TMP13]], i64 [[TMP16]], i32 1, i32 0, i64 0, ptr null)
1621 // CHECK6-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP3]])
1622 // CHECK6-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP3]])
1623 // CHECK6-NEXT: br label [[OMP_IF_END]]
1624 // CHECK6: omp_if.end:
1625 // CHECK6-NEXT: ret void
1626 //
1627 //
1628 // CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry.
1629 // CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
1630 // CHECK6-NEXT: entry:
1631 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1632 // CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1633 // CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1634 // CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1635 // CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1636 // CHECK6-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
1637 // CHECK6-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
1638 // CHECK6-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
1639 // CHECK6-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
1640 // CHECK6-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca ptr, align 8
1641 // CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1642 // CHECK6-NEXT: [[DOTLINEAR_START_I:%.*]] = alloca i32, align 4
1643 // CHECK6-NEXT: [[DOTLINEAR_START1_I:%.*]] = alloca i32, align 4
1644 // CHECK6-NEXT: [[I_I:%.*]] = alloca i32, align 4
1645 // CHECK6-NEXT: [[J_I:%.*]] = alloca i32, align 4
1646 // CHECK6-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
1647 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
1648 // CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
1649 // CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1650 // CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1651 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1652 // CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1653 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1654 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1655 // CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1656 // CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1657 // CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5
1658 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP8]], align 8
1659 // CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6
1660 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8
1661 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 7
1662 // CHECK6-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8
1663 // CHECK6-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 8
1664 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
1665 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9
1666 // CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
1667 // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
1668 // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
1669 // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
1670 // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
1671 // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
1672 // CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]]
1673 // CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]]
1674 // CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]]
1675 // CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]]
1676 // CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]]
1677 // CHECK6-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1678 // CHECK6-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]]
1679 // CHECK6-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]]
1680 // CHECK6-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1681 // CHECK6-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]]
1682 // CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1683 // CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]]
1684 // CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
1685 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1686 // CHECK6-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START_I]], align 4, !noalias [[META14]]
1687 // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP18]], i32 0, i32 1
1688 // CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
1689 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
1690 // CHECK6-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START1_I]], align 4, !noalias [[META14]]
1691 // CHECK6-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP18]], align 8
1692 // CHECK6-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]]
1693 // CHECK6-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP25]] to i32
1694 // CHECK6-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]]
1695 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
1696 // CHECK6: omp.inner.for.cond.i:
1697 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]]
1698 // CHECK6-NEXT: [[CONV3_I:%.*]] = sext i32 [[TMP26]] to i64
1699 // CHECK6-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1700 // CHECK6-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV3_I]], [[TMP27]]
1701 // CHECK6-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]]
1702 // CHECK6: omp.inner.for.body.i:
1703 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1704 // CHECK6-NEXT: store i32 [[TMP28]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1705 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTLINEAR_START1_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1706 // CHECK6-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1707 // CHECK6-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
1708 // CHECK6-NEXT: store i32 [[ADD5_I]], ptr [[J_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1709 // CHECK6-NEXT: [[TMP31:%.*]] = load i32, ptr [[J_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1710 // CHECK6-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP31]], 1
1711 // CHECK6-NEXT: store i32 [[INC_I]], ptr [[J_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1712 // CHECK6-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1713 // CHECK6-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP32]], 1
1714 // CHECK6-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]]
1715 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
1716 // CHECK6: omp.inner.for.end.i:
1717 // CHECK6-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]]
1718 // CHECK6-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1719 // CHECK6-NEXT: br i1 [[TMP34]], label [[DOTOMP_LINEAR_PU_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1720 // CHECK6: .omp.linear.pu.i:
1721 // CHECK6-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP18]], align 8
1722 // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP18]], i32 0, i32 1
1723 // CHECK6-NEXT: [[TMP37:%.*]] = load ptr, ptr [[TMP36]], align 8
1724 // CHECK6-NEXT: [[TMP38:%.*]] = load i32, ptr [[J_I]], align 4, !noalias [[META14]]
1725 // CHECK6-NEXT: store i32 [[TMP38]], ptr [[TMP37]], align 4
1726 // CHECK6-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
1727 // CHECK6: .omp_outlined..exit:
1728 // CHECK6-NEXT: ret i32 0
1729 //
1730 //
1731 // CHECK7-LABEL: define {{[^@]+}}@main
1732 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1733 // CHECK7-NEXT: entry:
1734 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1735 // CHECK7-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
1736 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
1737 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1738 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1739 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
1740 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
1741 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1742 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1743 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1744 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1745 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1746 // CHECK7-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 8
1747 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1748 // CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 16
1749 // CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1750 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1751 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4
1752 // CHECK7-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]])
1753 // CHECK7-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]])
1754 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4
1755 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
1756 // CHECK7-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[S_ARR]], double noundef 1.000000e+00)
1757 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
1758 // CHECK7-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
1759 // CHECK7-NEXT: call void @_ZN1SIdEC1Ed(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
1760 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1761 // CHECK7-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
1762 // CHECK7-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1763 // CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1764 // CHECK7-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
1765 // CHECK7-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR1]])
1766 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
1767 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1768 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1769 // CHECK7: arrayctor.loop:
1770 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1771 // CHECK7-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYCTOR_CUR]])
1772 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
1773 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1774 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1775 // CHECK7: arrayctor.cont:
1776 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1777 // CHECK7: omp.inner.for.cond:
1778 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1779 // CHECK7-NEXT: [[CONV5:%.*]] = sext i32 [[TMP1]] to i64
1780 // CHECK7-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
1781 // CHECK7-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV5]], [[TMP2]]
1782 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1783 // CHECK7: omp.inner.for.cond.cleanup:
1784 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1785 // CHECK7: omp.inner.for.body:
1786 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1787 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1788 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1789 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1790 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]]
1791 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 0
1792 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
1793 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 0
1794 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX6]], ptr align 8 [[VAR1]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]]
1795 // CHECK7-NEXT: store i32 33, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1796 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1797 // CHECK7: omp.body.continue:
1798 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1799 // CHECK7: omp.inner.for.inc:
1800 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1801 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP5]], 1
1802 // CHECK7-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1803 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1804 // CHECK7: omp.inner.for.end:
1805 // CHECK7-NEXT: store i32 10, ptr [[I]], align 4
1806 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VAR]], ptr align 8 [[VAR1]], i64 8, i1 false)
1807 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR2]], align 4
1808 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[T_VAR]], align 4
1809 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1810 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN8]], i64 2
1811 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP7]]
1812 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1813 // CHECK7: omp.arraycpy.body:
1814 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR3]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1815 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1816 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 8 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 8, i1 false)
1817 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1818 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1819 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]
1820 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
1821 // CHECK7: omp.arraycpy.done9:
1822 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i64 8, i1 false)
1823 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4
1824 // CHECK7-NEXT: store i32 [[TMP8]], ptr @_ZZ4mainE5sivar, align 4
1825 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
1826 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2
1827 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1828 // CHECK7: arraydestroy.body:
1829 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1830 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1831 // CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
1832 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1833 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1834 // CHECK7: arraydestroy.done11:
1835 // CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR1]]) #[[ATTR3]]
1836 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1837 // CHECK7-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
1838 // CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3]]
1839 // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1840 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2
1841 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
1842 // CHECK7: arraydestroy.body13:
1843 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1844 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1845 // CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]]
1846 // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1847 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1848 // CHECK7: arraydestroy.done17:
1849 // CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]]
1850 // CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]]
1851 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
1852 // CHECK7-NEXT: ret i32 [[TMP11]]
1853 //
1854 //
1855 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
1856 // CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
1857 // CHECK7-NEXT: entry:
1858 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1859 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1860 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1861 // CHECK7-NEXT: call void @_ZN1SIdEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]])
1862 // CHECK7-NEXT: ret void
1863 //
1864 //
1865 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
1866 // CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1867 // CHECK7-NEXT: entry:
1868 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1869 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
1870 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1871 // CHECK7-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
1872 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1873 // CHECK7-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
1874 // CHECK7-NEXT: call void @_ZN1SIdEC2Ed(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
1875 // CHECK7-NEXT: ret void
1876 //
1877 //
1878 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
1879 // CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1880 // CHECK7-NEXT: entry:
1881 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1882 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1883 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1884 // CHECK7-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
1885 // CHECK7-NEXT: ret void
1886 //
1887 //
1888 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1889 // CHECK7-SAME: () #[[ATTR1]] {
1890 // CHECK7-NEXT: entry:
1891 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1892 // CHECK7-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1893 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
1894 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
1895 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1896 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1897 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
1898 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
1899 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1900 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1901 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1902 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1903 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
1904 // CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4
1905 // CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
1906 // CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4
1907 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]])
1908 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1909 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 128
1910 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1911 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
1912 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
1913 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1914 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
1915 // CHECK7-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1916 // CHECK7-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
1917 // CHECK7-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1918 // CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1919 // CHECK7-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
1920 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
1921 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1922 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1923 // CHECK7: arrayctor.loop:
1924 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1925 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1926 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1927 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1928 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1929 // CHECK7: arrayctor.cont:
1930 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]])
1931 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1932 // CHECK7: omp.inner.for.cond:
1933 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1934 // CHECK7-NEXT: [[CONV5:%.*]] = sext i32 [[TMP1]] to i64
1935 // CHECK7-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]
1936 // CHECK7-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV5]], [[TMP2]]
1937 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1938 // CHECK7: omp.inner.for.cond.cleanup:
1939 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1940 // CHECK7: omp.inner.for.body:
1941 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1942 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1943 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1944 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1945 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR1]], align 128, !llvm.access.group [[ACC_GRP6]]
1946 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0
1947 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
1948 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0
1949 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
1950 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1951 // CHECK7: omp.body.continue:
1952 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1953 // CHECK7: omp.inner.for.inc:
1954 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1955 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP5]], 1
1956 // CHECK7-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1957 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1958 // CHECK7: omp.inner.for.end:
1959 // CHECK7-NEXT: store i32 10, ptr [[I]], align 4
1960 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128
1961 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[T_VAR]], align 128
1962 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC2]], i64 8, i1 false)
1963 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1964 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
1965 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP7]]
1966 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1967 // CHECK7: omp.arraycpy.body:
1968 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR3]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1969 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[OMP_INNER_FOR_END]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1970 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1971 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1972 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1973 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]
1974 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
1975 // CHECK7: omp.arraycpy.done9:
1976 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR]], ptr align 4 [[VAR4]], i64 4, i1 false)
1977 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]]
1978 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
1979 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2
1980 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1981 // CHECK7: arraydestroy.body:
1982 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP8]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1983 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1984 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1985 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1986 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1987 // CHECK7: arraydestroy.done11:
1988 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4
1989 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]]
1990 // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1991 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2
1992 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
1993 // CHECK7: arraydestroy.body13:
1994 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP9]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1995 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1996 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]]
1997 // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1998 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1999 // CHECK7: arraydestroy.done17:
2000 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
2001 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]]
2002 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[RETVAL]], align 4
2003 // CHECK7-NEXT: ret i32 [[TMP10]]
2004 //
2005 //
2006 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
2007 // CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2008 // CHECK7-NEXT: entry:
2009 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2010 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2011 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2012 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2013 // CHECK7-NEXT: store double 0.000000e+00, ptr [[F]], align 8
2014 // CHECK7-NEXT: ret void
2015 //
2016 //
2017 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
2018 // CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2019 // CHECK7-NEXT: entry:
2020 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2021 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2022 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2023 // CHECK7-NEXT: ret void
2024 //
2025 //
2026 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
2027 // CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2028 // CHECK7-NEXT: entry:
2029 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2030 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
2031 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2032 // CHECK7-NEXT: store double [[A]], ptr [[A_ADDR]], align 8
2033 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2034 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2035 // CHECK7-NEXT: [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
2036 // CHECK7-NEXT: store double [[TMP0]], ptr [[F]], align 8
2037 // CHECK7-NEXT: ret void
2038 //
2039 //
2040 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2041 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2042 // CHECK7-NEXT: entry:
2043 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2044 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2045 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2046 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2047 // CHECK7-NEXT: ret void
2048 //
2049 //
2050 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2051 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2052 // CHECK7-NEXT: entry:
2053 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2054 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2055 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2056 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2057 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2058 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2059 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2060 // CHECK7-NEXT: ret void
2061 //
2062 //
2063 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2064 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2065 // CHECK7-NEXT: entry:
2066 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2067 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2068 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2069 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
2070 // CHECK7-NEXT: ret void
2071 //
2072 //
2073 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2074 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2075 // CHECK7-NEXT: entry:
2076 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2077 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2078 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2079 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2080 // CHECK7-NEXT: store i32 0, ptr [[F]], align 4
2081 // CHECK7-NEXT: ret void
2082 //
2083 //
2084 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2085 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2086 // CHECK7-NEXT: entry:
2087 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2088 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2089 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2090 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2091 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2092 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2093 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2094 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
2095 // CHECK7-NEXT: ret void
2096 //
2097 //
2098 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2099 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2100 // CHECK7-NEXT: entry:
2101 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
2102 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2103 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2104 // CHECK7-NEXT: ret void
2105 //
2106 //
2107 // CHECK9-LABEL: define {{[^@]+}}@main
2108 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
2109 // CHECK9-NEXT: entry:
2110 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2111 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2112 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
2113 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2114 // CHECK9-NEXT: ret i32 0
2115 //
2116 //
2117 // CHECK10-LABEL: define {{[^@]+}}@main
2118 // CHECK10-SAME: () #[[ATTR1:[0-9]+]] {
2119 // CHECK10-NEXT: entry:
2120 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2121 // CHECK10-NEXT: store i32 0, ptr [[RETVAL]], align 4
2122 // CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
2123 // CHECK10-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)
2124 // CHECK10-NEXT: ret i32 0
2125 //
2126 //
2127 // CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke
2128 // CHECK10-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
2129 // CHECK10-NEXT: entry:
2130 // CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
2131 // CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
2132 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
2133 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2134 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2135 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2136 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
2137 // CHECK10-NEXT: [[G:%.*]] = alloca double, align 8
2138 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2139 // CHECK10-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, i32 }>, align 8
2140 // CHECK10-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2141 // CHECK10-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
2142 // CHECK10-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
2143 // CHECK10-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
2144 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2145 // CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2146 // CHECK10-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2147 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2148 // CHECK10: omp.inner.for.cond:
2149 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
2150 // CHECK10-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
2151 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
2152 // CHECK10-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]]
2153 // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2154 // CHECK10: omp.inner.for.body:
2155 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2156 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2157 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2158 // CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2159 // CHECK10-NEXT: store double 1.000000e+00, ptr [[G]], align 8, !llvm.access.group [[ACC_GRP2]]
2160 // CHECK10-NEXT: store i32 11, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
2161 // CHECK10-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 0
2162 // CHECK10-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8, !llvm.access.group [[ACC_GRP2]]
2163 // CHECK10-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 1
2164 // CHECK10-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8, !llvm.access.group [[ACC_GRP2]]
2165 // CHECK10-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 2
2166 // CHECK10-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4, !llvm.access.group [[ACC_GRP2]]
2167 // CHECK10-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 3
2168 // CHECK10-NEXT: store ptr @__main_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8, !llvm.access.group [[ACC_GRP2]]
2169 // CHECK10-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 4
2170 // CHECK10-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8, !llvm.access.group [[ACC_GRP2]]
2171 // CHECK10-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 5
2172 // CHECK10-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[G]], align 8, !llvm.access.group [[ACC_GRP2]]
2173 // CHECK10-NEXT: store volatile double [[TMP4]], ptr [[BLOCK_CAPTURED]], align 8, !llvm.access.group [[ACC_GRP2]]
2174 // CHECK10-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK]], i32 0, i32 6
2175 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
2176 // CHECK10-NEXT: store i32 [[TMP5]], ptr [[BLOCK_CAPTURED2]], align 8, !llvm.access.group [[ACC_GRP2]]
2177 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
2178 // CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !llvm.access.group [[ACC_GRP2]]
2179 // CHECK10-NEXT: call void [[TMP7]](ptr noundef [[BLOCK]]), !llvm.access.group [[ACC_GRP2]]
2180 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2181 // CHECK10: omp.body.continue:
2182 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2183 // CHECK10: omp.inner.for.inc:
2184 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2185 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2186 // CHECK10-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2187 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2188 // CHECK10: omp.inner.for.end:
2189 // CHECK10-NEXT: store i32 10, ptr [[I]], align 4
2190 // CHECK10-NEXT: [[TMP9:%.*]] = load double, ptr [[G]], align 8
2191 // CHECK10-NEXT: store volatile double [[TMP9]], ptr @g, align 8
2192 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR]], align 4
2193 // CHECK10-NEXT: store i32 [[TMP10]], ptr @_ZZ4mainE5sivar, align 4
2194 // CHECK10-NEXT: ret void
2195 //
2196 //
2197 // CHECK10-LABEL: define {{[^@]+}}@__main_block_invoke_2
2198 // CHECK10-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
2199 // CHECK10-NEXT: entry:
2200 // CHECK10-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
2201 // CHECK10-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
2202 // CHECK10-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2203 // CHECK10-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
2204 // CHECK10-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
2205 // CHECK10-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8
2206 // CHECK10-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6
2207 // CHECK10-NEXT: store i32 22, ptr [[BLOCK_CAPTURE_ADDR1]], align 8
2208 // CHECK10-NEXT: ret void
2209 //
2210 //
2211 // CHECK11-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
2212 // CHECK11-SAME: (i32 noundef [[N:%.*]], ptr noundef [[A:%.*]], ptr noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
2213 // CHECK11-NEXT: entry:
2214 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2215 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
2216 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
2217 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
2218 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2219 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2220 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2221 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
2222 // CHECK11-NEXT: [[A1:%.*]] = alloca ptr, align 8
2223 // CHECK11-NEXT: [[S2:%.*]] = alloca ptr, align 8
2224 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
2225 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
2226 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
2227 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2228 // CHECK11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2229 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
2230 // CHECK11-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
2231 // CHECK11-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2232 // CHECK11-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32
2233 // CHECK11-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2234 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2235 // CHECK11: omp.inner.for.cond:
2236 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
2237 // CHECK11-NEXT: [[CONV3:%.*]] = sext i32 [[TMP3]] to i64
2238 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
2239 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP4]]
2240 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2241 // CHECK11: omp.inner.for.body:
2242 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2243 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
2244 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2245 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2246 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2247 // CHECK11: omp.body.continue:
2248 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2249 // CHECK11: omp.inner.for.inc:
2250 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2251 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
2252 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2253 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2254 // CHECK11: omp.inner.for.end:
2255 // CHECK11-NEXT: store i32 10, ptr [[I]], align 4
2256 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[A1]], align 8
2257 // CHECK11-NEXT: store ptr [[TMP7]], ptr [[A_ADDR]], align 8
2258 // CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[S2]], align 8
2259 // CHECK11-NEXT: store ptr [[TMP8]], ptr [[S_ADDR]], align 8
2260 // CHECK11-NEXT: ret void
2261 //
2262 //
2263 // CHECK12-LABEL: define {{[^@]+}}@_Z4loopv
2264 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
2265 // CHECK12-NEXT: entry:
2266 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
2267 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4
2268 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
2269 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
2270 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
2271 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2272 // CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
2273 // CHECK12-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
2274 // CHECK12-NEXT: [[I2:%.*]] = alloca i32, align 4
2275 // CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4
2276 // CHECK12-NEXT: [[J4:%.*]] = alloca i32, align 4
2277 // CHECK12-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
2278 // CHECK12-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8
2279 // CHECK12-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2280 // CHECK12-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2281 // CHECK12-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
2282 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4
2283 // CHECK12-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START]], align 4
2284 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr [[J]], align 4
2285 // CHECK12-NEXT: store i32 [[TMP2]], ptr [[DOTLINEAR_START1]], align 4
2286 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2287 // CHECK12: omp.inner.for.cond:
2288 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
2289 // CHECK12-NEXT: [[CONV5:%.*]] = sext i32 [[TMP3]] to i64
2290 // CHECK12-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
2291 // CHECK12-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV5]], [[TMP4]]
2292 // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2293 // CHECK12: omp.inner.for.body:
2294 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2295 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
2296 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2297 // CHECK12-NEXT: store i32 [[ADD]], ptr [[I2]], align 4, !llvm.access.group [[ACC_GRP2]]
2298 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP2]]
2299 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2300 // CHECK12-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP7]], 1
2301 // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP6]], [[MUL6]]
2302 // CHECK12-NEXT: store i32 [[ADD7]], ptr [[J4]], align 4, !llvm.access.group [[ACC_GRP2]]
2303 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[J4]], align 4, !llvm.access.group [[ACC_GRP2]]
2304 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
2305 // CHECK12-NEXT: store i32 [[INC]], ptr [[J4]], align 4, !llvm.access.group [[ACC_GRP2]]
2306 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2307 // CHECK12: omp.body.continue:
2308 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2309 // CHECK12: omp.inner.for.inc:
2310 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2311 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP9]], 1
2312 // CHECK12-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2313 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2314 // CHECK12: omp.inner.for.end:
2315 // CHECK12-NEXT: store i32 10, ptr [[I]], align 4
2316 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, ptr [[J4]], align 4
2317 // CHECK12-NEXT: store i32 [[TMP10]], ptr [[J]], align 4
2318 // CHECK12-NEXT: ret void
2319 //
LLVM monorepo