clang/test/OpenMP/sections_reduction_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
   7
   8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
   9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
  10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // expected-no-diagnostics
  14 #ifndef HEADER
  15 #define HEADER
  16
  17 volatile double g;
  18
  19 template <class T>
  20 struct S {
  21   T f;
  22   S(T a) : f(a + g) {}
  23   S() : f(g) {}
  24   operator T() { return T(); }
  25   S &operator&(const S &) { return *this; }
  26   ~S() {}
  27 };
  28
  29
  30 template <typename T>
  31 T tmain() {
  32   T t;
  33   S<T> test;
  34   T t_var = T(), t_var1;
  35   T vec[] = {1, 2};
  36   S<T> s_arr[] = {1, 2};
  37   S<T> var(3), var1;
  38 #pragma omp parallel
  39 #pragma omp sections reduction(+:t_var) reduction(&:var) reduction(&& : var1) reduction(min: t_var1) nowait
  40   {
  41     vec[0] = t_var;
  42 #pragma omp section
  43     s_arr[0] = var;
  44   }
  45   return T();
  46 }
  47
  48 int main() {
  49 #ifdef LAMBDA
  50   [&]() {
  51 #pragma omp parallel
  52 #pragma omp sections reduction(+:g)
  53     {
  54
  55     // Reduction list for runtime.
  56
  57     g = 1;
  58
  59 #pragma omp section
  60     [&]() {
  61       g = 2;
  62     }();
  63   }
  64   }();
  65   return 0;
  66 #elif defined(BLOCKS)
  67   ^{
  68 #pragma omp parallel
  69 #pragma omp sections reduction(-:g)
  70     {
  71
  72     // Reduction list for runtime.
  73
  74     g = 1;
  75
  76 #pragma omp section
  77     ^{
  78       g = 2;
  79     }();
  80   }
  81   }();
  82   return 0;
  83 #else
  84   S<float> test;
  85   float t_var = 0, t_var1;
  86   int vec[] = {1, 2};
  87   S<float> s_arr[] = {1, 2};
  88   S<float> var(3), var1;
  89 #pragma omp parallel
  90 #pragma omp sections reduction(+:t_var) reduction(&:var) reduction(&& : var1) reduction(min: t_var1)
  91   {
  92     {
  93     vec[0] = t_var;
  94     s_arr[0] = var;
  95     vec[1] = t_var1;
  96     s_arr[1] = var1;
  97     }
  98   }
  99   return tmain<int>();
 100 #endif
 101 }
 102
 103
 104
 105
 106
 107
 108
 109
 110
 111 // Reduction list for runtime.
 112
 113
 114
 115 // For + reduction operation initial value of private variable is 0.
 116
 117 // For & reduction operation initial value of private variable is ones in all bits.
 118
 119 // For && reduction operation initial value of private variable is 1.0.
 120
 121 // For min reduction operation initial value of private variable is largest repesentable value.
 122
 123 // Skip checks for internal operations.
 124
 125 // ptr RedList[<n>] = {<ReductionVars>[0], ..., <ReductionVars>[<n>-1]};
 126
 127
 128 // res = __kmpc_reduce_nowait(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>);
 129
 130
 131 // switch(res)
 132
 133 // case 1:
 134 // t_var += t_var_reduction;
 135
 136 // var = var.operator &(var_reduction);
 137
 138 // var1 = var1.operator &&(var1_reduction);
 139
 140 // t_var1 = min(t_var1, t_var1_reduction);
 141
 142 // __kmpc_end_reduce_nowait(<loc>, <gtid>, &<lock>);
 143
 144 // break;
 145
 146 // case 2:
 147 // t_var += t_var_reduction;
 148
 149 // var = var.operator &(var_reduction);
 150
 151 // var1 = var1.operator &&(var1_reduction);
 152
 153 // t_var1 = min(t_var1, t_var1_reduction);
 154
 155 // break;
 156
 157 // void reduce_func(ptr lhs[<n>], ptr rhs[<n>]) {
 158 //  *(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
 159 //  ...
 160 //  *(Type<n>-1*)lhs[<n>-1] = ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
 161 //  *(Type<n>-1*)rhs[<n>-1]);
 162 // }
 163 // t_var_lhs = (iptr)lhs[0];
 164 // t_var_rhs = (iptr)rhs[0];
 165
 166 // var_lhs = (Sptr)lhs[1];
 167 // var_rhs = (Sptr)rhs[1];
 168
 169 // var1_lhs = (Sptr)lhs[2];
 170 // var1_rhs = (Sptr)rhs[2];
 171
 172 // t_var1_lhs = (iptr)lhs[3];
 173 // t_var1_rhs = (iptr)rhs[3];
 174
 175 // t_var_lhs += t_var_rhs;
 176
 177 // var_lhs = var_lhs.operator &(var_rhs);
 178
 179 // var1_lhs = var1_lhs.operator &&(var1_rhs);
 180
 181 // t_var1_lhs = min(t_var1_lhs, t_var1_rhs);
 182
 183 #endif
 184 // CHECK1-LABEL: define {{[^@]+}}@main
 185 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 186 // CHECK1-NEXT:  entry:
 187 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 188 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 189 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca float, align 4
 190 // CHECK1-NEXT:    [[T_VAR1:%.*]] = alloca float, align 4
 191 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 192 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 193 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S]], align 4
 194 // CHECK1-NEXT:    [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4
 195 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 196 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 197 // CHECK1-NEXT:    store float 0.000000e+00, ptr [[T_VAR]], align 4
 198 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
 199 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], float noundef 1.000000e+00)
 200 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1
 201 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
 202 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00)
 203 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]])
 204 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[VAR]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]])
 205 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 206 // CHECK1-NEXT:    store i32 [[CALL]], ptr [[RETVAL]], align 4
 207 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]]
 208 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
 209 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 210 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 211 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 212 // CHECK1:       arraydestroy.body:
 213 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 214 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 215 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 216 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 217 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 218 // CHECK1:       arraydestroy.done1:
 219 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 220 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
 221 // CHECK1-NEXT:    ret i32 [[TMP1]]
 222 //
 223 //
 224 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 225 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
 226 // CHECK1-NEXT:  entry:
 227 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 228 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 229 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 230 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 231 // CHECK1-NEXT:    ret void
 232 //
 233 //
 234 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 235 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 236 // CHECK1-NEXT:  entry:
 237 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 238 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 239 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 240 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 241 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 242 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 243 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 244 // CHECK1-NEXT:    ret void
 245 //
 246 //
 247 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined
 248 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3:[0-9]+]] {
 249 // CHECK1-NEXT:  entry:
 250 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 251 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 252 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
 253 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 254 // CHECK1-NEXT:    [[VAR1_ADDR:%.*]] = alloca ptr, align 8
 255 // CHECK1-NEXT:    [[T_VAR1_ADDR:%.*]] = alloca ptr, align 8
 256 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 257 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 258 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4
 259 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4
 260 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4
 261 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4
 262 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4
 263 // CHECK1-NEXT:    [[T_VAR2:%.*]] = alloca float, align 4
 264 // CHECK1-NEXT:    [[VAR3:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 265 // CHECK1-NEXT:    [[VAR14:%.*]] = alloca [[STRUCT_S]], align 4
 266 // CHECK1-NEXT:    [[T_VAR15:%.*]] = alloca float, align 4
 267 // CHECK1-NEXT:    [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x ptr], align 8
 268 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
 269 // CHECK1-NEXT:    [[REF_TMP16:%.*]] = alloca [[STRUCT_S]], align 4
 270 // CHECK1-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca float, align 4
 271 // CHECK1-NEXT:    [[TMP:%.*]] = alloca float, align 4
 272 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 273 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 274 // CHECK1-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 275 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 276 // CHECK1-NEXT:    store ptr [[VAR1]], ptr [[VAR1_ADDR]], align 8
 277 // CHECK1-NEXT:    store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8
 278 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 279 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 280 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
 281 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 282 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8
 283 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8
 284 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 285 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 286 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4
 287 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 288 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4
 289 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4
 290 // CHECK1-NEXT:    store float 0.000000e+00, ptr [[T_VAR2]], align 4
 291 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
 292 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
 293 // CHECK1-NEXT:    store float 0x47EFFFFFE0000000, ptr [[T_VAR15]], align 4
 294 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 295 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
 296 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
 297 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 298 // CHECK1-NEXT:    [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0
 299 // CHECK1-NEXT:    [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP8]], i32 0
 300 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_SECTIONS_UB_]], align 4
 301 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4
 302 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
 303 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 304 // CHECK1:       omp.inner.for.cond:
 305 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 306 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 307 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
 308 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 309 // CHECK1:       omp.inner.for.body:
 310 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 311 // CHECK1-NEXT:    switch i32 [[TMP14]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [
 312 // CHECK1-NEXT:      i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]
 313 // CHECK1-NEXT:    ]
 314 // CHECK1:       .omp.sections.case:
 315 // CHECK1-NEXT:    [[TMP15:%.*]] = load float, ptr [[T_VAR2]], align 4
 316 // CHECK1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP15]] to i32
 317 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 0
 318 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[ARRAYIDX]], align 4
 319 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 0
 320 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false)
 321 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[T_VAR15]], align 4
 322 // CHECK1-NEXT:    [[CONV7:%.*]] = fptosi float [[TMP16]] to i32
 323 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 1
 324 // CHECK1-NEXT:    store i32 [[CONV7]], ptr [[ARRAYIDX8]], align 4
 325 // CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 1
 326 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR14]], i64 4, i1 false)
 327 // CHECK1-NEXT:    br label [[DOTOMP_SECTIONS_EXIT]]
 328 // CHECK1:       .omp.sections.exit:
 329 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 330 // CHECK1:       omp.inner.for.inc:
 331 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 332 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP17]], 1
 333 // CHECK1-NEXT:    store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
 334 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 335 // CHECK1:       omp.inner.for.end:
 336 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP7]])
 337 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
 338 // CHECK1-NEXT:    store ptr [[T_VAR2]], ptr [[TMP18]], align 8
 339 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1
 340 // CHECK1-NEXT:    store ptr [[VAR3]], ptr [[TMP19]], align 8
 341 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2
 342 // CHECK1-NEXT:    store ptr [[VAR14]], ptr [[TMP20]], align 8
 343 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3
 344 // CHECK1-NEXT:    store ptr [[T_VAR15]], ptr [[TMP21]], align 8
 345 // CHECK1-NEXT:    [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 4, i64 32, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @main.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)
 346 // CHECK1-NEXT:    switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
 347 // CHECK1-NEXT:      i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
 348 // CHECK1-NEXT:      i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
 349 // CHECK1-NEXT:    ]
 350 // CHECK1:       .omp.reduction.case1:
 351 // CHECK1-NEXT:    [[TMP23:%.*]] = load float, ptr [[TMP0]], align 4
 352 // CHECK1-NEXT:    [[TMP24:%.*]] = load float, ptr [[T_VAR2]], align 4
 353 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP23]], [[TMP24]]
 354 // CHECK1-NEXT:    store float [[ADD]], ptr [[TMP0]], align 4
 355 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
 356 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL]], i64 4, i1 false)
 357 // CHECK1-NEXT:    [[CALL10:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
 358 // CHECK1-NEXT:    [[TOBOOL:%.*]] = fcmp une float [[CALL10]], 0.000000e+00
 359 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
 360 // CHECK1:       land.rhs:
 361 // CHECK1-NEXT:    [[CALL11:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
 362 // CHECK1-NEXT:    [[TOBOOL12:%.*]] = fcmp une float [[CALL11]], 0.000000e+00
 363 // CHECK1-NEXT:    br label [[LAND_END]]
 364 // CHECK1:       land.end:
 365 // CHECK1-NEXT:    [[TMP25:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL12]], [[LAND_RHS]] ]
 366 // CHECK1-NEXT:    [[CONV13:%.*]] = uitofp i1 [[TMP25]] to float
 367 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV13]])
 368 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
 369 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
 370 // CHECK1-NEXT:    [[TMP26:%.*]] = load float, ptr [[TMP3]], align 4
 371 // CHECK1-NEXT:    [[TMP27:%.*]] = load float, ptr [[T_VAR15]], align 4
 372 // CHECK1-NEXT:    [[CMP14:%.*]] = fcmp olt float [[TMP26]], [[TMP27]]
 373 // CHECK1-NEXT:    br i1 [[CMP14]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 374 // CHECK1:       cond.true:
 375 // CHECK1-NEXT:    [[TMP28:%.*]] = load float, ptr [[TMP3]], align 4
 376 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 377 // CHECK1:       cond.false:
 378 // CHECK1-NEXT:    [[TMP29:%.*]] = load float, ptr [[T_VAR15]], align 4
 379 // CHECK1-NEXT:    br label [[COND_END]]
 380 // CHECK1:       cond.end:
 381 // CHECK1-NEXT:    [[COND:%.*]] = phi float [ [[TMP28]], [[COND_TRUE]] ], [ [[TMP29]], [[COND_FALSE]] ]
 382 // CHECK1-NEXT:    store float [[COND]], ptr [[TMP3]], align 4
 383 // CHECK1-NEXT:    call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP7]], ptr @.gomp_critical_user_.reduction.var)
 384 // CHECK1-NEXT:    br label [[DOTOMP_REDUCTION_DEFAULT]]
 385 // CHECK1:       .omp.reduction.case2:
 386 // CHECK1-NEXT:    [[TMP30:%.*]] = load float, ptr [[T_VAR2]], align 4
 387 // CHECK1-NEXT:    [[TMP31:%.*]] = atomicrmw fadd ptr [[TMP0]], float [[TMP30]] monotonic, align 4
 388 // CHECK1-NEXT:    call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 389 // CHECK1-NEXT:    [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
 390 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL15]], i64 4, i1 false)
 391 // CHECK1-NEXT:    call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 392 // CHECK1-NEXT:    call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 393 // CHECK1-NEXT:    [[CALL17:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
 394 // CHECK1-NEXT:    [[TOBOOL18:%.*]] = fcmp une float [[CALL17]], 0.000000e+00
 395 // CHECK1-NEXT:    br i1 [[TOBOOL18]], label [[LAND_RHS19:%.*]], label [[LAND_END22:%.*]]
 396 // CHECK1:       land.rhs19:
 397 // CHECK1-NEXT:    [[CALL20:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
 398 // CHECK1-NEXT:    [[TOBOOL21:%.*]] = fcmp une float [[CALL20]], 0.000000e+00
 399 // CHECK1-NEXT:    br label [[LAND_END22]]
 400 // CHECK1:       land.end22:
 401 // CHECK1-NEXT:    [[TMP32:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL21]], [[LAND_RHS19]] ]
 402 // CHECK1-NEXT:    [[CONV23:%.*]] = uitofp i1 [[TMP32]] to float
 403 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP16]], float noundef [[CONV23]])
 404 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP16]], i64 4, i1 false)
 405 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR4]]
 406 // CHECK1-NEXT:    call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 407 // CHECK1-NEXT:    [[TMP33:%.*]] = load float, ptr [[T_VAR15]], align 4
 408 // CHECK1-NEXT:    [[ATOMIC_LOAD:%.*]] = load atomic i32, ptr [[TMP3]] monotonic, align 4
 409 // CHECK1-NEXT:    br label [[ATOMIC_CONT:%.*]]
 410 // CHECK1:       atomic_cont:
 411 // CHECK1-NEXT:    [[TMP34:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[LAND_END22]] ], [ [[TMP42:%.*]], [[COND_END27:%.*]] ]
 412 // CHECK1-NEXT:    [[TMP35:%.*]] = bitcast i32 [[TMP34]] to float
 413 // CHECK1-NEXT:    store float [[TMP35]], ptr [[TMP]], align 4
 414 // CHECK1-NEXT:    [[TMP36:%.*]] = load float, ptr [[TMP]], align 4
 415 // CHECK1-NEXT:    [[TMP37:%.*]] = load float, ptr [[T_VAR15]], align 4
 416 // CHECK1-NEXT:    [[CMP24:%.*]] = fcmp olt float [[TMP36]], [[TMP37]]
 417 // CHECK1-NEXT:    br i1 [[CMP24]], label [[COND_TRUE25:%.*]], label [[COND_FALSE26:%.*]]
 418 // CHECK1:       cond.true25:
 419 // CHECK1-NEXT:    [[TMP38:%.*]] = load float, ptr [[TMP]], align 4
 420 // CHECK1-NEXT:    br label [[COND_END27]]
 421 // CHECK1:       cond.false26:
 422 // CHECK1-NEXT:    [[TMP39:%.*]] = load float, ptr [[T_VAR15]], align 4
 423 // CHECK1-NEXT:    br label [[COND_END27]]
 424 // CHECK1:       cond.end27:
 425 // CHECK1-NEXT:    [[COND28:%.*]] = phi float [ [[TMP38]], [[COND_TRUE25]] ], [ [[TMP39]], [[COND_FALSE26]] ]
 426 // CHECK1-NEXT:    store float [[COND28]], ptr [[ATOMIC_TEMP]], align 4
 427 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4
 428 // CHECK1-NEXT:    [[TMP41:%.*]] = cmpxchg ptr [[TMP3]], i32 [[TMP34]], i32 [[TMP40]] monotonic monotonic, align 4
 429 // CHECK1-NEXT:    [[TMP42]] = extractvalue { i32, i1 } [[TMP41]], 0
 430 // CHECK1-NEXT:    [[TMP43:%.*]] = extractvalue { i32, i1 } [[TMP41]], 1
 431 // CHECK1-NEXT:    br i1 [[TMP43]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
 432 // CHECK1:       atomic_exit:
 433 // CHECK1-NEXT:    call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP7]], ptr @.gomp_critical_user_.reduction.var)
 434 // CHECK1-NEXT:    br label [[DOTOMP_REDUCTION_DEFAULT]]
 435 // CHECK1:       .omp.reduction.default:
 436 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]]
 437 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]]
 438 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP7]])
 439 // CHECK1-NEXT:    ret void
 440 //
 441 //
 442 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.omp.reduction.reduction_func
 443 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
 444 // CHECK1-NEXT:  entry:
 445 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 446 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 447 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 448 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 449 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 450 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 451 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 452 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 0
 453 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
 454 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 0
 455 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 456 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 1
 457 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
 458 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 1
 459 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
 460 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 2
 461 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
 462 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 2
 463 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8
 464 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 3
 465 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
 466 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 3
 467 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
 468 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[TMP7]], align 4
 469 // CHECK1-NEXT:    [[TMP21:%.*]] = load float, ptr [[TMP5]], align 4
 470 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP20]], [[TMP21]]
 471 // CHECK1-NEXT:    store float [[ADD]], ptr [[TMP7]], align 4
 472 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP11]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]])
 473 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP11]], ptr align 4 [[CALL]], i64 4, i1 false)
 474 // CHECK1-NEXT:    [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]])
 475 // CHECK1-NEXT:    [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00
 476 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
 477 // CHECK1:       land.rhs:
 478 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])
 479 // CHECK1-NEXT:    [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00
 480 // CHECK1-NEXT:    br label [[LAND_END]]
 481 // CHECK1:       land.end:
 482 // CHECK1-NEXT:    [[TMP22:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ]
 483 // CHECK1-NEXT:    [[CONV:%.*]] = uitofp i1 [[TMP22]] to float
 484 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV]])
 485 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
 486 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
 487 // CHECK1-NEXT:    [[TMP23:%.*]] = load float, ptr [[TMP19]], align 4
 488 // CHECK1-NEXT:    [[TMP24:%.*]] = load float, ptr [[TMP17]], align 4
 489 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp olt float [[TMP23]], [[TMP24]]
 490 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 491 // CHECK1:       cond.true:
 492 // CHECK1-NEXT:    [[TMP25:%.*]] = load float, ptr [[TMP19]], align 4
 493 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 494 // CHECK1:       cond.false:
 495 // CHECK1-NEXT:    [[TMP26:%.*]] = load float, ptr [[TMP17]], align 4
 496 // CHECK1-NEXT:    br label [[COND_END]]
 497 // CHECK1:       cond.end:
 498 // CHECK1-NEXT:    [[COND:%.*]] = phi float [ [[TMP25]], [[COND_TRUE]] ], [ [[TMP26]], [[COND_FALSE]] ]
 499 // CHECK1-NEXT:    store float [[COND]], ptr [[TMP19]], align 4
 500 // CHECK1-NEXT:    ret void
 501 //
 502 //
 503 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_
 504 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] align 2 {
 505 // CHECK1-NEXT:  entry:
 506 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 507 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 508 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 509 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 510 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 511 // CHECK1-NEXT:    ret ptr [[THIS1]]
 512 //
 513 //
 514 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv
 515 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR1]] align 2 {
 516 // CHECK1-NEXT:  entry:
 517 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 518 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 519 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 520 // CHECK1-NEXT:    ret float 0.000000e+00
 521 //
 522 //
 523 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 524 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 525 // CHECK1-NEXT:  entry:
 526 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 527 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 528 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 529 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
 530 // CHECK1-NEXT:    ret void
 531 //
 532 //
 533 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 534 // CHECK1-SAME: () #[[ATTR1]] {
 535 // CHECK1-NEXT:  entry:
 536 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 537 // CHECK1-NEXT:    [[T:%.*]] = alloca i32, align 4
 538 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 539 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 540 // CHECK1-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
 541 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 542 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 543 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
 544 // CHECK1-NEXT:    [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4
 545 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 546 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 547 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 548 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[S_ARR]], i32 noundef 1)
 549 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1
 550 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
 551 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
 552 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]])
 553 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VAR]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]])
 554 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 555 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]]
 556 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
 557 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 558 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 559 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 560 // CHECK1:       arraydestroy.body:
 561 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 562 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 563 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
 564 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 565 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 566 // CHECK1:       arraydestroy.done1:
 567 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
 568 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
 569 // CHECK1-NEXT:    ret i32 [[TMP1]]
 570 //
 571 //
 572 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 573 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 574 // CHECK1-NEXT:  entry:
 575 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 576 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 577 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 578 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 579 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile double, ptr @g, align 8
 580 // CHECK1-NEXT:    [[CONV:%.*]] = fptrunc double [[TMP0]] to float
 581 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 582 // CHECK1-NEXT:    ret void
 583 //
 584 //
 585 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 586 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 587 // CHECK1-NEXT:  entry:
 588 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 589 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 590 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 591 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 592 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 593 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 594 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 595 // CHECK1-NEXT:    [[CONV:%.*]] = fpext float [[TMP0]] to double
 596 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile double, ptr @g, align 8
 597 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]]
 598 // CHECK1-NEXT:    [[CONV2:%.*]] = fptrunc double [[ADD]] to float
 599 // CHECK1-NEXT:    store float [[CONV2]], ptr [[F]], align 4
 600 // CHECK1-NEXT:    ret void
 601 //
 602 //
 603 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 604 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 605 // CHECK1-NEXT:  entry:
 606 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 607 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 608 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 609 // CHECK1-NEXT:    ret void
 610 //
 611 //
 612 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 613 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 614 // CHECK1-NEXT:  entry:
 615 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 616 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 617 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 618 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 619 // CHECK1-NEXT:    ret void
 620 //
 621 //
 622 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 623 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 624 // CHECK1-NEXT:  entry:
 625 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 626 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 627 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 628 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 629 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 630 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 631 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
 632 // CHECK1-NEXT:    ret void
 633 //
 634 //
 635 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
 636 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3]] {
 637 // CHECK1-NEXT:  entry:
 638 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 639 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 640 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
 641 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 642 // CHECK1-NEXT:    [[VAR1_ADDR:%.*]] = alloca ptr, align 8
 643 // CHECK1-NEXT:    [[T_VAR1_ADDR:%.*]] = alloca ptr, align 8
 644 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 645 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 646 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4
 647 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4
 648 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4
 649 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4
 650 // CHECK1-NEXT:    [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4
 651 // CHECK1-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
 652 // CHECK1-NEXT:    [[VAR3:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 653 // CHECK1-NEXT:    [[VAR14:%.*]] = alloca [[STRUCT_S_0]], align 4
 654 // CHECK1-NEXT:    [[T_VAR15:%.*]] = alloca i32, align 4
 655 // CHECK1-NEXT:    [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x ptr], align 8
 656 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
 657 // CHECK1-NEXT:    [[REF_TMP13:%.*]] = alloca [[STRUCT_S_0]], align 4
 658 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 659 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 660 // CHECK1-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 661 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 662 // CHECK1-NEXT:    store ptr [[VAR1]], ptr [[VAR1_ADDR]], align 8
 663 // CHECK1-NEXT:    store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8
 664 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 665 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 666 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
 667 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 668 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8
 669 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8
 670 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 671 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 672 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4
 673 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 674 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4
 675 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4
 676 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR2]], align 4
 677 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
 678 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
 679 // CHECK1-NEXT:    store i32 2147483647, ptr [[T_VAR15]], align 4
 680 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 681 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
 682 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
 683 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 684 // CHECK1-NEXT:    [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 1
 685 // CHECK1-NEXT:    [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP8]], i32 1
 686 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_SECTIONS_UB_]], align 4
 687 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4
 688 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
 689 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 690 // CHECK1:       omp.inner.for.cond:
 691 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 692 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 693 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
 694 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 695 // CHECK1:       omp.inner.for.body:
 696 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 697 // CHECK1-NEXT:    switch i32 [[TMP14]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [
 698 // CHECK1-NEXT:      i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]
 699 // CHECK1-NEXT:      i32 1, label [[DOTOMP_SECTIONS_CASE6:%.*]]
 700 // CHECK1-NEXT:    ]
 701 // CHECK1:       .omp.sections.case:
 702 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4
 703 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 0
 704 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4
 705 // CHECK1-NEXT:    br label [[DOTOMP_SECTIONS_EXIT]]
 706 // CHECK1:       .omp.sections.case6:
 707 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], i64 0, i64 0
 708 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR3]], i64 4, i1 false)
 709 // CHECK1-NEXT:    br label [[DOTOMP_SECTIONS_EXIT]]
 710 // CHECK1:       .omp.sections.exit:
 711 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 712 // CHECK1:       omp.inner.for.inc:
 713 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 714 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP16]], 1
 715 // CHECK1-NEXT:    store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
 716 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 717 // CHECK1:       omp.inner.for.end:
 718 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP7]])
 719 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
 720 // CHECK1-NEXT:    store ptr [[T_VAR2]], ptr [[TMP17]], align 8
 721 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1
 722 // CHECK1-NEXT:    store ptr [[VAR3]], ptr [[TMP18]], align 8
 723 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2
 724 // CHECK1-NEXT:    store ptr [[VAR14]], ptr [[TMP19]], align 8
 725 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3
 726 // CHECK1-NEXT:    store ptr [[T_VAR15]], ptr [[TMP20]], align 8
 727 // CHECK1-NEXT:    [[TMP21:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP7]], i32 4, i64 32, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z5tmainIiET_v.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)
 728 // CHECK1-NEXT:    switch i32 [[TMP21]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
 729 // CHECK1-NEXT:      i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
 730 // CHECK1-NEXT:      i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
 731 // CHECK1-NEXT:    ]
 732 // CHECK1:       .omp.reduction.case1:
 733 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP0]], align 4
 734 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4
 735 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
 736 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[TMP0]], align 4
 737 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
 738 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL]], i64 4, i1 false)
 739 // CHECK1-NEXT:    [[CALL8:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
 740 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[CALL8]], 0
 741 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
 742 // CHECK1:       land.rhs:
 743 // CHECK1-NEXT:    [[CALL9:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
 744 // CHECK1-NEXT:    [[TOBOOL10:%.*]] = icmp ne i32 [[CALL9]], 0
 745 // CHECK1-NEXT:    br label [[LAND_END]]
 746 // CHECK1:       land.end:
 747 // CHECK1-NEXT:    [[TMP24:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL10]], [[LAND_RHS]] ]
 748 // CHECK1-NEXT:    [[CONV:%.*]] = zext i1 [[TMP24]] to i32
 749 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]])
 750 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
 751 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
 752 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP3]], align 4
 753 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[T_VAR15]], align 4
 754 // CHECK1-NEXT:    [[CMP11:%.*]] = icmp slt i32 [[TMP25]], [[TMP26]]
 755 // CHECK1-NEXT:    br i1 [[CMP11]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 756 // CHECK1:       cond.true:
 757 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[TMP3]], align 4
 758 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 759 // CHECK1:       cond.false:
 760 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[T_VAR15]], align 4
 761 // CHECK1-NEXT:    br label [[COND_END]]
 762 // CHECK1:       cond.end:
 763 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP27]], [[COND_TRUE]] ], [ [[TMP28]], [[COND_FALSE]] ]
 764 // CHECK1-NEXT:    store i32 [[COND]], ptr [[TMP3]], align 4
 765 // CHECK1-NEXT:    call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP7]], ptr @.gomp_critical_user_.reduction.var)
 766 // CHECK1-NEXT:    br label [[DOTOMP_REDUCTION_DEFAULT]]
 767 // CHECK1:       .omp.reduction.case2:
 768 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[T_VAR2]], align 4
 769 // CHECK1-NEXT:    [[TMP30:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP29]] monotonic, align 4
 770 // CHECK1-NEXT:    call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 771 // CHECK1-NEXT:    [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
 772 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL12]], i64 4, i1 false)
 773 // CHECK1-NEXT:    call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 774 // CHECK1-NEXT:    call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 775 // CHECK1-NEXT:    [[CALL14:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
 776 // CHECK1-NEXT:    [[TOBOOL15:%.*]] = icmp ne i32 [[CALL14]], 0
 777 // CHECK1-NEXT:    br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]]
 778 // CHECK1:       land.rhs16:
 779 // CHECK1-NEXT:    [[CALL17:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
 780 // CHECK1-NEXT:    [[TOBOOL18:%.*]] = icmp ne i32 [[CALL17]], 0
 781 // CHECK1-NEXT:    br label [[LAND_END19]]
 782 // CHECK1:       land.end19:
 783 // CHECK1-NEXT:    [[TMP31:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ]
 784 // CHECK1-NEXT:    [[CONV20:%.*]] = zext i1 [[TMP31]] to i32
 785 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP13]], i32 noundef [[CONV20]])
 786 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP13]], i64 4, i1 false)
 787 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR4]]
 788 // CHECK1-NEXT:    call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
 789 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[T_VAR15]], align 4
 790 // CHECK1-NEXT:    [[TMP33:%.*]] = atomicrmw min ptr [[TMP3]], i32 [[TMP32]] monotonic, align 4
 791 // CHECK1-NEXT:    br label [[DOTOMP_REDUCTION_DEFAULT]]
 792 // CHECK1:       .omp.reduction.default:
 793 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]]
 794 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]]
 795 // CHECK1-NEXT:    ret void
 796 //
 797 //
 798 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.omp.reduction.reduction_func
 799 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR5]] {
 800 // CHECK1-NEXT:  entry:
 801 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 802 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 803 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 804 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 805 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 806 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 807 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 808 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 0
 809 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
 810 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 0
 811 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 812 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 1
 813 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8
 814 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 1
 815 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
 816 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 2
 817 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
 818 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 2
 819 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8
 820 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP3]], i64 0, i64 3
 821 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8
 822 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 3
 823 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
 824 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP7]], align 4
 825 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP5]], align 4
 826 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
 827 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[TMP7]], align 4
 828 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP11]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]])
 829 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP11]], ptr align 4 [[CALL]], i64 4, i1 false)
 830 // CHECK1-NEXT:    [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]])
 831 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0
 832 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
 833 // CHECK1:       land.rhs:
 834 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])
 835 // CHECK1-NEXT:    [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0
 836 // CHECK1-NEXT:    br label [[LAND_END]]
 837 // CHECK1:       land.end:
 838 // CHECK1-NEXT:    [[TMP22:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ]
 839 // CHECK1-NEXT:    [[CONV:%.*]] = zext i1 [[TMP22]] to i32
 840 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]])
 841 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
 842 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
 843 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP19]], align 4
 844 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP17]], align 4
 845 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]]
 846 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 847 // CHECK1:       cond.true:
 848 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP19]], align 4
 849 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 850 // CHECK1:       cond.false:
 851 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP17]], align 4
 852 // CHECK1-NEXT:    br label [[COND_END]]
 853 // CHECK1:       cond.end:
 854 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP25]], [[COND_TRUE]] ], [ [[TMP26]], [[COND_FALSE]] ]
 855 // CHECK1-NEXT:    store i32 [[COND]], ptr [[TMP19]], align 4
 856 // CHECK1-NEXT:    ret void
 857 //
 858 //
 859 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_
 860 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] align 2 {
 861 // CHECK1-NEXT:  entry:
 862 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 863 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 864 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 865 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 866 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 867 // CHECK1-NEXT:    ret ptr [[THIS1]]
 868 //
 869 //
 870 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv
 871 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR1]] align 2 {
 872 // CHECK1-NEXT:  entry:
 873 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 874 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 875 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 876 // CHECK1-NEXT:    ret i32 0
 877 //
 878 //
 879 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 880 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 881 // CHECK1-NEXT:  entry:
 882 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 883 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 884 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 885 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
 886 // CHECK1-NEXT:    ret void
 887 //
 888 //
 889 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 890 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 891 // CHECK1-NEXT:  entry:
 892 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 893 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 894 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 895 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 896 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile double, ptr @g, align 8
 897 // CHECK1-NEXT:    [[CONV:%.*]] = fptosi double [[TMP0]] to i32
 898 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[F]], align 4
 899 // CHECK1-NEXT:    ret void
 900 //
 901 //
 902 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 903 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 904 // CHECK1-NEXT:  entry:
 905 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 906 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 907 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 908 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 909 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 910 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 911 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 912 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to double
 913 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile double, ptr @g, align 8
 914 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]]
 915 // CHECK1-NEXT:    [[CONV2:%.*]] = fptosi double [[ADD]] to i32
 916 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[F]], align 4
 917 // CHECK1-NEXT:    ret void
 918 //
 919 //
 920 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 921 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
 922 // CHECK1-NEXT:  entry:
 923 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 924 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 925 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 926 // CHECK1-NEXT:    ret void
 927 //
 928 //
 929 // CHECK3-LABEL: define {{[^@]+}}@main
 930 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 931 // CHECK3-NEXT:  entry:
 932 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 933 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
 934 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 935 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
 936 // CHECK3-NEXT:    ret i32 0
 937 //
 938 //
 939 // CHECK4-LABEL: define {{[^@]+}}@main
 940 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] {
 941 // CHECK4-NEXT:  entry:
 942 // CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 943 // CHECK4-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 944 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
 945 // CHECK4-NEXT:    call void [[TMP0]](ptr noundef @__block_literal_global)
 946 // CHECK4-NEXT:    ret i32 0
 947 //
 948 //
 949 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
 950 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
 951 // CHECK4-NEXT:  entry:
 952 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
 953 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
 954 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
 955 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
 956 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)
 957 // CHECK4-NEXT:    ret void
 958 //
 959 //
 960 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
 961 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
 962 // CHECK4-NEXT:  entry:
 963 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 964 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 965 // CHECK4-NEXT:    [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4
 966 // CHECK4-NEXT:    [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4
 967 // CHECK4-NEXT:    [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4
 968 // CHECK4-NEXT:    [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4
 969 // CHECK4-NEXT:    [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4
 970 // CHECK4-NEXT:    [[G:%.*]] = alloca double, align 8
 971 // CHECK4-NEXT:    [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double }>, align 8
 972 // CHECK4-NEXT:    [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8
 973 // CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 974 // CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 975 // CHECK4-NEXT:    store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4
 976 // CHECK4-NEXT:    store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 977 // CHECK4-NEXT:    store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4
 978 // CHECK4-NEXT:    store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4
 979 // CHECK4-NEXT:    store double 0.000000e+00, ptr [[G]], align 8
 980 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 981 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 982 // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
 983 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 984 // CHECK4-NEXT:    [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1
 985 // CHECK4-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1
 986 // CHECK4-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_SECTIONS_UB_]], align 4
 987 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4
 988 // CHECK4-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
 989 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 990 // CHECK4:       omp.inner.for.cond:
 991 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 992 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
 993 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 994 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 995 // CHECK4:       omp.inner.for.body:
 996 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
 997 // CHECK4-NEXT:    switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [
 998 // CHECK4-NEXT:      i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]
 999 // CHECK4-NEXT:      i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]]
1000 // CHECK4-NEXT:    ]
1001 // CHECK4:       .omp.sections.case:
1002 // CHECK4-NEXT:    store double 1.000000e+00, ptr [[G]], align 8
1003 // CHECK4-NEXT:    br label [[DOTOMP_SECTIONS_EXIT]]
1004 // CHECK4:       .omp.sections.case1:
1005 // CHECK4-NEXT:    [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 0
1006 // CHECK4-NEXT:    store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8
1007 // CHECK4-NEXT:    [[BLOCK_FLAGS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 1
1008 // CHECK4-NEXT:    store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
1009 // CHECK4-NEXT:    [[BLOCK_RESERVED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 2
1010 // CHECK4-NEXT:    store i32 0, ptr [[BLOCK_RESERVED]], align 4
1011 // CHECK4-NEXT:    [[BLOCK_INVOKE:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 3
1012 // CHECK4-NEXT:    store ptr @_block_invoke, ptr [[BLOCK_INVOKE]], align 8
1013 // CHECK4-NEXT:    [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 4
1014 // CHECK4-NEXT:    store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8
1015 // CHECK4-NEXT:    [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 5
1016 // CHECK4-NEXT:    [[TMP9:%.*]] = load volatile double, ptr [[G]], align 8
1017 // CHECK4-NEXT:    store volatile double [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8
1018 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
1019 // CHECK4-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8
1020 // CHECK4-NEXT:    call void [[TMP11]](ptr noundef [[BLOCK]])
1021 // CHECK4-NEXT:    br label [[DOTOMP_SECTIONS_EXIT]]
1022 // CHECK4:       .omp.sections.exit:
1023 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1024 // CHECK4:       omp.inner.for.inc:
1025 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
1026 // CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP12]], 1
1027 // CHECK4-NEXT:    store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
1028 // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
1029 // CHECK4:       omp.inner.for.end:
1030 // CHECK4-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
1031 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
1032 // CHECK4-NEXT:    store ptr [[G]], ptr [[TMP13]], align 8
1033 // CHECK4-NEXT:    [[TMP14:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @__main_block_invoke.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)
1034 // CHECK4-NEXT:    switch i32 [[TMP14]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
1035 // CHECK4-NEXT:      i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
1036 // CHECK4-NEXT:      i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
1037 // CHECK4-NEXT:    ]
1038 // CHECK4:       .omp.reduction.case1:
1039 // CHECK4-NEXT:    [[TMP15:%.*]] = load double, ptr @g, align 8
1040 // CHECK4-NEXT:    [[TMP16:%.*]] = load double, ptr [[G]], align 8
1041 // CHECK4-NEXT:    [[ADD:%.*]] = fadd double [[TMP15]], [[TMP16]]
1042 // CHECK4-NEXT:    store double [[ADD]], ptr @g, align 8
1043 // CHECK4-NEXT:    call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP1]], ptr @.gomp_critical_user_.reduction.var)
1044 // CHECK4-NEXT:    br label [[DOTOMP_REDUCTION_DEFAULT]]
1045 // CHECK4:       .omp.reduction.case2:
1046 // CHECK4-NEXT:    [[TMP17:%.*]] = load double, ptr [[G]], align 8
1047 // CHECK4-NEXT:    [[TMP18:%.*]] = atomicrmw fadd ptr @g, double [[TMP17]] monotonic, align 8
1048 // CHECK4-NEXT:    call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP1]], ptr @.gomp_critical_user_.reduction.var)
1049 // CHECK4-NEXT:    br label [[DOTOMP_REDUCTION_DEFAULT]]
1050 // CHECK4:       .omp.reduction.default:
1051 // CHECK4-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP1]])
1052 // CHECK4-NEXT:    ret void
1053 //
1054 //
1055 // CHECK4-LABEL: define {{[^@]+}}@_block_invoke
1056 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
1057 // CHECK4-NEXT:  entry:
1058 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1059 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1060 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1061 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1062 // CHECK4-NEXT:    [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
1063 // CHECK4-NEXT:    store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8
1064 // CHECK4-NEXT:    ret void
1065 //
1066 //
1067 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined.omp.reduction.reduction_func
1068 // CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
1069 // CHECK4-NEXT:  entry:
1070 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1071 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1072 // CHECK4-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1073 // CHECK4-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1074 // CHECK4-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1075 // CHECK4-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1076 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0
1077 // CHECK4-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
1078 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0
1079 // CHECK4-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1080 // CHECK4-NEXT:    [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8
1081 // CHECK4-NEXT:    [[TMP9:%.*]] = load double, ptr [[TMP5]], align 8
1082 // CHECK4-NEXT:    [[ADD:%.*]] = fadd double [[TMP8]], [[TMP9]]
1083 // CHECK4-NEXT:    store double [[ADD]], ptr [[TMP7]], align 8
1084 // CHECK4-NEXT:    ret void
1085 //