clang/test/OpenMP/vla_crash.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp -x c -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3
   4 // RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
   5
   6 int a;
   7
   8 void foo(void) {
   9   int(*b)[a];
  10   int *(**c)[a];
  11 #pragma omp parallel if (0)
  12   b[0][0] = c[0][a][0][a];
  13 }
  14
  15
  16 void bar(int n, int *a) {
  17   // expected-warning@+1 {{incompatible pointer types initializing 'int (*)[n]' with an expression of type 'int **'}}
  18   int(*p)[n] = &a;
  19 #pragma omp parallel if(0)
  20   // expected-warning@+1 {{comparison of distinct pointer types ('int (*)[n]' and 'int **')}}
  21   if (p == &a) {
  22   }
  23 }
  24
  25 // CHECK1-LABEL: define {{[^@]+}}@foo
  26 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
  27 // CHECK1-NEXT:  entry:
  28 // CHECK1-NEXT:    [[B:%.*]] = alloca ptr, align 8
  29 // CHECK1-NEXT:    [[C:%.*]] = alloca ptr, align 8
  30 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  31 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
  32 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
  33 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr @a, align 4
  34 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
  35 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr @a, align 4
  36 // CHECK1-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
  37 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
  38 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
  39 // CHECK1-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
  40 // CHECK1-NEXT:    call void @foo.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]], ptr [[B]], i64 [[TMP4]], ptr [[C]]) #[[ATTR2:[0-9]+]]
  41 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
  42 // CHECK1-NEXT:    ret void
  43 //
  44 //
  45 // CHECK1-LABEL: define {{[^@]+}}@foo.omp_outlined
  46 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] {
  47 // CHECK1-NEXT:  entry:
  48 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
  49 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
  50 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
  51 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
  52 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
  53 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
  54 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
  55 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
  56 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
  57 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
  58 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
  59 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
  60 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
  61 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
  62 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
  63 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
  64 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8
  65 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP4]], i64 0
  66 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
  67 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr @a, align 4
  68 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
  69 // CHECK1-NEXT:    [[TMP7:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP2]]
  70 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds ptr, ptr [[TMP5]], i64 [[TMP7]]
  71 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds ptr, ptr [[ARRAYIDX3]], i64 0
  72 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX4]], align 8
  73 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr @a, align 4
  74 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64
  75 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[TMP8]], i64 [[IDXPROM5]]
  76 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4
  77 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8
  78 // CHECK1-NEXT:    [[TMP12:%.*]] = mul nsw i64 0, [[TMP0]]
  79 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[TMP11]], i64 [[TMP12]]
  80 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX7]], i64 0
  81 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX8]], align 4
  82 // CHECK1-NEXT:    ret void
  83 //
  84 //
  85 // CHECK1-LABEL: define {{[^@]+}}@bar
  86 // CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
  87 // CHECK1-NEXT:  entry:
  88 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
  89 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
  90 // CHECK1-NEXT:    [[P:%.*]] = alloca ptr, align 8
  91 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  92 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
  93 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
  94 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
  95 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
  96 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
  97 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
  98 // CHECK1-NEXT:    store ptr [[A_ADDR]], ptr [[P]], align 8
  99 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 100 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
 101 // CHECK1-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
 102 // CHECK1-NEXT:    call void @bar.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]], ptr [[P]], ptr [[A_ADDR]]) #[[ATTR2]]
 103 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 104 // CHECK1-NEXT:    ret void
 105 //
 106 //
 107 // CHECK1-LABEL: define {{[^@]+}}@bar.omp_outlined
 108 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[P:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {
 109 // CHECK1-NEXT:  entry:
 110 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 111 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 112 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
 113 // CHECK1-NEXT:    [[P_ADDR:%.*]] = alloca ptr, align 8
 114 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 115 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 116 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 117 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
 118 // CHECK1-NEXT:    store ptr [[P]], ptr [[P_ADDR]], align 8
 119 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 120 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
 121 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[P_ADDR]], align 8
 122 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 123 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP1]], align 8
 124 // CHECK1-NEXT:    [[CMP:%.*]] = icmp eq ptr [[TMP3]], [[TMP2]]
 125 // CHECK1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
 126 // CHECK1:       if.then:
 127 // CHECK1-NEXT:    br label [[IF_END]]
 128 // CHECK1:       if.end:
 129 // CHECK1-NEXT:    ret void
 130 //