clang/test/Sema/rvv-required-features.c

   1 // REQUIRES: riscv-registered-target
   2 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp \
   3 // RUN:     -target-feature +xsfvqmaccdod -target-feature +xsfvqmaccqoq %s -fsyntax-only -verify
   4
   5 // expected-no-diagnostics
   6
   7 #include <riscv_vector.h>
   8 #include <sifive_vector.h>
   9
  10 vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
  11   return __riscv_vloxei64(base, bindex, vl);
  12 }
  13
  14 void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) {
  15   __riscv_vsoxei64(base, bindex, value, vl);
  16 }
  17
  18 void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
  19   __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
  20 }
  21
  22 void test_xsfvqmaccdod(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
  23   __riscv_sf_vqmacc_2x8x2(vd, vs1, vs2, vl);
  24 }
  25
  26 void test_xsfvqmaccqoq(vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, size_t vl) {
  27   __riscv_sf_vqmacc_4x8x4(vd, vs1, vs2, vl);
  28 }