lld/COFF/Chunks.cpp

   1 //===- Chunks.cpp ---------------------------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "Chunks.h"
  10 #include "COFFLinkerContext.h"
  11 #include "InputFiles.h"
  12 #include "SymbolTable.h"
  13 #include "Symbols.h"
  14 #include "Writer.h"
  15 #include "llvm/ADT/STLExtras.h"
  16 #include "llvm/ADT/StringExtras.h"
  17 #include "llvm/ADT/Twine.h"
  18 #include "llvm/BinaryFormat/COFF.h"
  19 #include "llvm/Object/COFF.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/Support/Endian.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 #include <algorithm>
  24 #include <iterator>
  25
  26 using namespace llvm;
  27 using namespace llvm::object;
  28 using namespace llvm::support;
  29 using namespace llvm::support::endian;
  30 using namespace llvm::COFF;
  31 using llvm::support::ulittle32_t;
  32
  33 namespace lld::coff {
  34
  35 SectionChunk::SectionChunk(ObjFile *f, const coff_section *h, Kind k)
  36     : Chunk(k), file(f), header(h), repl(this) {
  37   // Initialize relocs.
  38   if (file)
  39     setRelocs(file->getCOFFObj()->getRelocations(header));
  40
  41   // Initialize sectionName.
  42   StringRef sectionName;
  43   if (file) {
  44     if (Expected<StringRef> e = file->getCOFFObj()->getSectionName(header))
  45       sectionName = *e;
  46   }
  47   sectionNameData = sectionName.data();
  48   sectionNameSize = sectionName.size();
  49
  50   setAlignment(header->getAlignment());
  51
  52   hasData = !(header->Characteristics & IMAGE_SCN_CNT_UNINITIALIZED_DATA);
  53
  54   // If linker GC is disabled, every chunk starts out alive.  If linker GC is
  55   // enabled, treat non-comdat sections as roots. Generally optimized object
  56   // files will be built with -ffunction-sections or /Gy, so most things worth
  57   // stripping will be in a comdat.
  58   if (file)
  59     live = !file->symtab.ctx.config.doGC || !isCOMDAT();
  60   else
  61     live = true;
  62 }
  63
  64 // SectionChunk is one of the most frequently allocated classes, so it is
  65 // important to keep it as compact as possible. As of this writing, the number
  66 // below is the size of this class on x64 platforms.
  67 static_assert(sizeof(SectionChunk) <= 88, "SectionChunk grew unexpectedly");
  68
  69 static void add16(uint8_t *p, int16_t v) { write16le(p, read16le(p) + v); }
  70 static void add32(uint8_t *p, int32_t v) { write32le(p, read32le(p) + v); }
  71 static void add64(uint8_t *p, int64_t v) { write64le(p, read64le(p) + v); }
  72 static void or16(uint8_t *p, uint16_t v) { write16le(p, read16le(p) | v); }
  73 static void or32(uint8_t *p, uint32_t v) { write32le(p, read32le(p) | v); }
  74
  75 // Verify that given sections are appropriate targets for SECREL
  76 // relocations. This check is relaxed because unfortunately debug
  77 // sections have section-relative relocations against absolute symbols.
  78 static bool checkSecRel(const SectionChunk *sec, OutputSection *os) {
  79   if (os)
  80     return true;
  81   if (sec->isCodeView())
  82     return false;
  83   error("SECREL relocation cannot be applied to absolute symbols");
  84   return false;
  85 }
  86
  87 static void applySecRel(const SectionChunk *sec, uint8_t *off,
  88                         OutputSection *os, uint64_t s) {
  89   if (!checkSecRel(sec, os))
  90     return;
  91   uint64_t secRel = s - os->getRVA();
  92   if (secRel > UINT32_MAX) {
  93     error("overflow in SECREL relocation in section: " + sec->getSectionName());
  94     return;
  95   }
  96   add32(off, secRel);
  97 }
  98
  99 static void applySecIdx(uint8_t *off, OutputSection *os,
 100                         unsigned numOutputSections) {
 101   // numOutputSections is the largest valid section index. Make sure that
 102   // it fits in 16 bits.
 103   assert(numOutputSections <= 0xffff && "size of outputSections is too big");
 104
 105   // Absolute symbol doesn't have section index, but section index relocation
 106   // against absolute symbol should be resolved to one plus the last output
 107   // section index. This is required for compatibility with MSVC.
 108   if (os)
 109     add16(off, os->sectionIndex);
 110   else
 111     add16(off, numOutputSections + 1);
 112 }
 113
 114 void SectionChunk::applyRelX64(uint8_t *off, uint16_t type, OutputSection *os,
 115                                uint64_t s, uint64_t p,
 116                                uint64_t imageBase) const {
 117   switch (type) {
 118   case IMAGE_REL_AMD64_ADDR32:
 119     add32(off, s + imageBase);
 120     break;
 121   case IMAGE_REL_AMD64_ADDR64:
 122     add64(off, s + imageBase);
 123     break;
 124   case IMAGE_REL_AMD64_ADDR32NB: add32(off, s); break;
 125   case IMAGE_REL_AMD64_REL32:    add32(off, s - p - 4); break;
 126   case IMAGE_REL_AMD64_REL32_1:  add32(off, s - p - 5); break;
 127   case IMAGE_REL_AMD64_REL32_2:  add32(off, s - p - 6); break;
 128   case IMAGE_REL_AMD64_REL32_3:  add32(off, s - p - 7); break;
 129   case IMAGE_REL_AMD64_REL32_4:  add32(off, s - p - 8); break;
 130   case IMAGE_REL_AMD64_REL32_5:  add32(off, s - p - 9); break;
 131   case IMAGE_REL_AMD64_SECTION:
 132     applySecIdx(off, os, file->symtab.ctx.outputSections.size());
 133     break;
 134   case IMAGE_REL_AMD64_SECREL:   applySecRel(this, off, os, s); break;
 135   default:
 136     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 137           toString(file));
 138   }
 139 }
 140
 141 void SectionChunk::applyRelX86(uint8_t *off, uint16_t type, OutputSection *os,
 142                                uint64_t s, uint64_t p,
 143                                uint64_t imageBase) const {
 144   switch (type) {
 145   case IMAGE_REL_I386_ABSOLUTE: break;
 146   case IMAGE_REL_I386_DIR32:
 147     add32(off, s + imageBase);
 148     break;
 149   case IMAGE_REL_I386_DIR32NB:  add32(off, s); break;
 150   case IMAGE_REL_I386_REL32:    add32(off, s - p - 4); break;
 151   case IMAGE_REL_I386_SECTION:
 152     applySecIdx(off, os, file->symtab.ctx.outputSections.size());
 153     break;
 154   case IMAGE_REL_I386_SECREL:   applySecRel(this, off, os, s); break;
 155   default:
 156     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 157           toString(file));
 158   }
 159 }
 160
 161 static void applyMOV(uint8_t *off, uint16_t v) {
 162   write16le(off, (read16le(off) & 0xfbf0) | ((v & 0x800) >> 1) | ((v >> 12) & 0xf));
 163   write16le(off + 2, (read16le(off + 2) & 0x8f00) | ((v & 0x700) << 4) | (v & 0xff));
 164 }
 165
 166 static uint16_t readMOV(uint8_t *off, bool movt) {
 167   uint16_t op1 = read16le(off);
 168   if ((op1 & 0xfbf0) != (movt ? 0xf2c0 : 0xf240))
 169     error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
 170           " instruction in MOV32T relocation");
 171   uint16_t op2 = read16le(off + 2);
 172   if ((op2 & 0x8000) != 0)
 173     error("unexpected instruction in " + Twine(movt ? "MOVT" : "MOVW") +
 174           " instruction in MOV32T relocation");
 175   return (op2 & 0x00ff) | ((op2 >> 4) & 0x0700) | ((op1 << 1) & 0x0800) |
 176          ((op1 & 0x000f) << 12);
 177 }
 178
 179 void applyMOV32T(uint8_t *off, uint32_t v) {
 180   uint16_t immW = readMOV(off, false);    // read MOVW operand
 181   uint16_t immT = readMOV(off + 4, true); // read MOVT operand
 182   uint32_t imm = immW | (immT << 16);
 183   v += imm;                         // add the immediate offset
 184   applyMOV(off, v);           // set MOVW operand
 185   applyMOV(off + 4, v >> 16); // set MOVT operand
 186 }
 187
 188 static void applyBranch20T(uint8_t *off, int32_t v) {
 189   if (!isInt<21>(v))
 190     error("relocation out of range");
 191   uint32_t s = v < 0 ? 1 : 0;
 192   uint32_t j1 = (v >> 19) & 1;
 193   uint32_t j2 = (v >> 18) & 1;
 194   or16(off, (s << 10) | ((v >> 12) & 0x3f));
 195   or16(off + 2, (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
 196 }
 197
 198 void applyBranch24T(uint8_t *off, int32_t v) {
 199   if (!isInt<25>(v))
 200     error("relocation out of range");
 201   uint32_t s = v < 0 ? 1 : 0;
 202   uint32_t j1 = ((~v >> 23) & 1) ^ s;
 203   uint32_t j2 = ((~v >> 22) & 1) ^ s;
 204   or16(off, (s << 10) | ((v >> 12) & 0x3ff));
 205   // Clear out the J1 and J2 bits which may be set.
 206   write16le(off + 2, (read16le(off + 2) & 0xd000) | (j1 << 13) | (j2 << 11) | ((v >> 1) & 0x7ff));
 207 }
 208
 209 void SectionChunk::applyRelARM(uint8_t *off, uint16_t type, OutputSection *os,
 210                                uint64_t s, uint64_t p,
 211                                uint64_t imageBase) const {
 212   // Pointer to thumb code must have the LSB set.
 213   uint64_t sx = s;
 214   if (os && (os->header.Characteristics & IMAGE_SCN_MEM_EXECUTE))
 215     sx |= 1;
 216   switch (type) {
 217   case IMAGE_REL_ARM_ADDR32:
 218     add32(off, sx + imageBase);
 219     break;
 220   case IMAGE_REL_ARM_ADDR32NB:  add32(off, sx); break;
 221   case IMAGE_REL_ARM_MOV32T:
 222     applyMOV32T(off, sx + imageBase);
 223     break;
 224   case IMAGE_REL_ARM_BRANCH20T: applyBranch20T(off, sx - p - 4); break;
 225   case IMAGE_REL_ARM_BRANCH24T: applyBranch24T(off, sx - p - 4); break;
 226   case IMAGE_REL_ARM_BLX23T:    applyBranch24T(off, sx - p - 4); break;
 227   case IMAGE_REL_ARM_SECTION:
 228     applySecIdx(off, os, file->symtab.ctx.outputSections.size());
 229     break;
 230   case IMAGE_REL_ARM_SECREL:    applySecRel(this, off, os, s); break;
 231   case IMAGE_REL_ARM_REL32:     add32(off, sx - p - 4); break;
 232   default:
 233     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 234           toString(file));
 235   }
 236 }
 237
 238 // Interpret the existing immediate value as a byte offset to the
 239 // target symbol, then update the instruction with the immediate as
 240 // the page offset from the current instruction to the target.
 241 void applyArm64Addr(uint8_t *off, uint64_t s, uint64_t p, int shift) {
 242   uint32_t orig = read32le(off);
 243   int64_t imm =
 244       SignExtend64<21>(((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC));
 245   s += imm;
 246   imm = (s >> shift) - (p >> shift);
 247   uint32_t immLo = (imm & 0x3) << 29;
 248   uint32_t immHi = (imm & 0x1FFFFC) << 3;
 249   uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3);
 250   write32le(off, (orig & ~mask) | immLo | immHi);
 251 }
 252
 253 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
 254 // Optionally limit the range of the written immediate by one or more bits
 255 // (rangeLimit).
 256 void applyArm64Imm(uint8_t *off, uint64_t imm, uint32_t rangeLimit) {
 257   uint32_t orig = read32le(off);
 258   imm += (orig >> 10) & 0xFFF;
 259   orig &= ~(0xFFF << 10);
 260   write32le(off, orig | ((imm & (0xFFF >> rangeLimit)) << 10));
 261 }
 262
 263 // Add the 12 bit page offset to the existing immediate.
 264 // Ldr/str instructions store the opcode immediate scaled
 265 // by the load/store size (giving a larger range for larger
 266 // loads/stores). The immediate is always (both before and after
 267 // fixing up the relocation) stored scaled similarly.
 268 // Even if larger loads/stores have a larger range, limit the
 269 // effective offset to 12 bit, since it is intended to be a
 270 // page offset.
 271 static void applyArm64Ldr(uint8_t *off, uint64_t imm) {
 272   uint32_t orig = read32le(off);
 273   uint32_t size = orig >> 30;
 274   // 0x04000000 indicates SIMD/FP registers
 275   // 0x00800000 indicates 128 bit
 276   if ((orig & 0x4800000) == 0x4800000)
 277     size += 4;
 278   if ((imm & ((1 << size) - 1)) != 0)
 279     error("misaligned ldr/str offset");
 280   applyArm64Imm(off, imm >> size, size);
 281 }
 282
 283 static void applySecRelLow12A(const SectionChunk *sec, uint8_t *off,
 284                               OutputSection *os, uint64_t s) {
 285   if (checkSecRel(sec, os))
 286     applyArm64Imm(off, (s - os->getRVA()) & 0xfff, 0);
 287 }
 288
 289 static void applySecRelHigh12A(const SectionChunk *sec, uint8_t *off,
 290                                OutputSection *os, uint64_t s) {
 291   if (!checkSecRel(sec, os))
 292     return;
 293   uint64_t secRel = (s - os->getRVA()) >> 12;
 294   if (0xfff < secRel) {
 295     error("overflow in SECREL_HIGH12A relocation in section: " +
 296           sec->getSectionName());
 297     return;
 298   }
 299   applyArm64Imm(off, secRel & 0xfff, 0);
 300 }
 301
 302 static void applySecRelLdr(const SectionChunk *sec, uint8_t *off,
 303                            OutputSection *os, uint64_t s) {
 304   if (checkSecRel(sec, os))
 305     applyArm64Ldr(off, (s - os->getRVA()) & 0xfff);
 306 }
 307
 308 void applyArm64Branch26(uint8_t *off, int64_t v) {
 309   if (!isInt<28>(v))
 310     error("relocation out of range");
 311   or32(off, (v & 0x0FFFFFFC) >> 2);
 312 }
 313
 314 static void applyArm64Branch19(uint8_t *off, int64_t v) {
 315   if (!isInt<21>(v))
 316     error("relocation out of range");
 317   or32(off, (v & 0x001FFFFC) << 3);
 318 }
 319
 320 static void applyArm64Branch14(uint8_t *off, int64_t v) {
 321   if (!isInt<16>(v))
 322     error("relocation out of range");
 323   or32(off, (v & 0x0000FFFC) << 3);
 324 }
 325
 326 void SectionChunk::applyRelARM64(uint8_t *off, uint16_t type, OutputSection *os,
 327                                  uint64_t s, uint64_t p,
 328                                  uint64_t imageBase) const {
 329   switch (type) {
 330   case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(off, s, p, 12); break;
 331   case IMAGE_REL_ARM64_REL21:          applyArm64Addr(off, s, p, 0); break;
 332   case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(off, s & 0xfff, 0); break;
 333   case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(off, s & 0xfff); break;
 334   case IMAGE_REL_ARM64_BRANCH26:       applyArm64Branch26(off, s - p); break;
 335   case IMAGE_REL_ARM64_BRANCH19:       applyArm64Branch19(off, s - p); break;
 336   case IMAGE_REL_ARM64_BRANCH14:       applyArm64Branch14(off, s - p); break;
 337   case IMAGE_REL_ARM64_ADDR32:
 338     add32(off, s + imageBase);
 339     break;
 340   case IMAGE_REL_ARM64_ADDR32NB:       add32(off, s); break;
 341   case IMAGE_REL_ARM64_ADDR64:
 342     add64(off, s + imageBase);
 343     break;
 344   case IMAGE_REL_ARM64_SECREL:         applySecRel(this, off, os, s); break;
 345   case IMAGE_REL_ARM64_SECREL_LOW12A:  applySecRelLow12A(this, off, os, s); break;
 346   case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelHigh12A(this, off, os, s); break;
 347   case IMAGE_REL_ARM64_SECREL_LOW12L:  applySecRelLdr(this, off, os, s); break;
 348   case IMAGE_REL_ARM64_SECTION:
 349     applySecIdx(off, os, file->symtab.ctx.outputSections.size());
 350     break;
 351   case IMAGE_REL_ARM64_REL32:          add32(off, s - p - 4); break;
 352   default:
 353     error("unsupported relocation type 0x" + Twine::utohexstr(type) + " in " +
 354           toString(file));
 355   }
 356 }
 357
 358 static void maybeReportRelocationToDiscarded(const SectionChunk *fromChunk,
 359                                              Defined *sym,
 360                                              const coff_relocation &rel,
 361                                              bool isMinGW) {
 362   // Don't report these errors when the relocation comes from a debug info
 363   // section or in mingw mode. MinGW mode object files (built by GCC) can
 364   // have leftover sections with relocations against discarded comdat
 365   // sections. Such sections are left as is, with relocations untouched.
 366   if (fromChunk->isCodeView() || fromChunk->isDWARF() || isMinGW)
 367     return;
 368
 369   // Get the name of the symbol. If it's null, it was discarded early, so we
 370   // have to go back to the object file.
 371   ObjFile *file = fromChunk->file;
 372   std::string name;
 373   if (sym) {
 374     name = toString(file->symtab.ctx, *sym);
 375   } else {
 376     COFFSymbolRef coffSym =
 377         check(file->getCOFFObj()->getSymbol(rel.SymbolTableIndex));
 378     name = maybeDemangleSymbol(
 379         file->symtab.ctx, check(file->getCOFFObj()->getSymbolName(coffSym)));
 380   }
 381
 382   std::vector<std::string> symbolLocations =
 383       getSymbolLocations(file, rel.SymbolTableIndex);
 384
 385   std::string out;
 386   llvm::raw_string_ostream os(out);
 387   os << "relocation against symbol in discarded section: " + name;
 388   for (const std::string &s : symbolLocations)
 389     os << s;
 390   error(out);
 391 }
 392
 393 void SectionChunk::writeTo(uint8_t *buf) const {
 394   if (!hasData)
 395     return;
 396   // Copy section contents from source object file to output file.
 397   ArrayRef<uint8_t> a = getContents();
 398   if (!a.empty())
 399     memcpy(buf, a.data(), a.size());
 400
 401   // Apply relocations.
 402   size_t inputSize = getSize();
 403   for (const coff_relocation &rel : getRelocs()) {
 404     // Check for an invalid relocation offset. This check isn't perfect, because
 405     // we don't have the relocation size, which is only known after checking the
 406     // machine and relocation type. As a result, a relocation may overwrite the
 407     // beginning of the following input section.
 408     if (rel.VirtualAddress >= inputSize) {
 409       error("relocation points beyond the end of its parent section");
 410       continue;
 411     }
 412
 413     applyRelocation(buf + rel.VirtualAddress, rel);
 414   }
 415
 416   // Write the offset to EC entry thunk preceding section contents. The low bit
 417   // is always set, so it's effectively an offset from the last byte of the
 418   // offset.
 419   if (Defined *entryThunk = getEntryThunk())
 420     write32le(buf - sizeof(uint32_t), entryThunk->getRVA() - rva + 1);
 421 }
 422
 423 void SectionChunk::applyRelocation(uint8_t *off,
 424                                    const coff_relocation &rel) const {
 425   auto *sym = dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex));
 426
 427   // Get the output section of the symbol for this relocation.  The output
 428   // section is needed to compute SECREL and SECTION relocations used in debug
 429   // info.
 430   Chunk *c = sym ? sym->getChunk() : nullptr;
 431   COFFLinkerContext &ctx = file->symtab.ctx;
 432   OutputSection *os = c ? ctx.getOutputSection(c) : nullptr;
 433
 434   // Skip the relocation if it refers to a discarded section, and diagnose it
 435   // as an error if appropriate. If a symbol was discarded early, it may be
 436   // null. If it was discarded late, the output section will be null, unless
 437   // it was an absolute or synthetic symbol.
 438   if (!sym ||
 439       (!os && !isa<DefinedAbsolute>(sym) && !isa<DefinedSynthetic>(sym))) {
 440     maybeReportRelocationToDiscarded(this, sym, rel, ctx.config.mingw);
 441     return;
 442   }
 443
 444   uint64_t s = sym->getRVA();
 445
 446   // Compute the RVA of the relocation for relative relocations.
 447   uint64_t p = rva + rel.VirtualAddress;
 448   uint64_t imageBase = ctx.config.imageBase;
 449   switch (getArch()) {
 450   case Triple::x86_64:
 451     applyRelX64(off, rel.Type, os, s, p, imageBase);
 452     break;
 453   case Triple::x86:
 454     applyRelX86(off, rel.Type, os, s, p, imageBase);
 455     break;
 456   case Triple::thumb:
 457     applyRelARM(off, rel.Type, os, s, p, imageBase);
 458     break;
 459   case Triple::aarch64:
 460     applyRelARM64(off, rel.Type, os, s, p, imageBase);
 461     break;
 462   default:
 463     llvm_unreachable("unknown machine type");
 464   }
 465 }
 466
 467 // Defend against unsorted relocations. This may be overly conservative.
 468 void SectionChunk::sortRelocations() {
 469   auto cmpByVa = [](const coff_relocation &l, const coff_relocation &r) {
 470     return l.VirtualAddress < r.VirtualAddress;
 471   };
 472   if (llvm::is_sorted(getRelocs(), cmpByVa))
 473     return;
 474   warn("some relocations in " + file->getName() + " are not sorted");
 475   MutableArrayRef<coff_relocation> newRelocs(
 476       bAlloc().Allocate<coff_relocation>(relocsSize), relocsSize);
 477   memcpy(newRelocs.data(), relocsData, relocsSize * sizeof(coff_relocation));
 478   llvm::sort(newRelocs, cmpByVa);
 479   setRelocs(newRelocs);
 480 }
 481
 482 // Similar to writeTo, but suitable for relocating a subsection of the overall
 483 // section.
 484 void SectionChunk::writeAndRelocateSubsection(ArrayRef<uint8_t> sec,
 485                                               ArrayRef<uint8_t> subsec,
 486                                               uint32_t &nextRelocIndex,
 487                                               uint8_t *buf) const {
 488   assert(!subsec.empty() && !sec.empty());
 489   assert(sec.begin() <= subsec.begin() && subsec.end() <= sec.end() &&
 490          "subsection is not part of this section");
 491   size_t vaBegin = std::distance(sec.begin(), subsec.begin());
 492   size_t vaEnd = std::distance(sec.begin(), subsec.end());
 493   memcpy(buf, subsec.data(), subsec.size());
 494   for (; nextRelocIndex < relocsSize; ++nextRelocIndex) {
 495     const coff_relocation &rel = relocsData[nextRelocIndex];
 496     // Only apply relocations that apply to this subsection. These checks
 497     // assume that all subsections completely contain their relocations.
 498     // Relocations must not straddle the beginning or end of a subsection.
 499     if (rel.VirtualAddress < vaBegin)
 500       continue;
 501     if (rel.VirtualAddress + 1 >= vaEnd)
 502       break;
 503     applyRelocation(&buf[rel.VirtualAddress - vaBegin], rel);
 504   }
 505 }
 506
 507 void SectionChunk::addAssociative(SectionChunk *child) {
 508   // Insert the child section into the list of associated children. Keep the
 509   // list ordered by section name so that ICF does not depend on section order.
 510   assert(child->assocChildren == nullptr &&
 511          "associated sections cannot have their own associated children");
 512   SectionChunk *prev = this;
 513   SectionChunk *next = assocChildren;
 514   for (; next != nullptr; prev = next, next = next->assocChildren) {
 515     if (next->getSectionName() <= child->getSectionName())
 516       break;
 517   }
 518
 519   // Insert child between prev and next.
 520   assert(prev->assocChildren == next);
 521   prev->assocChildren = child;
 522   child->assocChildren = next;
 523 }
 524
 525 static uint8_t getBaserelType(const coff_relocation &rel,
 526                               Triple::ArchType arch) {
 527   switch (arch) {
 528   case Triple::x86_64:
 529     if (rel.Type == IMAGE_REL_AMD64_ADDR64)
 530       return IMAGE_REL_BASED_DIR64;
 531     if (rel.Type == IMAGE_REL_AMD64_ADDR32)
 532       return IMAGE_REL_BASED_HIGHLOW;
 533     return IMAGE_REL_BASED_ABSOLUTE;
 534   case Triple::x86:
 535     if (rel.Type == IMAGE_REL_I386_DIR32)
 536       return IMAGE_REL_BASED_HIGHLOW;
 537     return IMAGE_REL_BASED_ABSOLUTE;
 538   case Triple::thumb:
 539     if (rel.Type == IMAGE_REL_ARM_ADDR32)
 540       return IMAGE_REL_BASED_HIGHLOW;
 541     if (rel.Type == IMAGE_REL_ARM_MOV32T)
 542       return IMAGE_REL_BASED_ARM_MOV32T;
 543     return IMAGE_REL_BASED_ABSOLUTE;
 544   case Triple::aarch64:
 545     if (rel.Type == IMAGE_REL_ARM64_ADDR64)
 546       return IMAGE_REL_BASED_DIR64;
 547     return IMAGE_REL_BASED_ABSOLUTE;
 548   default:
 549     llvm_unreachable("unknown machine type");
 550   }
 551 }
 552
 553 // Windows-specific.
 554 // Collect all locations that contain absolute addresses, which need to be
 555 // fixed by the loader if load-time relocation is needed.
 556 // Only called when base relocation is enabled.
 557 void SectionChunk::getBaserels(std::vector<Baserel> *res) {
 558   for (const coff_relocation &rel : getRelocs()) {
 559     uint8_t ty = getBaserelType(rel, getArch());
 560     if (ty == IMAGE_REL_BASED_ABSOLUTE)
 561       continue;
 562     Symbol *target = file->getSymbol(rel.SymbolTableIndex);
 563     if (!target || isa<DefinedAbsolute>(target))
 564       continue;
 565     res->emplace_back(rva + rel.VirtualAddress, ty);
 566   }
 567 }
 568
 569 // MinGW specific.
 570 // Check whether a static relocation of type Type can be deferred and
 571 // handled at runtime as a pseudo relocation (for references to a module
 572 // local variable, which turned out to actually need to be imported from
 573 // another DLL) This returns the size the relocation is supposed to update,
 574 // in bits, or 0 if the relocation cannot be handled as a runtime pseudo
 575 // relocation.
 576 static int getRuntimePseudoRelocSize(uint16_t type, Triple::ArchType arch) {
 577   // Relocations that either contain an absolute address, or a plain
 578   // relative offset, since the runtime pseudo reloc implementation
 579   // adds 8/16/32/64 bit values to a memory address.
 580   //
 581   // Given a pseudo relocation entry,
 582   //
 583   // typedef struct {
 584   //   DWORD sym;
 585   //   DWORD target;
 586   //   DWORD flags;
 587   // } runtime_pseudo_reloc_item_v2;
 588   //
 589   // the runtime relocation performs this adjustment:
 590   //     *(base + .target) += *(base + .sym) - (base + .sym)
 591   //
 592   // This works for both absolute addresses (IMAGE_REL_*_ADDR32/64,
 593   // IMAGE_REL_I386_DIR32, where the memory location initially contains
 594   // the address of the IAT slot, and for relative addresses (IMAGE_REL*_REL32),
 595   // where the memory location originally contains the relative offset to the
 596   // IAT slot.
 597   //
 598   // This requires the target address to be writable, either directly out of
 599   // the image, or temporarily changed at runtime with VirtualProtect.
 600   // Since this only operates on direct address values, it doesn't work for
 601   // ARM/ARM64 relocations, other than the plain ADDR32/ADDR64 relocations.
 602   switch (arch) {
 603   case Triple::x86_64:
 604     switch (type) {
 605     case IMAGE_REL_AMD64_ADDR64:
 606       return 64;
 607     case IMAGE_REL_AMD64_ADDR32:
 608     case IMAGE_REL_AMD64_REL32:
 609     case IMAGE_REL_AMD64_REL32_1:
 610     case IMAGE_REL_AMD64_REL32_2:
 611     case IMAGE_REL_AMD64_REL32_3:
 612     case IMAGE_REL_AMD64_REL32_4:
 613     case IMAGE_REL_AMD64_REL32_5:
 614       return 32;
 615     default:
 616       return 0;
 617     }
 618   case Triple::x86:
 619     switch (type) {
 620     case IMAGE_REL_I386_DIR32:
 621     case IMAGE_REL_I386_REL32:
 622       return 32;
 623     default:
 624       return 0;
 625     }
 626   case Triple::thumb:
 627     switch (type) {
 628     case IMAGE_REL_ARM_ADDR32:
 629       return 32;
 630     default:
 631       return 0;
 632     }
 633   case Triple::aarch64:
 634     switch (type) {
 635     case IMAGE_REL_ARM64_ADDR64:
 636       return 64;
 637     case IMAGE_REL_ARM64_ADDR32:
 638       return 32;
 639     default:
 640       return 0;
 641     }
 642   default:
 643     llvm_unreachable("unknown machine type");
 644   }
 645 }
 646
 647 // MinGW specific.
 648 // Append information to the provided vector about all relocations that
 649 // need to be handled at runtime as runtime pseudo relocations (references
 650 // to a module local variable, which turned out to actually need to be
 651 // imported from another DLL).
 652 void SectionChunk::getRuntimePseudoRelocs(
 653     std::vector<RuntimePseudoReloc> &res) {
 654   for (const coff_relocation &rel : getRelocs()) {
 655     auto *target =
 656         dyn_cast_or_null<Defined>(file->getSymbol(rel.SymbolTableIndex));
 657     if (!target || !target->isRuntimePseudoReloc)
 658       continue;
 659     // If the target doesn't have a chunk allocated, it may be a
 660     // DefinedImportData symbol which ended up unnecessary after GC.
 661     // Normally we wouldn't eliminate section chunks that are referenced, but
 662     // references within DWARF sections don't count for keeping section chunks
 663     // alive. Thus such dangling references in DWARF sections are expected.
 664     if (!target->getChunk())
 665       continue;
 666     int sizeInBits = getRuntimePseudoRelocSize(rel.Type, getArch());
 667     if (sizeInBits == 0) {
 668       error("unable to automatically import from " + target->getName() +
 669             " with relocation type " +
 670             file->getCOFFObj()->getRelocationTypeName(rel.Type) + " in " +
 671             toString(file));
 672       continue;
 673     }
 674     int addressSizeInBits = file->symtab.ctx.config.is64() ? 64 : 32;
 675     if (sizeInBits < addressSizeInBits) {
 676       warn("runtime pseudo relocation in " + toString(file) + " against " +
 677            "symbol " + target->getName() + " is too narrow (only " +
 678            Twine(sizeInBits) + " bits wide); this can fail at runtime " +
 679            "depending on memory layout");
 680     }
 681     // sizeInBits is used to initialize the Flags field; currently no
 682     // other flags are defined.
 683     res.emplace_back(target, this, rel.VirtualAddress, sizeInBits);
 684   }
 685 }
 686
 687 bool SectionChunk::isCOMDAT() const {
 688   return header->Characteristics & IMAGE_SCN_LNK_COMDAT;
 689 }
 690
 691 void SectionChunk::printDiscardedMessage() const {
 692   // Removed by dead-stripping. If it's removed by ICF, ICF already
 693   // printed out the name, so don't repeat that here.
 694   if (sym && this == repl)
 695     log("Discarded " + sym->getName());
 696 }
 697
 698 StringRef SectionChunk::getDebugName() const {
 699   if (sym)
 700     return sym->getName();
 701   return "";
 702 }
 703
 704 ArrayRef<uint8_t> SectionChunk::getContents() const {
 705   ArrayRef<uint8_t> a;
 706   cantFail(file->getCOFFObj()->getSectionContents(header, a));
 707   return a;
 708 }
 709
 710 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic() {
 711   assert(isCodeView());
 712   return consumeDebugMagic(getContents(), getSectionName());
 713 }
 714
 715 ArrayRef<uint8_t> SectionChunk::consumeDebugMagic(ArrayRef<uint8_t> data,
 716                                                   StringRef sectionName) {
 717   if (data.empty())
 718     return {};
 719
 720   // First 4 bytes are section magic.
 721   if (data.size() < 4)
 722     fatal("the section is too short: " + sectionName);
 723
 724   if (!sectionName.starts_with(".debug$"))
 725     fatal("invalid section: " + sectionName);
 726
 727   uint32_t magic = support::endian::read32le(data.data());
 728   uint32_t expectedMagic = sectionName == ".debug$H"
 729                                ? DEBUG_HASHES_SECTION_MAGIC
 730                                : DEBUG_SECTION_MAGIC;
 731   if (magic != expectedMagic) {
 732     warn("ignoring section " + sectionName + " with unrecognized magic 0x" +
 733          utohexstr(magic));
 734     return {};
 735   }
 736   return data.slice(4);
 737 }
 738
 739 SectionChunk *SectionChunk::findByName(ArrayRef<SectionChunk *> sections,
 740                                        StringRef name) {
 741   for (SectionChunk *c : sections)
 742     if (c->getSectionName() == name)
 743       return c;
 744   return nullptr;
 745 }
 746
 747 void SectionChunk::replace(SectionChunk *other) {
 748   p2Align = std::max(p2Align, other->p2Align);
 749   other->repl = repl;
 750   other->live = false;
 751 }
 752
 753 uint32_t SectionChunk::getSectionNumber() const {
 754   DataRefImpl r;
 755   r.p = reinterpret_cast<uintptr_t>(header);
 756   SectionRef s(r, file->getCOFFObj());
 757   return s.getIndex() + 1;
 758 }
 759
 760 CommonChunk::CommonChunk(const COFFSymbolRef s) : sym(s) {
 761   // The value of a common symbol is its size. Align all common symbols smaller
 762   // than 32 bytes naturally, i.e. round the size up to the next power of two.
 763   // This is what MSVC link.exe does.
 764   setAlignment(std::min(32U, uint32_t(PowerOf2Ceil(sym.getValue()))));
 765   hasData = false;
 766 }
 767
 768 uint32_t CommonChunk::getOutputCharacteristics() const {
 769   return IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_MEM_READ |
 770          IMAGE_SCN_MEM_WRITE;
 771 }
 772
 773 void StringChunk::writeTo(uint8_t *buf) const {
 774   memcpy(buf, str.data(), str.size());
 775   buf[str.size()] = '\0';
 776 }
 777
 778 ImportThunkChunk::ImportThunkChunk(COFFLinkerContext &ctx, Defined *s)
 779     : NonSectionCodeChunk(ImportThunkKind), live(!ctx.config.doGC),
 780       impSymbol(s), ctx(ctx) {}
 781
 782 ImportThunkChunkX64::ImportThunkChunkX64(COFFLinkerContext &ctx, Defined *s)
 783     : ImportThunkChunk(ctx, s) {
 784   // Intel Optimization Manual says that all branch targets
 785   // should be 16-byte aligned. MSVC linker does this too.
 786   setAlignment(16);
 787 }
 788
 789 void ImportThunkChunkX64::writeTo(uint8_t *buf) const {
 790   memcpy(buf, importThunkX86, sizeof(importThunkX86));
 791   // The first two bytes is a JMP instruction. Fill its operand.
 792   write32le(buf + 2, impSymbol->getRVA() - rva - getSize());
 793 }
 794
 795 void ImportThunkChunkX86::getBaserels(std::vector<Baserel> *res) {
 796   res->emplace_back(getRVA() + 2, ctx.config.machine);
 797 }
 798
 799 void ImportThunkChunkX86::writeTo(uint8_t *buf) const {
 800   memcpy(buf, importThunkX86, sizeof(importThunkX86));
 801   // The first two bytes is a JMP instruction. Fill its operand.
 802   write32le(buf + 2, impSymbol->getRVA() + ctx.config.imageBase);
 803 }
 804
 805 void ImportThunkChunkARM::getBaserels(std::vector<Baserel> *res) {
 806   res->emplace_back(getRVA(), IMAGE_REL_BASED_ARM_MOV32T);
 807 }
 808
 809 void ImportThunkChunkARM::writeTo(uint8_t *buf) const {
 810   memcpy(buf, importThunkARM, sizeof(importThunkARM));
 811   // Fix mov.w and mov.t operands.
 812   applyMOV32T(buf, impSymbol->getRVA() + ctx.config.imageBase);
 813 }
 814
 815 void ImportThunkChunkARM64::writeTo(uint8_t *buf) const {
 816   int64_t off = impSymbol->getRVA() & 0xfff;
 817   memcpy(buf, importThunkARM64, sizeof(importThunkARM64));
 818   applyArm64Addr(buf, impSymbol->getRVA(), rva, 12);
 819   applyArm64Ldr(buf + 4, off);
 820 }
 821
 822 // A Thumb2, PIC, non-interworking range extension thunk.
 823 const uint8_t armThunk[] = {
 824     0x40, 0xf2, 0x00, 0x0c, // P:  movw ip,:lower16:S - (P + (L1-P) + 4)
 825     0xc0, 0xf2, 0x00, 0x0c, //     movt ip,:upper16:S - (P + (L1-P) + 4)
 826     0xe7, 0x44,             // L1: add  pc, ip
 827 };
 828
 829 size_t RangeExtensionThunkARM::getSize() const {
 830   assert(ctx.config.machine == ARMNT);
 831   (void)&ctx;
 832   return sizeof(armThunk);
 833 }
 834
 835 void RangeExtensionThunkARM::writeTo(uint8_t *buf) const {
 836   assert(ctx.config.machine == ARMNT);
 837   uint64_t offset = target->getRVA() - rva - 12;
 838   memcpy(buf, armThunk, sizeof(armThunk));
 839   applyMOV32T(buf, uint32_t(offset));
 840 }
 841
 842 // A position independent ARM64 adrp+add thunk, with a maximum range of
 843 // +/- 4 GB, which is enough for any PE-COFF.
 844 const uint8_t arm64Thunk[] = {
 845     0x10, 0x00, 0x00, 0x90, // adrp x16, Dest
 846     0x10, 0x02, 0x00, 0x91, // add  x16, x16, :lo12:Dest
 847     0x00, 0x02, 0x1f, 0xd6, // br   x16
 848 };
 849
 850 size_t RangeExtensionThunkARM64::getSize() const { return sizeof(arm64Thunk); }
 851
 852 void RangeExtensionThunkARM64::writeTo(uint8_t *buf) const {
 853   memcpy(buf, arm64Thunk, sizeof(arm64Thunk));
 854   applyArm64Addr(buf + 0, target->getRVA(), rva, 12);
 855   applyArm64Imm(buf + 4, target->getRVA() & 0xfff, 0);
 856 }
 857
 858 LocalImportChunk::LocalImportChunk(COFFLinkerContext &c, Defined *s)
 859     : sym(s), ctx(c) {
 860   setAlignment(ctx.config.wordsize);
 861 }
 862
 863 void LocalImportChunk::getBaserels(std::vector<Baserel> *res) {
 864   res->emplace_back(getRVA(), ctx.config.machine);
 865 }
 866
 867 size_t LocalImportChunk::getSize() const { return ctx.config.wordsize; }
 868
 869 void LocalImportChunk::writeTo(uint8_t *buf) const {
 870   if (ctx.config.is64()) {
 871     write64le(buf, sym->getRVA() + ctx.config.imageBase);
 872   } else {
 873     write32le(buf, sym->getRVA() + ctx.config.imageBase);
 874   }
 875 }
 876
 877 void RVATableChunk::writeTo(uint8_t *buf) const {
 878   ulittle32_t *begin = reinterpret_cast<ulittle32_t *>(buf);
 879   size_t cnt = 0;
 880   for (const ChunkAndOffset &co : syms)
 881     begin[cnt++] = co.inputChunk->getRVA() + co.offset;
 882   llvm::sort(begin, begin + cnt);
 883   assert(std::unique(begin, begin + cnt) == begin + cnt &&
 884          "RVA tables should be de-duplicated");
 885 }
 886
 887 void RVAFlagTableChunk::writeTo(uint8_t *buf) const {
 888   struct RVAFlag {
 889     ulittle32_t rva;
 890     uint8_t flag;
 891   };
 892   auto flags =
 893       MutableArrayRef(reinterpret_cast<RVAFlag *>(buf), syms.size());
 894   for (auto t : zip(syms, flags)) {
 895     const auto &sym = std::get<0>(t);
 896     auto &flag = std::get<1>(t);
 897     flag.rva = sym.inputChunk->getRVA() + sym.offset;
 898     flag.flag = 0;
 899   }
 900   llvm::sort(flags,
 901              [](const RVAFlag &a, const RVAFlag &b) { return a.rva < b.rva; });
 902   assert(llvm::unique(flags, [](const RVAFlag &a,
 903                                 const RVAFlag &b) { return a.rva == b.rva; }) ==
 904              flags.end() &&
 905          "RVA tables should be de-duplicated");
 906 }
 907
 908 size_t ECCodeMapChunk::getSize() const {
 909   return map.size() * sizeof(chpe_range_entry);
 910 }
 911
 912 void ECCodeMapChunk::writeTo(uint8_t *buf) const {
 913   auto table = reinterpret_cast<chpe_range_entry *>(buf);
 914   for (uint32_t i = 0; i < map.size(); i++) {
 915     const ECCodeMapEntry &entry = map[i];
 916     uint32_t start = entry.first->getRVA();
 917     table[i].StartOffset = start | entry.type;
 918     table[i].Length = entry.last->getRVA() + entry.last->getSize() - start;
 919   }
 920 }
 921
 922 // MinGW specific, for the "automatic import of variables from DLLs" feature.
 923 size_t PseudoRelocTableChunk::getSize() const {
 924   if (relocs.empty())
 925     return 0;
 926   return 12 + 12 * relocs.size();
 927 }
 928
 929 // MinGW specific.
 930 void PseudoRelocTableChunk::writeTo(uint8_t *buf) const {
 931   if (relocs.empty())
 932     return;
 933
 934   ulittle32_t *table = reinterpret_cast<ulittle32_t *>(buf);
 935   // This is the list header, to signal the runtime pseudo relocation v2
 936   // format.
 937   table[0] = 0;
 938   table[1] = 0;
 939   table[2] = 1;
 940
 941   size_t idx = 3;
 942   for (const RuntimePseudoReloc &rpr : relocs) {
 943     table[idx + 0] = rpr.sym->getRVA();
 944     table[idx + 1] = rpr.target->getRVA() + rpr.targetOffset;
 945     table[idx + 2] = rpr.flags;
 946     idx += 3;
 947   }
 948 }
 949
 950 // Windows-specific. This class represents a block in .reloc section.
 951 // The format is described here.
 952 //
 953 // On Windows, each DLL is linked against a fixed base address and
 954 // usually loaded to that address. However, if there's already another
 955 // DLL that overlaps, the loader has to relocate it. To do that, DLLs
 956 // contain .reloc sections which contain offsets that need to be fixed
 957 // up at runtime. If the loader finds that a DLL cannot be loaded to its
 958 // desired base address, it loads it to somewhere else, and add <actual
 959 // base address> - <desired base address> to each offset that is
 960 // specified by the .reloc section. In ELF terms, .reloc sections
 961 // contain relative relocations in REL format (as opposed to RELA.)
 962 //
 963 // This already significantly reduces the size of relocations compared
 964 // to ELF .rel.dyn, but Windows does more to reduce it (probably because
 965 // it was invented for PCs in the late '80s or early '90s.)  Offsets in
 966 // .reloc are grouped by page where the page size is 12 bits, and
 967 // offsets sharing the same page address are stored consecutively to
 968 // represent them with less space. This is very similar to the page
 969 // table which is grouped by (multiple stages of) pages.
 970 //
 971 // For example, let's say we have 0x00030, 0x00500, 0x00700, 0x00A00,
 972 // 0x20004, and 0x20008 in a .reloc section for x64. The uppermost 4
 973 // bits have a type IMAGE_REL_BASED_DIR64 or 0xA. In the section, they
 974 // are represented like this:
 975 //
 976 //   0x00000  -- page address (4 bytes)
 977 //   16       -- size of this block (4 bytes)
 978 //     0xA030 -- entries (2 bytes each)
 979 //     0xA500
 980 //     0xA700
 981 //     0xAA00
 982 //   0x20000  -- page address (4 bytes)
 983 //   12       -- size of this block (4 bytes)
 984 //     0xA004 -- entries (2 bytes each)
 985 //     0xA008
 986 //
 987 // Usually we have a lot of relocations for each page, so the number of
 988 // bytes for one .reloc entry is close to 2 bytes on average.
 989 BaserelChunk::BaserelChunk(uint32_t page, Baserel *begin, Baserel *end) {
 990   // Block header consists of 4 byte page RVA and 4 byte block size.
 991   // Each entry is 2 byte. Last entry may be padding.
 992   data.resize(alignTo((end - begin) * 2 + 8, 4));
 993   uint8_t *p = data.data();
 994   write32le(p, page);
 995   write32le(p + 4, data.size());
 996   p += 8;
 997   for (Baserel *i = begin; i != end; ++i) {
 998     write16le(p, (i->type << 12) | (i->rva - page));
 999     p += 2;
1000   }
1001 }
1002
1003 void BaserelChunk::writeTo(uint8_t *buf) const {
1004   memcpy(buf, data.data(), data.size());
1005 }
1006
1007 uint8_t Baserel::getDefaultType(llvm::COFF::MachineTypes machine) {
1008   return is64Bit(machine) ? IMAGE_REL_BASED_DIR64 : IMAGE_REL_BASED_HIGHLOW;
1009 }
1010
1011 MergeChunk::MergeChunk(uint32_t alignment)
1012     : builder(StringTableBuilder::RAW, llvm::Align(alignment)) {
1013   setAlignment(alignment);
1014 }
1015
1016 void MergeChunk::addSection(COFFLinkerContext &ctx, SectionChunk *c) {
1017   assert(isPowerOf2_32(c->getAlignment()));
1018   uint8_t p2Align = llvm::Log2_32(c->getAlignment());
1019   assert(p2Align < std::size(ctx.mergeChunkInstances));
1020   auto *&mc = ctx.mergeChunkInstances[p2Align];
1021   if (!mc)
1022     mc = make<MergeChunk>(c->getAlignment());
1023   mc->sections.push_back(c);
1024 }
1025
1026 void MergeChunk::finalizeContents() {
1027   assert(!finalized && "should only finalize once");
1028   for (SectionChunk *c : sections)
1029     if (c->live)
1030       builder.add(toStringRef(c->getContents()));
1031   builder.finalize();
1032   finalized = true;
1033 }
1034
1035 void MergeChunk::assignSubsectionRVAs() {
1036   for (SectionChunk *c : sections) {
1037     if (!c->live)
1038       continue;
1039     size_t off = builder.getOffset(toStringRef(c->getContents()));
1040     c->setRVA(rva + off);
1041   }
1042 }
1043
1044 uint32_t MergeChunk::getOutputCharacteristics() const {
1045   return IMAGE_SCN_MEM_READ | IMAGE_SCN_CNT_INITIALIZED_DATA;
1046 }
1047
1048 size_t MergeChunk::getSize() const {
1049   return builder.getSize();
1050 }
1051
1052 void MergeChunk::writeTo(uint8_t *buf) const {
1053   builder.write(buf);
1054 }
1055
1056 // MinGW specific.
1057 size_t AbsolutePointerChunk::getSize() const { return ctx.config.wordsize; }
1058
1059 void AbsolutePointerChunk::writeTo(uint8_t *buf) const {
1060   if (ctx.config.is64()) {
1061     write64le(buf, value);
1062   } else {
1063     write32le(buf, value);
1064   }
1065 }
1066
1067 void ECExportThunkChunk::writeTo(uint8_t *buf) const {
1068   memcpy(buf, ECExportThunkCode, sizeof(ECExportThunkCode));
1069   write32le(buf + 10, target->getRVA() - rva - 14);
1070 }
1071
1072 size_t CHPECodeRangesChunk::getSize() const {
1073   return exportThunks.size() * sizeof(chpe_code_range_entry);
1074 }
1075
1076 void CHPECodeRangesChunk::writeTo(uint8_t *buf) const {
1077   auto ranges = reinterpret_cast<chpe_code_range_entry *>(buf);
1078
1079   for (uint32_t i = 0; i < exportThunks.size(); i++) {
1080     Chunk *thunk = exportThunks[i].first;
1081     uint32_t start = thunk->getRVA();
1082     ranges[i].StartRva = start;
1083     ranges[i].EndRva = start + thunk->getSize();
1084     ranges[i].EntryPoint = start;
1085   }
1086 }
1087
1088 size_t CHPERedirectionChunk::getSize() const {
1089   // Add an extra +1 for a terminator entry.
1090   return (exportThunks.size() + 1) * sizeof(chpe_redirection_entry);
1091 }
1092
1093 void CHPERedirectionChunk::writeTo(uint8_t *buf) const {
1094   auto entries = reinterpret_cast<chpe_redirection_entry *>(buf);
1095
1096   for (uint32_t i = 0; i < exportThunks.size(); i++) {
1097     entries[i].Source = exportThunks[i].first->getRVA();
1098     entries[i].Destination = exportThunks[i].second->getRVA();
1099   }
1100 }
1101
1102 ImportThunkChunkARM64EC::ImportThunkChunkARM64EC(ImportFile *file)
1103     : ImportThunkChunk(file->symtab.ctx, file->impSym), file(file) {}
1104
1105 size_t ImportThunkChunkARM64EC::getSize() const {
1106   if (!extended)
1107     return sizeof(importThunkARM64EC);
1108   // The last instruction is replaced with an inline range extension thunk.
1109   return sizeof(importThunkARM64EC) + sizeof(arm64Thunk) - sizeof(uint32_t);
1110 }
1111
1112 void ImportThunkChunkARM64EC::writeTo(uint8_t *buf) const {
1113   memcpy(buf, importThunkARM64EC, sizeof(importThunkARM64EC));
1114   applyArm64Addr(buf, file->impSym->getRVA(), rva, 12);
1115   applyArm64Ldr(buf + 4, file->impSym->getRVA() & 0xfff);
1116
1117   // The exit thunk may be missing. This can happen if the application only
1118   // references a function by its address (in which case the thunk is never
1119   // actually used, but is still required to fill the auxiliary IAT), or in
1120   // cases of hand-written assembly calling an imported ARM64EC function (where
1121   // the exit thunk is ignored by __icall_helper_arm64ec). In such cases, MSVC
1122   // link.exe uses 0 as the RVA.
1123   uint32_t exitThunkRVA = exitThunk ? exitThunk->getRVA() : 0;
1124   applyArm64Addr(buf + 8, exitThunkRVA, rva + 8, 12);
1125   applyArm64Imm(buf + 12, exitThunkRVA & 0xfff, 0);
1126
1127   Defined *helper = cast<Defined>(file->symtab.ctx.config.arm64ECIcallHelper);
1128   if (extended) {
1129     // Replace last instruction with an inline range extension thunk.
1130     memcpy(buf + 16, arm64Thunk, sizeof(arm64Thunk));
1131     applyArm64Addr(buf + 16, helper->getRVA(), rva + 16, 12);
1132     applyArm64Imm(buf + 20, helper->getRVA() & 0xfff, 0);
1133   } else {
1134     applyArm64Branch26(buf + 16, helper->getRVA() - rva - 16);
1135   }
1136 }
1137
1138 bool ImportThunkChunkARM64EC::verifyRanges() {
1139   if (extended)
1140     return true;
1141   auto helper = cast<Defined>(file->symtab.ctx.config.arm64ECIcallHelper);
1142   return isInt<28>(helper->getRVA() - rva - 16);
1143 }
1144
1145 uint32_t ImportThunkChunkARM64EC::extendRanges() {
1146   if (extended || verifyRanges())
1147     return 0;
1148   extended = true;
1149   // The last instruction is replaced with an inline range extension thunk.
1150   return sizeof(arm64Thunk) - sizeof(uint32_t);
1151 }
1152
1153 size_t Arm64XDynamicRelocEntry::getSize() const {
1154   switch (type) {
1155   case IMAGE_DVRT_ARM64X_FIXUP_TYPE_VALUE:
1156     return sizeof(uint16_t) + size; // A header and a payload.
1157   case IMAGE_DVRT_ARM64X_FIXUP_TYPE_DELTA:
1158   case IMAGE_DVRT_ARM64X_FIXUP_TYPE_ZEROFILL:
1159     llvm_unreachable("unsupported type");
1160   }
1161 }
1162
1163 void Arm64XDynamicRelocEntry::writeTo(uint8_t *buf) const {
1164   auto out = reinterpret_cast<ulittle16_t *>(buf);
1165   *out = (offset & 0xfff) | (type << 12);
1166
1167   switch (type) {
1168   case IMAGE_DVRT_ARM64X_FIXUP_TYPE_VALUE:
1169     *out |= ((bit_width(size) - 1) << 14); // Encode the size.
1170     switch (size) {
1171     case 2:
1172       out[1] = value;
1173       break;
1174     case 4:
1175       *reinterpret_cast<ulittle32_t *>(out + 1) = value;
1176       break;
1177     case 8:
1178       *reinterpret_cast<ulittle64_t *>(out + 1) = value;
1179       break;
1180     default:
1181       llvm_unreachable("invalid size");
1182     }
1183     break;
1184   case IMAGE_DVRT_ARM64X_FIXUP_TYPE_DELTA:
1185   case IMAGE_DVRT_ARM64X_FIXUP_TYPE_ZEROFILL:
1186     llvm_unreachable("unsupported type");
1187   }
1188 }
1189
1190 void DynamicRelocsChunk::finalize() {
1191   llvm::stable_sort(arm64xRelocs, [=](const Arm64XDynamicRelocEntry &a,
1192                                       const Arm64XDynamicRelocEntry &b) {
1193     return a.offset < b.offset;
1194   });
1195
1196   size = sizeof(coff_dynamic_reloc_table) + sizeof(coff_dynamic_relocation64) +
1197          sizeof(coff_base_reloc_block_header);
1198
1199   for (const Arm64XDynamicRelocEntry &entry : arm64xRelocs) {
1200     assert(!(entry.offset & ~0xfff)); // Not yet supported.
1201     size += entry.getSize();
1202   }
1203
1204   size = alignTo(size, sizeof(uint32_t));
1205 }
1206
1207 void DynamicRelocsChunk::writeTo(uint8_t *buf) const {
1208   auto table = reinterpret_cast<coff_dynamic_reloc_table *>(buf);
1209   table->Version = 1;
1210   table->Size = sizeof(coff_dynamic_relocation64);
1211   buf += sizeof(*table);
1212
1213   auto header = reinterpret_cast<coff_dynamic_relocation64 *>(buf);
1214   header->Symbol = IMAGE_DYNAMIC_RELOCATION_ARM64X;
1215   buf += sizeof(*header);
1216
1217   auto pageHeader = reinterpret_cast<coff_base_reloc_block_header *>(buf);
1218   pageHeader->BlockSize = sizeof(*pageHeader);
1219   for (const Arm64XDynamicRelocEntry &entry : arm64xRelocs) {
1220     entry.writeTo(buf + pageHeader->BlockSize);
1221     pageHeader->BlockSize += entry.getSize();
1222   }
1223   pageHeader->BlockSize = alignTo(pageHeader->BlockSize, sizeof(uint32_t));
1224
1225   header->BaseRelocSize = pageHeader->BlockSize;
1226   table->Size += header->BaseRelocSize;
1227   assert(size == sizeof(*table) + sizeof(*header) + header->BaseRelocSize);
1228 }
1229
1230 } // namespace lld::coff