llvm/lib/CodeGen/MachineRegisterInfo.cpp

   1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implementation of the MachineRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineRegisterInfo.h"
  14 #include "llvm/ADT/iterator_range.h"
  15 #include "llvm/CodeGen/LowLevelType.h"
  16 #include "llvm/CodeGen/MachineBasicBlock.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/MachineInstr.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineOperand.h"
  21 #include "llvm/CodeGen/TargetInstrInfo.h"
  22 #include "llvm/CodeGen/TargetRegisterInfo.h"
  23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  24 #include "llvm/Config/llvm-config.h"
  25 #include "llvm/IR/Attributes.h"
  26 #include "llvm/IR/DebugLoc.h"
  27 #include "llvm/IR/Function.h"
  28 #include "llvm/MC/MCRegisterInfo.h"
  29 #include "llvm/Support/Casting.h"
  30 #include "llvm/Support/CommandLine.h"
  31 #include "llvm/Support/Compiler.h"
  32 #include "llvm/Support/ErrorHandling.h"
  33 #include "llvm/Support/raw_ostream.h"
  34 #include <cassert>
  35
  36 using namespace llvm;
  37
  38 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
  39   cl::init(true), cl::desc("Enable subregister liveness tracking."));
  40
  41 // Pin the vtable to this file.
  42 void MachineRegisterInfo::Delegate::anchor() {}
  43
  44 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
  45     : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
  46                                    EnableSubRegLiveness) {
  47   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
  48   VRegInfo.reserve(256);
  49   RegAllocHints.reserve(256);
  50   UsedPhysRegMask.resize(NumRegs);
  51   PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
  52 }
  53
  54 /// setRegClass - Set the register class of the specified virtual register.
  55 ///
  56 void
  57 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {
  58   assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
  59   VRegInfo[Reg].first = RC;
  60 }
  61
  62 void MachineRegisterInfo::setRegBank(Register Reg,
  63                                      const RegisterBank &RegBank) {
  64   VRegInfo[Reg].first = &RegBank;
  65 }
  66
  67 static const TargetRegisterClass *
  68 constrainRegClass(MachineRegisterInfo &MRI, Register Reg,
  69                   const TargetRegisterClass *OldRC,
  70                   const TargetRegisterClass *RC, unsigned MinNumRegs) {
  71   if (OldRC == RC)
  72     return RC;
  73   const TargetRegisterClass *NewRC =
  74       MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
  75   if (!NewRC || NewRC == OldRC)
  76     return NewRC;
  77   if (NewRC->getNumRegs() < MinNumRegs)
  78     return nullptr;
  79   MRI.setRegClass(Reg, NewRC);
  80   return NewRC;
  81 }
  82
  83 const TargetRegisterClass *
  84 MachineRegisterInfo::constrainRegClass(Register Reg,
  85                                        const TargetRegisterClass *RC,
  86                                        unsigned MinNumRegs) {
  87   return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
  88 }
  89
  90 bool
  91 MachineRegisterInfo::constrainRegAttrs(Register Reg,
  92                                        Register ConstrainingReg,
  93                                        unsigned MinNumRegs) {
  94   const LLT RegTy = getType(Reg);
  95   const LLT ConstrainingRegTy = getType(ConstrainingReg);
  96   if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
  97       RegTy != ConstrainingRegTy)
  98     return false;
  99   const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
 100   if (!ConstrainingRegCB.isNull()) {
 101     const auto RegCB = getRegClassOrRegBank(Reg);
 102     if (RegCB.isNull())
 103       setRegClassOrRegBank(Reg, ConstrainingRegCB);
 104     else if (RegCB.is<const TargetRegisterClass *>() !=
 105              ConstrainingRegCB.is<const TargetRegisterClass *>())
 106       return false;
 107     else if (RegCB.is<const TargetRegisterClass *>()) {
 108       if (!::constrainRegClass(
 109               *this, Reg, RegCB.get<const TargetRegisterClass *>(),
 110               ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
 111         return false;
 112     } else if (RegCB != ConstrainingRegCB)
 113       return false;
 114   }
 115   if (ConstrainingRegTy.isValid())
 116     setType(Reg, ConstrainingRegTy);
 117   return true;
 118 }
 119
 120 bool
 121 MachineRegisterInfo::recomputeRegClass(Register Reg) {
 122   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
 123   const TargetRegisterClass *OldRC = getRegClass(Reg);
 124   const TargetRegisterClass *NewRC =
 125       getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
 126
 127   // Stop early if there is no room to grow.
 128   if (NewRC == OldRC)
 129     return false;
 130
 131   // Accumulate constraints from all uses.
 132   for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
 133     // Apply the effect of the given operand to NewRC.
 134     MachineInstr *MI = MO.getParent();
 135     unsigned OpNo = &MO - &MI->getOperand(0);
 136     NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
 137                                             getTargetRegisterInfo());
 138     if (!NewRC || NewRC == OldRC)
 139       return false;
 140   }
 141   setRegClass(Reg, NewRC);
 142   return true;
 143 }
 144
 145 Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
 146   Register Reg = Register::index2VirtReg(getNumVirtRegs());
 147   VRegInfo.grow(Reg);
 148   RegAllocHints.grow(Reg);
 149   insertVRegByName(Name, Reg);
 150   return Reg;
 151 }
 152
 153 /// createVirtualRegister - Create and return a new virtual register in the
 154 /// function with the specified register class.
 155 ///
 156 Register
 157 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
 158                                            StringRef Name) {
 159   assert(RegClass && "Cannot create register without RegClass!");
 160   assert(RegClass->isAllocatable() &&
 161          "Virtual register RegClass must be allocatable.");
 162
 163   // New virtual register number.
 164   Register Reg = createIncompleteVirtualRegister(Name);
 165   VRegInfo[Reg].first = RegClass;
 166   if (TheDelegate)
 167     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
 168   return Reg;
 169 }
 170
 171 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
 172                                                    StringRef Name) {
 173   Register Reg = createIncompleteVirtualRegister(Name);
 174   VRegInfo[Reg].first = VRegInfo[VReg].first;
 175   setType(Reg, getType(VReg));
 176   if (TheDelegate)
 177     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
 178   return Reg;
 179 }
 180
 181 void MachineRegisterInfo::setType(Register VReg, LLT Ty) {
 182   VRegToType.grow(VReg);
 183   VRegToType[VReg] = Ty;
 184 }
 185
 186 Register
 187 MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
 188   // New virtual register number.
 189   Register Reg = createIncompleteVirtualRegister(Name);
 190   // FIXME: Should we use a dummy register class?
 191   VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
 192   setType(Reg, Ty);
 193   if (TheDelegate)
 194     TheDelegate->MRI_NoteNewVirtualRegister(Reg);
 195   return Reg;
 196 }
 197
 198 void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
 199
 200 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
 201 void MachineRegisterInfo::clearVirtRegs() {
 202 #ifndef NDEBUG
 203   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
 204     Register Reg = Register::index2VirtReg(i);
 205     if (!VRegInfo[Reg].second)
 206       continue;
 207     verifyUseList(Reg);
 208     llvm_unreachable("Remaining virtual register operands");
 209   }
 210 #endif
 211   VRegInfo.clear();
 212   for (auto &I : LiveIns)
 213     I.second = 0;
 214 }
 215
 216 void MachineRegisterInfo::verifyUseList(Register Reg) const {
 217 #ifndef NDEBUG
 218   bool Valid = true;
 219   for (MachineOperand &M : reg_operands(Reg)) {
 220     MachineOperand *MO = &M;
 221     MachineInstr *MI = MO->getParent();
 222     if (!MI) {
 223       errs() << printReg(Reg, getTargetRegisterInfo())
 224              << " use list MachineOperand " << MO
 225              << " has no parent instruction.\n";
 226       Valid = false;
 227       continue;
 228     }
 229     MachineOperand *MO0 = &MI->getOperand(0);
 230     unsigned NumOps = MI->getNumOperands();
 231     if (!(MO >= MO0 && MO < MO0+NumOps)) {
 232       errs() << printReg(Reg, getTargetRegisterInfo())
 233              << " use list MachineOperand " << MO
 234              << " doesn't belong to parent MI: " << *MI;
 235       Valid = false;
 236     }
 237     if (!MO->isReg()) {
 238       errs() << printReg(Reg, getTargetRegisterInfo())
 239              << " MachineOperand " << MO << ": " << *MO
 240              << " is not a register\n";
 241       Valid = false;
 242     }
 243     if (MO->getReg() != Reg) {
 244       errs() << printReg(Reg, getTargetRegisterInfo())
 245              << " use-list MachineOperand " << MO << ": "
 246              << *MO << " is the wrong register\n";
 247       Valid = false;
 248     }
 249   }
 250   assert(Valid && "Invalid use list");
 251 #endif
 252 }
 253
 254 void MachineRegisterInfo::verifyUseLists() const {
 255 #ifndef NDEBUG
 256   for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
 257     verifyUseList(Register::index2VirtReg(i));
 258   for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
 259     verifyUseList(i);
 260 #endif
 261 }
 262
 263 /// Add MO to the linked list of operands for its register.
 264 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
 265   assert(!MO->isOnRegUseList() && "Already on list");
 266   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 267   MachineOperand *const Head = HeadRef;
 268
 269   // Head points to the first list element.
 270   // Next is NULL on the last list element.
 271   // Prev pointers are circular, so Head->Prev == Last.
 272
 273   // Head is NULL for an empty list.
 274   if (!Head) {
 275     MO->Contents.Reg.Prev = MO;
 276     MO->Contents.Reg.Next = nullptr;
 277     HeadRef = MO;
 278     return;
 279   }
 280   assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
 281
 282   // Insert MO between Last and Head in the circular Prev chain.
 283   MachineOperand *Last = Head->Contents.Reg.Prev;
 284   assert(Last && "Inconsistent use list");
 285   assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
 286   Head->Contents.Reg.Prev = MO;
 287   MO->Contents.Reg.Prev = Last;
 288
 289   // Def operands always precede uses. This allows def_iterator to stop early.
 290   // Insert def operands at the front, and use operands at the back.
 291   if (MO->isDef()) {
 292     // Insert def at the front.
 293     MO->Contents.Reg.Next = Head;
 294     HeadRef = MO;
 295   } else {
 296     // Insert use at the end.
 297     MO->Contents.Reg.Next = nullptr;
 298     Last->Contents.Reg.Next = MO;
 299   }
 300 }
 301
 302 /// Remove MO from its use-def list.
 303 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
 304   assert(MO->isOnRegUseList() && "Operand not on use list");
 305   MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
 306   MachineOperand *const Head = HeadRef;
 307   assert(Head && "List already empty");
 308
 309   // Unlink this from the doubly linked list of operands.
 310   MachineOperand *Next = MO->Contents.Reg.Next;
 311   MachineOperand *Prev = MO->Contents.Reg.Prev;
 312
 313   // Prev links are circular, next link is NULL instead of looping back to Head.
 314   if (MO == Head)
 315     HeadRef = Next;
 316   else
 317     Prev->Contents.Reg.Next = Next;
 318
 319   (Next ? Next : Head)->Contents.Reg.Prev = Prev;
 320
 321   MO->Contents.Reg.Prev = nullptr;
 322   MO->Contents.Reg.Next = nullptr;
 323 }
 324
 325 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
 326 ///
 327 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
 328 /// operands that won't be destroyed, which is OK because the MO destructor is
 329 /// trivial anyway).
 330 ///
 331 /// The Src and Dst ranges may overlap.
 332 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
 333                                        MachineOperand *Src,
 334                                        unsigned NumOps) {
 335   assert(Src != Dst && NumOps && "Noop moveOperands");
 336
 337   // Copy backwards if Dst is within the Src range.
 338   int Stride = 1;
 339   if (Dst >= Src && Dst < Src + NumOps) {
 340     Stride = -1;
 341     Dst += NumOps - 1;
 342     Src += NumOps - 1;
 343   }
 344
 345   // Copy one operand at a time.
 346   do {
 347     new (Dst) MachineOperand(*Src);
 348
 349     // Dst takes Src's place in the use-def chain.
 350     if (Src->isReg()) {
 351       MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
 352       MachineOperand *Prev = Src->Contents.Reg.Prev;
 353       MachineOperand *Next = Src->Contents.Reg.Next;
 354       assert(Head && "List empty, but operand is chained");
 355       assert(Prev && "Operand was not on use-def list");
 356
 357       // Prev links are circular, next link is NULL instead of looping back to
 358       // Head.
 359       if (Src == Head)
 360         Head = Dst;
 361       else
 362         Prev->Contents.Reg.Next = Dst;
 363
 364       // Update Prev pointer. This also works when Src was pointing to itself
 365       // in a 1-element list. In that case Head == Dst.
 366       (Next ? Next : Head)->Contents.Reg.Prev = Dst;
 367     }
 368
 369     Dst += Stride;
 370     Src += Stride;
 371   } while (--NumOps);
 372 }
 373
 374 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
 375 /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
 376 /// except that it also changes any definitions of the register as well.
 377 /// If ToReg is a physical register we apply the sub register to obtain the
 378 /// final/proper physical register.
 379 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {
 380   assert(FromReg != ToReg && "Cannot replace a reg with itself");
 381
 382   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 383
 384   // TODO: This could be more efficient by bulk changing the operands.
 385   for (MachineOperand &O : llvm::make_early_inc_range(reg_operands(FromReg))) {
 386     if (Register::isPhysicalRegister(ToReg)) {
 387       O.substPhysReg(ToReg, *TRI);
 388     } else {
 389       O.setReg(ToReg);
 390     }
 391   }
 392 }
 393
 394 /// getVRegDef - Return the machine instr that defines the specified virtual
 395 /// register or null if none is found.  This assumes that the code is in SSA
 396 /// form, so there should only be one definition.
 397 MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {
 398   // Since we are in SSA form, we can use the first definition.
 399   def_instr_iterator I = def_instr_begin(Reg);
 400   assert((I.atEnd() || std::next(I) == def_instr_end()) &&
 401          "getVRegDef assumes a single definition or no definition");
 402   return !I.atEnd() ? &*I : nullptr;
 403 }
 404
 405 /// getUniqueVRegDef - Return the unique machine instr that defines the
 406 /// specified virtual register or null if none is found.  If there are
 407 /// multiple definitions or no definition, return null.
 408 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {
 409   if (def_empty(Reg)) return nullptr;
 410   def_instr_iterator I = def_instr_begin(Reg);
 411   if (std::next(I) != def_instr_end())
 412     return nullptr;
 413   return &*I;
 414 }
 415
 416 bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {
 417   return hasSingleElement(use_nodbg_operands(RegNo));
 418 }
 419
 420 bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {
 421   return hasSingleElement(use_nodbg_instructions(RegNo));
 422 }
 423
 424 /// clearKillFlags - Iterate over all the uses of the given register and
 425 /// clear the kill flag from the MachineOperand. This function is used by
 426 /// optimization passes which extend register lifetimes and need only
 427 /// preserve conservative kill flag information.
 428 void MachineRegisterInfo::clearKillFlags(Register Reg) const {
 429   for (MachineOperand &MO : use_operands(Reg))
 430     MO.setIsKill(false);
 431 }
 432
 433 bool MachineRegisterInfo::isLiveIn(Register Reg) const {
 434   for (const std::pair<MCRegister, Register> &LI : liveins())
 435     if ((Register)LI.first == Reg || LI.second == Reg)
 436       return true;
 437   return false;
 438 }
 439
 440 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
 441 /// corresponding live-in physical register.
 442 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
 443   for (const std::pair<MCRegister, Register> &LI : liveins())
 444     if (LI.second == VReg)
 445       return LI.first;
 446   return MCRegister();
 447 }
 448
 449 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
 450 /// corresponding live-in physical register.
 451 Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
 452   for (const std::pair<MCRegister, Register> &LI : liveins())
 453     if (LI.first == PReg)
 454       return LI.second;
 455   return Register();
 456 }
 457
 458 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
 459 /// into the given entry block.
 460 void
 461 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 462                                       const TargetRegisterInfo &TRI,
 463                                       const TargetInstrInfo &TII) {
 464   // Emit the copies into the top of the block.
 465   for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
 466     if (LiveIns[i].second) {
 467       if (use_nodbg_empty(LiveIns[i].second)) {
 468         // The livein has no non-dbg uses. Drop it.
 469         //
 470         // It would be preferable to have isel avoid creating live-in
 471         // records for unused arguments in the first place, but it's
 472         // complicated by the debug info code for arguments.
 473         LiveIns.erase(LiveIns.begin() + i);
 474         --i; --e;
 475       } else {
 476         // Emit a copy.
 477         BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
 478                 TII.get(TargetOpcode::COPY), LiveIns[i].second)
 479           .addReg(LiveIns[i].first);
 480
 481         // Add the register to the entry block live-in set.
 482         EntryMBB->addLiveIn(LiveIns[i].first);
 483       }
 484     } else {
 485       // Add the register to the entry block live-in set.
 486       EntryMBB->addLiveIn(LiveIns[i].first);
 487     }
 488 }
 489
 490 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
 491   // Lane masks are only defined for vregs.
 492   assert(Register::isVirtualRegister(Reg));
 493   const TargetRegisterClass &TRC = *getRegClass(Reg);
 494   return TRC.getLaneMask();
 495 }
 496
 497 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 498 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
 499   for (MachineInstr &I : use_instructions(Reg))
 500     I.dump();
 501 }
 502 #endif
 503
 504 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
 505   ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
 506   assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
 507          "Invalid ReservedRegs vector from target");
 508 }
 509
 510 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
 511   assert(Register::isPhysicalRegister(PhysReg));
 512
 513   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 514   if (TRI->isConstantPhysReg(PhysReg))
 515     return true;
 516
 517   // Check if any overlapping register is modified, or allocatable so it may be
 518   // used later.
 519   for (MCRegAliasIterator AI(PhysReg, TRI, true);
 520        AI.isValid(); ++AI)
 521     if (!def_empty(*AI) || isAllocatable(*AI))
 522       return false;
 523   return true;
 524 }
 525
 526 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
 527 /// specified register as undefined which causes the DBG_VALUE to be
 528 /// deleted during LiveDebugVariables analysis.
 529 void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
 530   // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
 531   // We use make_early_inc_range because setReg invalidates the iterator.
 532   for (MachineInstr &UseMI : llvm::make_early_inc_range(use_instructions(Reg))) {
 533     if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
 534       UseMI.setDebugValueUndef();
 535   }
 536 }
 537
 538 static const Function *getCalledFunction(const MachineInstr &MI) {
 539   for (const MachineOperand &MO : MI.operands()) {
 540     if (!MO.isGlobal())
 541       continue;
 542     const Function *Func = dyn_cast<Function>(MO.getGlobal());
 543     if (Func != nullptr)
 544       return Func;
 545   }
 546   return nullptr;
 547 }
 548
 549 static bool isNoReturnDef(const MachineOperand &MO) {
 550   // Anything which is not a noreturn function is a real def.
 551   const MachineInstr &MI = *MO.getParent();
 552   if (!MI.isCall())
 553     return false;
 554   const MachineBasicBlock &MBB = *MI.getParent();
 555   if (!MBB.succ_empty())
 556     return false;
 557   const MachineFunction &MF = *MBB.getParent();
 558   // We need to keep correct unwind information even if the function will
 559   // not return, since the runtime may need it.
 560   if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
 561     return false;
 562   const Function *Called = getCalledFunction(MI);
 563   return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||
 564            !Called->hasFnAttribute(Attribute::NoUnwind));
 565 }
 566
 567 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
 568                                             bool SkipNoReturnDef) const {
 569   if (UsedPhysRegMask.test(PhysReg))
 570     return true;
 571   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 572   for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
 573     for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
 574       if (!SkipNoReturnDef && isNoReturnDef(MO))
 575         continue;
 576       return true;
 577     }
 578   }
 579   return false;
 580 }
 581
 582 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,
 583                                         bool SkipRegMaskTest) const {
 584   if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg))
 585     return true;
 586   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 587   for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
 588        ++AliasReg) {
 589     if (!reg_nodbg_empty(*AliasReg))
 590       return true;
 591   }
 592   return false;
 593 }
 594
 595 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) {
 596
 597   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 598   assert(Reg && (Reg < TRI->getNumRegs()) &&
 599          "Trying to disable an invalid register");
 600
 601   if (!IsUpdatedCSRsInitialized) {
 602     const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
 603     for (const MCPhysReg *I = CSR; *I; ++I)
 604       UpdatedCSRs.push_back(*I);
 605
 606     // Zero value represents the end of the register list
 607     // (no more registers should be pushed).
 608     UpdatedCSRs.push_back(0);
 609
 610     IsUpdatedCSRsInitialized = true;
 611   }
 612
 613   // Remove the register (and its aliases from the list).
 614   for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
 615     llvm::erase_value(UpdatedCSRs, *AI);
 616 }
 617
 618 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
 619   if (IsUpdatedCSRsInitialized)
 620     return UpdatedCSRs.data();
 621
 622   return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
 623 }
 624
 625 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
 626   if (IsUpdatedCSRsInitialized)
 627     UpdatedCSRs.clear();
 628
 629   append_range(UpdatedCSRs, CSRs);
 630
 631   // Zero value represents the end of the register list
 632   // (no more registers should be pushed).
 633   UpdatedCSRs.push_back(0);
 634   IsUpdatedCSRsInitialized = true;
 635 }
 636
 637 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
 638   const TargetRegisterInfo *TRI = getTargetRegisterInfo();
 639   for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
 640     bool IsRootReserved = true;
 641     for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
 642          Super.isValid(); ++Super) {
 643       MCRegister Reg = *Super;
 644       if (!isReserved(Reg)) {
 645         IsRootReserved = false;
 646         break;
 647       }
 648     }
 649     if (IsRootReserved)
 650       return true;
 651   }
 652   return false;
 653 }
 654
 655 bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF,
 656                                              MCRegister Reg) const {
 657   return getTargetRegisterInfo()->isArgumentRegister(MF, Reg);
 658 }
 659
 660 bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF,
 661                                           MCRegister Reg) const {
 662   return getTargetRegisterInfo()->isFixedRegister(MF, Reg);
 663 }
 664
 665 bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF,
 666                                                    MCRegister Reg) const {
 667   return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg);
 668 }