llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

   1 //=- AArch64SchedExynosM4.td - Samsung Exynos M4 Sched Defs --*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for the Samsung Exynos M4 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // The Exynos-M4 is an advanced superscalar microprocessor with a 6-wide
  16 // in-order stage for decode and dispatch and a wider issue stage.
  17 // The execution units and loads and stores are out-of-order.
  18
  19 def ExynosM4Model : SchedMachineModel {
  20   let IssueWidth            =   6; // Up to 6 uops per cycle.
  21   let MicroOpBufferSize     = 228; // ROB size.
  22   let LoopMicroOpBufferSize =  48; // Based on the instruction queue size.
  23   let LoadLatency           =   4; // Optimistic load cases.
  24   let MispredictPenalty     =  16; // Minimum branch misprediction penalty.
  25   let CompleteModel         =   1; // Use the default model otherwise.
  26
  27   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
  28                                                     PAUnsupported.F,
  29                                                     SMEUnsupported.F);
  30 }
  31
  32 //===----------------------------------------------------------------------===//
  33 // Define each kind of processor resource and number available on the Exynos-M4.
  34
  35 let SchedModel = ExynosM4Model in {
  36
  37 def M4UnitA  : ProcResource<2>; // Simple integer
  38 def M4UnitC  : ProcResource<2>; // Simple and complex integer
  39 let Super =  M4UnitC, BufferSize = 1 in
  40 def M4UnitD  : ProcResource<1>; // Integer division (inside C0, serialized)
  41 let Super =  M4UnitC in
  42 def M4UnitE  : ProcResource<1>; // CRC (inside C0)
  43 def M4UnitB  : ProcResource<2>; // Branch
  44 def M4UnitL0 : ProcResource<1>; // Load
  45 def M4UnitS0 : ProcResource<1>; // Store
  46 def M4PipeLS : ProcResource<1>; // Load/Store
  47 let Super = M4PipeLS in {
  48   def M4UnitL1 : ProcResource<1>;
  49   def M4UnitS1 : ProcResource<1>;
  50 }
  51 def M4PipeF0 : ProcResource<1>; // FP #0
  52 let Super = M4PipeF0 in {
  53   def M4UnitFMAC0 : ProcResource<1>; // FP multiplication
  54   def M4UnitFADD0 : ProcResource<1>; // Simple FP
  55   def M4UnitFCVT0 : ProcResource<1>; // FP conversion
  56   def M4UnitNALU0 : ProcResource<1>; // Simple vector
  57   def M4UnitNHAD  : ProcResource<1>; // Horizontal vector
  58   def M4UnitNMSC  : ProcResource<1>; // FP and vector miscellanea
  59   def M4UnitNMUL0 : ProcResource<1>; // Vector multiplication
  60   def M4UnitNSHT0 : ProcResource<1>; // Vector shifting
  61   def M4UnitNSHF0 : ProcResource<1>; // Vector shuffling
  62   def M4UnitNCRY0 : ProcResource<1>; // Cryptographic
  63 }
  64 def M4PipeF1 : ProcResource<1>; // FP #1
  65 let Super = M4PipeF1 in {
  66   def M4UnitFMAC1 : ProcResource<1>; // FP multiplication
  67   def M4UnitFADD1 : ProcResource<1>; // Simple FP
  68   def M4UnitFDIV0 : ProcResource<2>; // FP division (serialized)
  69   def M4UnitFSQR0 : ProcResource<2>; // FP square root (serialized)
  70   def M4UnitFST0  : ProcResource<1>; // FP store
  71   def M4UnitNALU1 : ProcResource<1>; // Simple vector
  72   def M4UnitNSHT1 : ProcResource<1>; // Vector shifting
  73   def M4UnitNSHF1 : ProcResource<1>; // Vector shuffling
  74 }
  75 def M4PipeF2 : ProcResource<1>; // FP #2
  76 let Super = M4PipeF2 in {
  77   def M4UnitFMAC2 : ProcResource<1>; // FP multiplication
  78   def M4UnitFADD2 : ProcResource<1>; // Simple FP
  79   def M4UnitFCVT1 : ProcResource<1>; // FP conversion
  80   def M4UnitFDIV1 : ProcResource<2>; // FP division (serialized)
  81   def M4UnitFSQR1 : ProcResource<2>; // FP square root (serialized)
  82   def M4UnitFST1  : ProcResource<1>; // FP store
  83   def M4UnitNALU2 : ProcResource<1>; // Simple vector
  84   def M4UnitNMUL1 : ProcResource<1>; // Vector multiplication
  85   def M4UnitNSHT2 : ProcResource<1>; // Vector shifting
  86   def M4UnitNCRY1 : ProcResource<1>; // Cryptographic
  87 }
  88
  89 def M4UnitALU   : ProcResGroup<[M4UnitA,
  90                                 M4UnitC]>;
  91 def M4UnitL     : ProcResGroup<[M4UnitL0,
  92                                 M4UnitL1]>;
  93 def M4UnitS     : ProcResGroup<[M4UnitS0,
  94                                 M4UnitS1]>;
  95 def M4UnitFMAC  : ProcResGroup<[M4UnitFMAC0,
  96                                 M4UnitFMAC1,
  97                                 M4UnitFMAC2]>;
  98 def M4UnitFMACH : ProcResGroup<[M4UnitFMAC0,
  99                                 M4UnitFMAC1]>;
 100 def M4UnitFADD  : ProcResGroup<[M4UnitFADD0,
 101                                 M4UnitFADD1,
 102                                 M4UnitFADD2]>;
 103 def M4UnitFADDH : ProcResGroup<[M4UnitFADD0,
 104                                 M4UnitFADD1]>;
 105 def M4UnitFCVT  : ProcResGroup<[M4UnitFCVT0,
 106                                 M4UnitFCVT1]>;
 107 def M4UnitFCVTH : ProcResGroup<[M4UnitFCVT0]>;
 108 def M4UnitFDIV  : ProcResGroup<[M4UnitFDIV0,
 109                                 M4UnitFDIV1]>;
 110 def M4UnitFDIVH : ProcResGroup<[M4UnitFDIV0]>;
 111 def M4UnitFSQR  : ProcResGroup<[M4UnitFSQR0,
 112                                 M4UnitFSQR1]>;
 113 def M4UnitFSQRH : ProcResGroup<[M4UnitFSQR0]>;
 114 def M4UnitFST   : ProcResGroup<[M4UnitFST0,
 115                                 M4UnitFST1]>;
 116 def M4UnitNALU  : ProcResGroup<[M4UnitNALU0,
 117                                 M4UnitNALU1,
 118                                 M4UnitNALU2]>;
 119 def M4UnitNALUH : ProcResGroup<[M4UnitNALU0,
 120                                 M4UnitNALU1]>;
 121 def M4UnitNMUL  : ProcResGroup<[M4UnitNMUL0,
 122                                 M4UnitNMUL1]>;
 123 def M4UnitNSHT  : ProcResGroup<[M4UnitNSHT0,
 124                                 M4UnitNSHT1,
 125                                 M4UnitNSHT2]>;
 126 def M4UnitNSHF  : ProcResGroup<[M4UnitNSHF0,
 127                                 M4UnitNSHF1]>;
 128 def M4UnitNSHFH : ProcResGroup<[M4UnitNSHF0]>;
 129 def M4UnitNCRY  : ProcResGroup<[M4UnitNCRY0,
 130                                 M4UnitNCRY1]>;
 131
 132 //===----------------------------------------------------------------------===//
 133 // Resources details.
 134
 135 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
 136 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
 137                                     let NumMicroOps = 0; }
 138 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
 139                                     let NumMicroOps = 0; }
 140
 141 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
 142 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
 143 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
 144                                              let ResourceCycles = [2]; }
 145 def M4WriteAB : SchedWriteRes<[M4UnitALU,
 146                                M4UnitC]>   { let Latency = 2;
 147                                              let NumMicroOps = 2; }
 148 def M4WriteAC : SchedWriteRes<[M4UnitALU,
 149                                M4UnitALU,
 150                                M4UnitC]>   { let Latency = 3;
 151                                              let NumMicroOps = 3; }
 152 def M4WriteAD : SchedWriteRes<[M4UnitALU,
 153                                M4UnitC]>   { let Latency = 2;
 154                                              let NumMicroOps = 2; }
 155 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
 156                                              let NumMicroOps = 2; }
 157 def M4WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred,   [M4WriteZ0]>,
 158                                    SchedVar<ExynosArithPred,   [M4WriteA1]>,
 159                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 160                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 161 def M4WriteAV : SchedWriteVariant<[SchedVar<ExynosResetPred,   [M4WriteZ0]>,
 162                                    SchedVar<ExynosArithPred,   [M4WriteA1]>,
 163                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 164                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 165 def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M4WriteA1]>,
 166                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
 167                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
 168 def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>,
 169                                    SchedVar<NoSchedPred,              [M4WriteAF]>]>;
 170
 171 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
 172 def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>,
 173                                    SchedVar<NoSchedPred,            [M4WriteAB]>]>;
 174
 175 def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
 176 def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
 177 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
 178                                            let ResourceCycles = [2]; }
 179
 180 def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
 181                                             let ResourceCycles = [12]; }
 182 def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
 183                                             let ResourceCycles = [21]; }
 184
 185 def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
 186
 187 def M4WriteL4 : SchedWriteRes<[M4UnitL]> { let Latency = 4; }
 188 def M4WriteL5 : SchedWriteRes<[M4UnitL]> { let Latency = 5; }
 189 def M4WriteLA : SchedWriteRes<[M4UnitL,
 190                                M4UnitL]> { let Latency = 5;
 191                                            let NumMicroOps = 1; }
 192 def M4WriteLB : SchedWriteRes<[M4UnitA,
 193                                M4UnitL]> { let Latency = 5;
 194                                            let NumMicroOps = 2; }
 195 def M4WriteLC : SchedWriteRes<[M4UnitA,
 196                                M4UnitL,
 197                                M4UnitL]> { let Latency = 5;
 198                                            let NumMicroOps = 2; }
 199 def M4WriteLD : SchedWriteRes<[M4UnitA,
 200                                M4UnitL]> { let Latency = 4;
 201                                            let NumMicroOps = 2; }
 202 def M4WriteLE : SchedWriteRes<[M4UnitA,
 203                                M4UnitL]> { let Latency = 6;
 204                                            let NumMicroOps = 2; }
 205 def M4WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 206                                            let NumMicroOps = 0; }
 207 def M4WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteL5]>,
 208                                    SchedVar<NoSchedPred,         [M4WriteL4]>]>;
 209 def M4WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteLE]>,
 210                                    SchedVar<NoSchedPred,         [M4WriteL5]>]>;
 211
 212 def M4WriteS1 : SchedWriteRes<[M4UnitS]>  { let Latency = 1; }
 213 def M4WriteSA : SchedWriteRes<[M4UnitS0]> { let Latency = 3; }
 214 def M4WriteSB : SchedWriteRes<[M4UnitA,
 215                                M4UnitS]>  { let Latency = 2;
 216                                             let NumMicroOps = 1; }
 217 def M4WriteSX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteSB]>,
 218                                    SchedVar<NoSchedPred,         [M4WriteS1]>]>;
 219
 220 def M4ReadAdrBase : SchedReadVariant<[SchedVar<
 221                                         MCSchedPredicate<
 222                                           CheckAny<
 223                                             [ScaledIdxFn,
 224                                              ExynosScaledIdxFn]>>, [ReadDefault]>,
 225                                       SchedVar<NoSchedPred,        [ReadDefault]>]>;
 226
 227 def M4WriteNEONA   : SchedWriteRes<[M4UnitNSHF,
 228                                     M4UnitFADD]>  { let Latency = 3;
 229                                                     let NumMicroOps = 2; }
 230 def M4WriteNEONB   : SchedWriteRes<[M4UnitNALU,
 231                                     M4UnitS0]>    { let Latency = 5;
 232                                                     let NumMicroOps = 2; }
 233 def M4WriteNEOND   : SchedWriteRes<[M4UnitNSHF,
 234                                     M4UnitFST]>   { let Latency = 6;
 235                                                     let NumMicroOps = 2; }
 236 def M4WriteNEONH   : SchedWriteRes<[M4UnitNALU,
 237                                     M4UnitS0]>    { let Latency = 5;
 238                                                     let NumMicroOps = 2; }
 239 def M4WriteNEONI   : SchedWriteRes<[M4UnitNSHF,
 240                                     M4UnitS0]>    { let Latency = 2;
 241                                                     let NumMicroOps = 2; }
 242 def M4WriteNEONJ   : SchedWriteRes<[M4UnitNMSC,
 243                                     M4UnitS0]>    { let Latency = 4; }
 244 def M4WriteNEONK   : SchedWriteRes<[M4UnitNSHF,
 245                                     M4UnitNMSC,
 246                                     M4UnitS0]>    { let Latency = 5;
 247                                                     let NumMicroOps = 2; }
 248 def M4WriteNEONL   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 249 def M4WriteNEONN   : SchedWriteRes<[M4UnitNMSC,
 250                                     M4UnitNMSC]>  { let Latency = 5;
 251                                                     let NumMicroOps = 2; }
 252 def M4WriteNEONO   : SchedWriteRes<[M4UnitNMSC,
 253                                     M4UnitNMSC,
 254                                     M4UnitNMSC]>  { let Latency = 8;
 255                                                     let NumMicroOps = 3; }
 256 def M4WriteNEONP   : SchedWriteRes<[M4UnitNSHF,
 257                                     M4UnitNMSC]>  { let Latency = 4;
 258                                                     let NumMicroOps = 2; }
 259 def M4WriteNEONQ   : SchedWriteRes<[M4UnitNMSC,
 260                                     M4UnitC]>     { let Latency = 3;
 261                                                     let NumMicroOps = 1; }
 262 def M4WriteNEONR   : SchedWriteRes<[M4UnitFCVT0,
 263                                     M4UnitS0]>    { let Latency = 4;
 264                                                     let NumMicroOps = 1; }
 265 def M4WriteNEONV   : SchedWriteRes<[M4UnitFDIV,
 266                                     M4UnitFDIV]>  { let Latency = 7;
 267                                                     let ResourceCycles = [6, 6]; }
 268 def M4WriteNEONVH  : SchedWriteRes<[M4UnitFDIVH,
 269                                     M4UnitFDIVH]> { let Latency = 7;
 270                                                     let ResourceCycles = [6, 6]; }
 271 def M4WriteNEONW   : SchedWriteRes<[M4UnitFDIV,
 272                                     M4UnitFDIV]>  { let Latency = 12;
 273                                                     let ResourceCycles = [9, 9]; }
 274 def M4WriteNEONX   : SchedWriteRes<[M4UnitFSQR,
 275                                     M4UnitFSQR]>  { let Latency = 8;
 276                                                     let ResourceCycles = [7, 7]; }
 277 def M4WriteNEONXH  : SchedWriteRes<[M4UnitFSQRH,
 278                                     M4UnitFSQRH]> { let Latency = 7;
 279                                                     let ResourceCycles = [6, 6]; }
 280 def M4WriteNEONY   : SchedWriteRes<[M4UnitFSQR,
 281                                     M4UnitFSQR]>  { let Latency = 12;
 282                                                     let ResourceCycles = [9, 9]; }
 283 def M4WriteNEONZ   : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>,
 284                                         SchedVar<NoSchedPred,     [M4WriteNEONN]>]>;
 285
 286 def M4WriteFADD2   : SchedWriteRes<[M4UnitFADD]>  { let Latency = 2; }
 287 def M4WriteFADD2H  : SchedWriteRes<[M4UnitFADDH]> { let Latency = 2; }
 288
 289 def M4WriteFCVT2   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 2; }
 290 def M4WriteFCVT2A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 2; }
 291 def M4WriteFCVT2H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 2; }
 292 def M4WriteFCVT3   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 3; }
 293 def M4WriteFCVT3A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 3; }
 294 def M4WriteFCVT3H  : SchedWriteRes<[M4UnitFCVTH]> { let Latency = 3; }
 295 def M4WriteFCVT4   : SchedWriteRes<[M4UnitFCVT]>  { let Latency = 4; }
 296 def M4WriteFCVT4A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
 297 def M4WriteFCVT6A  : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
 298
 299 def M4WriteFDIV7   : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 7;
 300                                                     let ResourceCycles = [6]; }
 301 def M4WriteFDIV7H  : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
 302                                                     let ResourceCycles = [6]; }
 303 def M4WriteFDIV12  : SchedWriteRes<[M4UnitFDIV]>  { let Latency = 12;
 304                                                     let ResourceCycles = [9]; }
 305
 306 def M4WriteFMAC2H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
 307 def M4WriteFMAC3H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
 308 def M4WriteFMAC3   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 3; }
 309 def M4WriteFMAC4   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 4; }
 310 def M4WriteFMAC4H  : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
 311 def M4WriteFMAC5   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 5; }
 312
 313 def M4WriteFSQR7H  : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
 314                                                     let ResourceCycles = [6]; }
 315 def M4WriteFSQR8   : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 8;
 316                                                     let ResourceCycles = [7]; }
 317 def M4WriteFSQR12  : SchedWriteRes<[M4UnitFSQR]>  { let Latency = 12;
 318                                                     let ResourceCycles = [9]; }
 319
 320 def M4WriteNALU1   : SchedWriteRes<[M4UnitNALU]>  { let Latency = 1; }
 321 def M4WriteNALU1H  : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
 322
 323 def M4WriteNCRY1   : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 1; }
 324 def M4WriteNCRY1A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 1; }
 325 def M4WriteNCRY3A  : SchedWriteRes<[M4UnitNCRY0]> { let Latency = 3; }
 326 def M4WriteNCRY5A  : SchedWriteRes<[M4UnitNCRY]>  { let Latency = 5; }
 327
 328 def M4WriteNHAD1   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 1; }
 329 def M4WriteNHAD3   : SchedWriteRes<[M4UnitNHAD]>  { let Latency = 3; }
 330
 331 def M4WriteNMSC1   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 1; }
 332 def M4WriteNMSC2   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 2; }
 333 def M4WriteNMSC3   : SchedWriteRes<[M4UnitNMSC]>  { let Latency = 3; }
 334
 335 def M4WriteNMUL3   : SchedWriteRes<[M4UnitNMUL]>  { let Latency = 3; }
 336
 337 def M4WriteNSHF1   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1; }
 338 def M4WriteNSHF1H  : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
 339 def M4WriteNSHF3   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3; }
 340 def M4WriteNSHFA   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 1;
 341                                                     let ResourceCycles = [2]; }
 342 def M4WriteNSHFB   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 2;
 343                                                     let NumMicroOps = 2;
 344                                                     let ResourceCycles = [2]; }
 345 def M4WriteNSHFC   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 3;
 346                                                     let NumMicroOps = 3;
 347                                                     let ResourceCycles = [4]; }
 348 def M4WriteNSHFD   : SchedWriteRes<[M4UnitNSHF]>  { let Latency = 4;
 349                                                     let NumMicroOps = 4;
 350                                                     let ResourceCycles = [4]; }
 351
 352 def M4WriteNSHT1   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 1; }
 353 def M4WriteNSHT2   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 2; }
 354 def M4WriteNSHT3   : SchedWriteRes<[M4UnitNSHT]>  { let Latency = 3; }
 355 def M4WriteNSHT4A  : SchedWriteRes<[M4UnitNSHT1]> { let Latency = 4; }
 356
 357 def M4WriteVLDA    : SchedWriteRes<[M4UnitL,
 358                                     M4UnitL]>     { let Latency = 5;
 359                                                     let NumMicroOps = 2; }
 360 def M4WriteVLDB    : SchedWriteRes<[M4UnitL,
 361                                     M4UnitL,
 362                                     M4UnitL]>     { let Latency = 6;
 363                                                     let NumMicroOps = 3; }
 364 def M4WriteVLDC    : SchedWriteRes<[M4UnitL,
 365                                     M4UnitL,
 366                                     M4UnitL,
 367                                     M4UnitL]>     { let Latency = 6;
 368                                                     let NumMicroOps = 4; }
 369 def M4WriteVLDD    : SchedWriteRes<[M4UnitL,
 370                                     M4UnitNSHF]>  { let Latency = 6;
 371                                                     let NumMicroOps = 2;
 372                                                     let ResourceCycles = [2, 1]; }
 373 def M4WriteVLDF    : SchedWriteRes<[M4UnitL,
 374                                     M4UnitL]>     { let Latency = 10;
 375                                                     let NumMicroOps = 2;
 376                                                     let ResourceCycles = [3, 3]; }
 377 def M4WriteVLDG    : SchedWriteRes<[M4UnitL,
 378                                     M4UnitNSHF,
 379                                     M4UnitNSHF]>  { let Latency = 6;
 380                                                     let NumMicroOps = 3;
 381                                                     let ResourceCycles = [2, 1, 1]; }
 382 def M4WriteVLDI    : SchedWriteRes<[M4UnitL,
 383                                     M4UnitL,
 384                                     M4UnitL]>     { let Latency = 12;
 385                                                     let NumMicroOps = 3;
 386                                                     let ResourceCycles = [3, 3, 3]; }
 387 def M4WriteVLDJ    : SchedWriteRes<[M4UnitL,
 388                                     M4UnitNSHF,
 389                                     M4UnitNSHF,
 390                                     M4UnitNSHF]>  { let Latency = 7;
 391                                                     let NumMicroOps = 4;
 392                                                     let ResourceCycles = [3, 1, 1, 1]; }
 393 def M4WriteVLDK    : SchedWriteRes<[M4UnitL,
 394                                     M4UnitNSHF,
 395                                     M4UnitNSHF,
 396                                     M4UnitNSHF,
 397                                     M4UnitNSHF]>  { let Latency = 7;
 398                                                     let NumMicroOps = 5;
 399                                                     let ResourceCycles = [3, 1, 1, 1, 1]; }
 400 def M4WriteVLDL    : SchedWriteRes<[M4UnitL,
 401                                     M4UnitNSHF,
 402                                     M4UnitNSHF,
 403                                     M4UnitL,
 404                                     M4UnitNSHF]>  { let Latency = 7;
 405                                                     let NumMicroOps = 5;
 406                                                     let ResourceCycles = [3, 1, 1, 6, 1]; }
 407 def M4WriteVLDM    : SchedWriteRes<[M4UnitL,
 408                                     M4UnitNSHF,
 409                                     M4UnitNSHF,
 410                                     M4UnitL,
 411                                     M4UnitNSHF,
 412                                     M4UnitNSHF]>  { let Latency = 7;
 413                                                     let NumMicroOps = 6;
 414                                                     let ResourceCycles = [3, 1, 1, 3, 1, 1]; }
 415 def M4WriteVLDN    : SchedWriteRes<[M4UnitL,
 416                                     M4UnitL,
 417                                     M4UnitL,
 418                                     M4UnitL]>     { let Latency = 14;
 419                                                     let NumMicroOps = 4;
 420                                                     let ResourceCycles = [3, 3, 3, 3]; }
 421
 422 def M4WriteVST1    : SchedWriteRes<[M4UnitS,
 423                                     M4UnitFST]>  { let Latency = 1;
 424                                                    let NumMicroOps = 1; }
 425 def M4WriteVSTA    : WriteSequence<[WriteVST], 2>;
 426 def M4WriteVSTB    : WriteSequence<[WriteVST], 3>;
 427 def M4WriteVSTC    : WriteSequence<[WriteVST], 4>;
 428 def M4WriteVSTD    : SchedWriteRes<[M4UnitS,
 429                                     M4UnitFST]>   { let Latency = 2; }
 430 def M4WriteVSTE    : SchedWriteRes<[M4UnitS,
 431                                     M4UnitFST,
 432                                     M4UnitS,
 433                                     M4UnitFST]>   { let Latency = 2;
 434                                                     let NumMicroOps = 2; }
 435 def M4WriteVSTF    : SchedWriteRes<[M4UnitNSHF,
 436                                     M4UnitS,
 437                                     M4UnitFST,
 438                                     M4UnitS,
 439                                     M4UnitFST]>   { let Latency = 4;
 440                                                     let NumMicroOps = 4;
 441                                                     let ResourceCycles = [1, 2, 1, 2, 1]; }
 442 def M4WriteVSTG    : SchedWriteRes<[M4UnitNSHF,
 443                                     M4UnitNSHF,
 444                                     M4UnitNSHF,
 445                                     M4UnitS,
 446                                     M4UnitFST,
 447                                     M4UnitS,
 448                                     M4UnitFST,
 449                                     M4UnitS,
 450                                     M4UnitFST]>   { let Latency = 5;
 451                                                     let NumMicroOps = 6;
 452                                                     let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
 453 def M4WriteVSTI    : SchedWriteRes<[M4UnitNSHF,
 454                                     M4UnitNSHF,
 455                                     M4UnitNSHF,
 456                                     M4UnitNSHF,
 457                                     M4UnitS,
 458                                     M4UnitFST,
 459                                     M4UnitS,
 460                                     M4UnitFST,
 461                                     M4UnitS,
 462                                     M4UnitFST,
 463                                     M4UnitS,
 464                                     M4UnitFST]>   { let Latency = 8;
 465                                                     let NumMicroOps = 5;
 466                                                     let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
 467 def M4WriteVSTJ    : SchedWriteRes<[M4UnitA,
 468                                     M4UnitS,
 469                                     M4UnitFST,
 470                                     M4UnitS,
 471                                     M4UnitFST]>   { let Latency = 1;
 472                                                     let NumMicroOps = 2; }
 473 def M4WriteVSTK    : SchedWriteRes<[M4UnitA,
 474                                     M4UnitS,
 475                                     M4UnitFST]>   { let Latency = 3;
 476                                                     let NumMicroOps = 2; }
 477 def M4WriteVSTL    : SchedWriteRes<[M4UnitNSHF,
 478                                     M4UnitNSHF,
 479                                     M4UnitS,
 480                                     M4UnitFST,
 481                                     M4UnitS,
 482                                     M4UnitFST]>   { let Latency = 4;
 483                                                     let NumMicroOps = 4;
 484                                                     let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
 485 def M4WriteVSTY    : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>,
 486                                         SchedVar<NoSchedPred,         [WriteVST]>]>;
 487
 488 // Special cases.
 489 def M4WriteCOPY    : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>,
 490                                         SchedVar<NoSchedPred,  [M4WriteZ0]>]>;
 491 def M4WriteMOVI    : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>,
 492                                         SchedVar<NoSchedPred,       [M4WriteNALU1]>]>;
 493
 494 // Fast forwarding.
 495 def M4ReadAESM1    : SchedReadAdvance<+1, [M4WriteNCRY1]>;
 496 def M4ReadFMACM1   : SchedReadAdvance<+1, [M4WriteFMAC4,
 497                                            M4WriteFMAC4H,
 498                                            M4WriteFMAC5]>;
 499 def M4ReadNMULM1   : SchedReadAdvance<+1, [M4WriteNMUL3]>;
 500 def M4ReadNMULP2   : SchedReadAdvance<-2, [M4WriteNMUL3]>;
 501
 502
 503 //===----------------------------------------------------------------------===//
 504 // Coarse scheduling model.
 505
 506 // Branch instructions.
 507 def : SchedAlias<WriteBr,    M4WriteZ0>;
 508 def : SchedAlias<WriteBrReg, M4WriteC1>;
 509
 510 // Arithmetic and logical integer instructions.
 511 def : SchedAlias<WriteI,     M4WriteA1>;
 512 def : SchedAlias<WriteIEReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
 513 def : SchedAlias<WriteISReg, M4WriteAA>; // FIXME: M4WriteAX crashes TableGen.
 514 def : SchedAlias<WriteIS,    M4WriteA1>;
 515
 516 // Move instructions.
 517 def : SchedAlias<WriteImm, M4WriteA1>;
 518
 519 // Divide and multiply instructions.
 520 def : SchedAlias<WriteID32, M4WriteD12>;
 521 def : SchedAlias<WriteID64, M4WriteD21>;
 522 def : SchedAlias<WriteIM32, M4WriteC3>;
 523 def : SchedAlias<WriteIM64, M4WriteCA>;
 524
 525 // Miscellaneous instructions.
 526 def : SchedAlias<WriteExtr, M4WriteAY>;
 527
 528 // Addressing modes.
 529 def : SchedAlias<WriteAdr,    M4WriteZ1>;
 530 def : SchedAlias<ReadAdrBase, M4ReadAdrBase>;
 531
 532 // Load instructions.
 533 def : SchedAlias<WriteLD,    M4WriteL4>;
 534 def : SchedAlias<WriteLDHi,  M4WriteZ4>;
 535 def : SchedAlias<WriteLDIdx, M4WriteLX>;
 536
 537 // Store instructions.
 538 def : SchedAlias<WriteST,    M4WriteS1>;
 539 def : SchedAlias<WriteSTP,   M4WriteS1>;
 540 def : SchedAlias<WriteSTX,   M4WriteS1>;
 541 def : SchedAlias<WriteSTIdx, M4WriteSX>;
 542
 543 // FP data instructions.
 544 def : SchedAlias<WriteF,    M4WriteFADD2>;
 545 def : SchedAlias<WriteFCmp, M4WriteNMSC2>;
 546 def : SchedAlias<WriteFDiv, M4WriteFDIV12>;
 547 def : SchedAlias<WriteFMul, M4WriteFMAC3>;
 548
 549 // FP miscellaneous instructions.
 550 def : SchedAlias<WriteFCvt,  M4WriteFCVT2>;
 551 def : SchedAlias<WriteFImm,  M4WriteNALU1>;
 552 def : SchedAlias<WriteFCopy, M4WriteNALU1>;
 553
 554 // FP load instructions.
 555 def : SchedAlias<WriteVLD, M4WriteL5>;
 556
 557 // FP store instructions.
 558 def : SchedAlias<WriteVST, M4WriteVST1>;
 559
 560 // ASIMD FP instructions.
 561 def : SchedAlias<WriteVd, M4WriteNALU1>;
 562 def : SchedAlias<WriteVq, M4WriteNALU1>;
 563
 564 // Other miscellaneous instructions.
 565 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 566 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 567 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 568 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 569
 570 //===----------------------------------------------------------------------===//
 571 // Generic fast forwarding.
 572
 573 // TODO: Add FP register forwarding rules.
 574
 575 def : ReadAdvance<ReadI,       0>;
 576 def : ReadAdvance<ReadISReg,   0>;
 577 def : ReadAdvance<ReadIEReg,   0>;
 578 def : ReadAdvance<ReadIM,      0>;
 579 // TODO: The forwarding for 32 bits actually saves 2 cycles.
 580 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 581 def : ReadAdvance<ReadID,      0>;
 582 def : ReadAdvance<ReadExtrHi,  0>;
 583 def : ReadAdvance<ReadAdrBase, 0>;
 584 def : ReadAdvance<ReadVLD,     0>;
 585 def : ReadAdvance<ReadST,      0>;
 586
 587 //===----------------------------------------------------------------------===//
 588 // Finer scheduling model.
 589
 590 // Branch instructions
 591 def : InstRW<[M4WriteB1], (instrs Bcc)>;
 592 def : InstRW<[M4WriteAF], (instrs BL)>;
 593 def : InstRW<[M4WriteBX], (instrs BLR)>;
 594 def : InstRW<[M4WriteC1], (instregex "^CBN?Z[WX]")>;
 595 def : InstRW<[M4WriteAD], (instregex "^TBN?Z[WX]")>;
 596
 597 // Arithmetic and logical integer instructions.
 598 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
 599 def : InstRW<[M4WriteAU], (instrs ORRWrs, ORRXrs)>;
 600 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
 601 def : InstRW<[M4WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
 602 def : InstRW<[M4WriteAV], (instrs ADDWri, ADDXri, ORRWri, ORRXri)>;
 603
 604 // Move instructions.
 605 def : InstRW<[M4WriteCOPY], (instrs COPY)>;
 606 def : InstRW<[M4WriteZ0],   (instrs ADR, ADRP)>;
 607 def : InstRW<[M4WriteZ0],   (instregex "^MOV[NZ][WX]i")>;
 608
 609 // Divide and multiply instructions.
 610
 611 // Miscellaneous instructions.
 612
 613 // Load instructions.
 614 def : InstRW<[M4WriteLD,
 615               WriteLDHi,
 616               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 617 def : InstRW<[M4WriteL5,
 618               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 619 def : InstRW<[WriteLDIdx,
 620               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 621 def : InstRW<[M4WriteL5,
 622               ReadAdrBase], (instrs PRFMroW)>;
 623 def : InstRW<[WriteLDIdx,
 624               ReadAdrBase], (instrs PRFMroX)>;
 625
 626 // Store instructions.
 627 def : InstRW<[M4WriteSB,
 628               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 629 def : InstRW<[WriteST,
 630               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 631
 632 // FP data instructions.
 633 def : InstRW<[M4WriteNSHF1H], (instrs FABSHr)>;
 634 def : InstRW<[M4WriteNSHF1],  (instregex "^FABS[SD]r")>;
 635 def : InstRW<[M4WriteFADD2H], (instregex "^F(ADD|SUB)Hrr")>;
 636 def : InstRW<[M4WriteFADD2],  (instregex "^F(ADD|SUB)[SD]rr")>;
 637 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.i16")>;
 638 def : InstRW<[M4WriteFADD2],  (instregex "^FADDPv.i(32|64)")>;
 639 def : InstRW<[M4WriteNEONQ],  (instregex "^FCCMPE?[HSD]rr")>;
 640 def : InstRW<[M4WriteNMSC2],  (instregex "^FCMPE?[HSD]r[ir]")>;
 641 def : InstRW<[M4WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)(16|32|64|v1)")>;
 642 def : InstRW<[M4WriteFDIV7H], (instrs FDIVHrr)>;
 643 def : InstRW<[M4WriteFDIV7],  (instrs FDIVSrr)>;
 644 def : InstRW<[M4WriteFDIV12], (instrs FDIVDrr)>;
 645 def : InstRW<[M4WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?[HSD]rr")>;
 646 def : InstRW<[M4WriteFMAC3H], (instregex "^FN?MULHrr")>;
 647 def : InstRW<[M4WriteFMAC3],  (instregex "^FN?MUL[SD]rr")>;
 648 def : InstRW<[M4WriteFMAC3H], (instrs FMULX16)>;
 649 def : InstRW<[M4WriteFMAC3],  (instregex "^FMULX(32|64)")>;
 650 def : InstRW<[M4WriteFMAC4H,
 651               M4ReadFMACM1],  (instregex "^FN?M(ADD|SUB)Hrrr")>;
 652 def : InstRW<[M4WriteFMAC4,
 653               M4ReadFMACM1],  (instregex "^FN?M(ADD|SUB)[SD]rrr")>;
 654 def : InstRW<[M4WriteNALU1H], (instrs FNEGHr)>;
 655 def : InstRW<[M4WriteNALU1],  (instregex "^FNEG[SD]r")>;
 656 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
 657 def : InstRW<[M4WriteNEONH],  (instregex "^FCSEL[HSD]rrr")>;
 658 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTHr)>;
 659 def : InstRW<[M4WriteFSQR8],  (instrs FSQRTSr)>;
 660 def : InstRW<[M4WriteFSQR12], (instrs FSQRTDr)>;
 661
 662 // FP miscellaneous instructions.
 663 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVTH[SD]r")>;
 664 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>;
 665 def : InstRW<[M4WriteFCVT2],  (instregex "^FCVT[SD][SD]r")>;
 666 def : InstRW<[M4WriteFCVT6A], (instregex "^[SU]CVTF[SU][XW][HSD]ri")>;
 667 def : InstRW<[M4WriteNEONR],  (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
 668 def : InstRW<[M4WriteNALU1],  (instregex "^FMOV[HSD][ir]")>;
 669 def : InstRW<[M4WriteSA],     (instregex "^FMOV[WX][HSD]r")>;
 670 def : InstRW<[M4WriteNEONJ],  (instregex "^FMOV[HSD][WX]r")>;
 671 def : InstRW<[M4WriteNEONI],  (instregex "^FMOVXDHighr")>;
 672 def : InstRW<[M4WriteNEONK],  (instregex "^FMOVDXHighr")>;
 673 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>;
 674 def : InstRW<[M4WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>;
 675 def : InstRW<[M4WriteNMSC1],  (instregex "^FRECPXv1")>;
 676 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>;
 677 def : InstRW<[M4WriteFMAC4],  (instregex "^F(RECP|RSQRT)S(32|64)")>;
 678
 679 // FP load instructions.
 680 def : InstRW<[WriteVLD],    (instregex "^LDR[SDQ]l")>;
 681 def : InstRW<[WriteVLD],    (instregex "^LDUR[BHSDQ]i")>;
 682 def : InstRW<[WriteVLD,
 683               WriteAdr],    (instregex "^LDR[BHSDQ](post|pre)")>;
 684 def : InstRW<[WriteVLD],    (instregex "^LDR[BHSDQ]ui")>;
 685 def : InstRW<[M4WriteLE,
 686               ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
 687 def : InstRW<[WriteVLD,
 688               ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
 689 def : InstRW<[M4WriteLY,
 690               ReadAdrBase], (instrs LDRQroX)>;
 691 def : InstRW<[WriteVLD,
 692               M4WriteLH],   (instregex "^LDN?P[SD]i")>;
 693 def : InstRW<[M4WriteLA,
 694               M4WriteLH],   (instregex "^LDN?PQi")>;
 695 def : InstRW<[M4WriteL5,
 696               M4WriteLH,
 697               WriteAdr],    (instregex "^LDP[SD]post")>;
 698 def : InstRW<[M4WriteLB,
 699               M4WriteLH,
 700               WriteAdr],    (instrs LDPQpost)>;
 701 def : InstRW<[M4WriteLB,
 702               M4WriteLH,
 703               WriteAdr],    (instregex "^LDP[SD]pre")>;
 704 def : InstRW<[M4WriteLC,
 705               M4WriteLH,
 706               WriteAdr],    (instrs LDPQpre)>;
 707
 708 // FP store instructions.
 709 def : InstRW<[WriteVST],    (instregex "^STUR[BHSDQ]i")>;
 710 def : InstRW<[WriteVST,
 711               WriteAdr],    (instregex "^STR[BHSDQ](post|pre)")>;
 712 def : InstRW<[WriteVST],    (instregex "^STR[BHSDQ]ui")>;
 713 def : InstRW<[M4WriteVSTK,
 714               ReadAdrBase], (instregex "^STR[BHSD]roW")>;
 715 def : InstRW<[M4WriteVSTK,
 716               ReadAdrBase], (instrs STRQroW)>;
 717 def : InstRW<[WriteVST,
 718               ReadAdrBase], (instregex "^STR[BHSD]roX")>;
 719 def : InstRW<[M4WriteVSTY,
 720               ReadAdrBase], (instrs STRQroX)>;
 721 def : InstRW<[WriteVST],    (instregex "^STN?P[SD]i")>;
 722 def : InstRW<[M4WriteVSTJ], (instregex "^STN?PQi")>;
 723 def : InstRW<[WriteVST,
 724               WriteAdr],    (instregex "^STP[SD](post|pre)")>;
 725 def : InstRW<[M4WriteVSTJ,
 726               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 727
 728 // ASIMD instructions.
 729 def : InstRW<[M4WriteNHAD1],  (instregex "^[SU]ABDL?v")>;
 730 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]ABAL?v")>;
 731 def : InstRW<[M4WriteNMSC1],  (instregex "^ABSv")>;
 732 def : InstRW<[M4WriteNALU1],  (instregex "^(ADD|NEG|SUB)v")>;
 733 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]?ADDL?Pv")>;
 734 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]H(ADD|SUB)v")>;
 735 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU](ADD|SUB)[LW]v")>;
 736 def : InstRW<[M4WriteNHAD3],  (instregex "^R?(ADD|SUB)HN2?v")>;
 737 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]Q(ADD|SUB)v")>;
 738 def : InstRW<[M4WriteNHAD3],  (instregex "^(SU|US)QADDv")>;
 739 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]RHADDv")>;
 740 def : InstRW<[M4WriteNMSC1],  (instregex "^SQ(ABS|NEG)v")>;
 741 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]?ADDL?Vv")>;
 742 def : InstRW<[M4WriteNMSC1],  (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 743 def : InstRW<[M4WriteNALU1],  (instregex "^CMTSTv")>;
 744 def : InstRW<[M4WriteNALU1],  (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
 745 def : InstRW<[M4WriteNMSC1],  (instregex "^[SU](MIN|MAX)v")>;
 746 def : InstRW<[M4WriteNMSC2],  (instregex "^[SU](MIN|MAX)Pv")>;
 747 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU](MIN|MAX)Vv")>;
 748 def : InstRW<[M4WriteNMUL3,
 749               M4ReadNMULM1],  (instregex "^ML[AS]v")>;
 750 def : InstRW<[M4WriteNMUL3,
 751               M4ReadNMULM1],  (instregex "^(SQR?D)?MULH?v")>;
 752 def : InstRW<[M4WriteNMUL3,
 753               M4ReadNMULM1],  (instregex "^SQRDML[AS]H")>;
 754 def : InstRW<[M4WriteNMUL3,
 755               M4ReadNMULM1],  (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
 756 def : InstRW<[M4WriteNMUL3,
 757               M4ReadNMULP2],  (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>;
 758 def : InstRW<[M4WriteNMUL3,
 759               M4ReadNMULM1],  (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
 760 def : InstRW<[M4WriteNMUL3,
 761               M4ReadNMULP2],  (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>;
 762 def : InstRW<[M4WriteNMUL3],  (instregex "^[SU]DOT(lane)?v")>;
 763 def : InstRW<[M4WriteNHAD3],  (instregex "^[SU]ADALPv")>;
 764 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
 765 def : InstRW<[M4WriteNSHT1],  (instregex "^SHL[dv]")>;
 766 def : InstRW<[M4WriteNSHT1],  (instregex "^S[LR]I[dv]")>;
 767 def : InstRW<[M4WriteNSHT1],  (instregex "^[SU]SH[LR][dv]")>;
 768 def : InstRW<[M4WriteNSHT2],  (instregex "^[SU]?SHLLv")>;
 769 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?Q?R?SHRU?N[bhsv]")>;
 770 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]RSH[LR][dv]")>;
 771 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]QR?SHLU?[bhsdv]")>;
 772
 773 // ASIMD FP instructions.
 774 def : InstRW<[M4WriteNSHF1H], (instregex "^FABSv.f16")>;
 775 def : InstRW<[M4WriteNSHF1],  (instregex "^FABSv.f(32|64)")>;
 776 def : InstRW<[M4WriteFADD2H], (instregex "^F(ABD|ADD|SUB)v.f16")>;
 777 def : InstRW<[M4WriteFADD2],  (instregex "^F(ABD|ADD|SUB)v.f(32|64)")>;
 778 def : InstRW<[M4WriteFADD2H], (instregex "^FADDPv.f16")>;
 779 def : InstRW<[M4WriteFADD2],  (instregex "^FADDPv.f(32|64)")>;
 780 def : InstRW<[M4WriteNMSC1],  (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 781 def : InstRW<[M4WriteFCVT2],  (instregex "^FCVT(L|N|XN)v")>;
 782 def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
 783 def : InstRW<[M4WriteFCVT2H], (instregex "^[SU]CVTFv.[fi]16")>;
 784 def : InstRW<[M4WriteFCVT2],  (instregex "^[SU]CVTFv.[fi](32|64)")>;
 785 def : InstRW<[M4WriteFDIV7H], (instrs FDIVv4f16)>;
 786 def : InstRW<[M4WriteNEONVH], (instrs FDIVv8f16)>;
 787 def : InstRW<[M4WriteFDIV7],  (instrs FDIVv2f32)>;
 788 def : InstRW<[M4WriteNEONV],  (instrs FDIVv4f32)>;
 789 def : InstRW<[M4WriteNEONW],  (instrs FDIVv2f64)>;
 790 def : InstRW<[M4WriteNMSC1],  (instregex "^F(MAX|MIN)(NM)?v")>;
 791 def : InstRW<[M4WriteNMSC2],  (instregex "^F(MAX|MIN)(NM)?Pv")>;
 792 def : InstRW<[M4WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;
 793 def : InstRW<[M4WriteFMAC2H], (instregex "^FMULX?v.[fi]16")>;
 794 def : InstRW<[M4WriteFMAC3],  (instregex "^FMULX?v.[fi](32|64)")>;
 795 def : InstRW<[M4WriteFMAC4H,
 796               M4ReadFMACM1],  (instregex "^FML[AS]v.[fi]16")>;
 797 def : InstRW<[M4WriteFMAC4,
 798               M4ReadFMACM1],  (instregex "^FML[AS]v.[fi](32|64)")>;
 799 def : InstRW<[M4WriteNALU1H], (instregex "^FNEGv.f16")>;
 800 def : InstRW<[M4WriteNALU1],  (instregex "^FNEGv.f(32|64)")>;
 801 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
 802 def : InstRW<[M4WriteFSQR7H], (instrs FSQRTv4f16)>;
 803 def : InstRW<[M4WriteNEONXH], (instrs FSQRTv8f16)>;
 804 def : InstRW<[M4WriteFSQR8],  (instrs FSQRTv2f32)>;
 805 def : InstRW<[M4WriteNEONX],  (instrs FSQRTv4f32)>;
 806 def : InstRW<[M4WriteNEONY],  (instrs FSQRTv2f64)>;
 807
 808 // ASIMD miscellaneous instructions.
 809 def : InstRW<[M4WriteNALU1],  (instregex "^RBITv")>;
 810 def : InstRW<[M4WriteNALU1],  (instregex "^(BIF|BIT|BSL|BSP)v")>;
 811 def : InstRW<[M4WriteNALU1],  (instregex "^CL[STZ]v")>;
 812 def : InstRW<[M4WriteNEONB],  (instregex "^DUPv.+gpr")>;
 813 def : InstRW<[M4WriteNSHF1],  (instregex "^DUP(i8|i16|i32|i64)$")>;
 814 def : InstRW<[M4WriteNSHF1],  (instregex "^DUPv.+lane")>;
 815 def : InstRW<[M4WriteNSHF1],  (instregex "^EXTv")>;
 816 def : InstRW<[M4WriteNSHT4A], (instregex "^XTNv")>;
 817 def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]?QXTU?Nv")>;
 818 def : InstRW<[M4WriteNEONB],  (instregex "^INSv.+gpr")>;
 819 def : InstRW<[M4WriteNSHF1],  (instregex "^INSv.+lane")>;
 820 def : InstRW<[M4WriteMOVI],   (instregex "^(MOV|MVN)I")>;
 821 def : InstRW<[M4WriteNALU1H], (instregex "^FMOVv.f16")>;
 822 def : InstRW<[M4WriteNALU1],  (instregex "^FMOVv.f(32|64)")>;
 823 def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>;
 824 def : InstRW<[M4WriteFCVT3],  (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>;
 825 def : InstRW<[M4WriteFCVT3],  (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
 826 def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>;
 827 def : InstRW<[M4WriteFMAC4],  (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
 828 def : InstRW<[M4WriteNSHF1],  (instregex "^REV(16|32|64)v")>;
 829 def : InstRW<[M4WriteNSHFA],  (instregex "^TB[LX]v(8|16)i8One")>;
 830 def : InstRW<[M4WriteNSHFB],  (instregex "^TB[LX]v(8|16)i8Two")>;
 831 def : InstRW<[M4WriteNSHFC],  (instregex "^TB[LX]v(8|16)i8Three")>;
 832 def : InstRW<[M4WriteNSHFD],  (instregex "^TB[LX]v(8|16)i8Four")>;
 833 def : InstRW<[M4WriteNEONP],  (instregex "^[SU]MOVv")>;
 834 def : InstRW<[M4WriteNSHF1],  (instregex "^(TRN|UZP|ZIP)[12]v")>;
 835
 836 // ASIMD load instructions.
 837 def : InstRW<[WriteVLD],    (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 838 def : InstRW<[WriteVLD,
 839               M4WriteA1],   (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 840 def : InstRW<[WriteVLD],    (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 841 def : InstRW<[WriteVLD,
 842               M4WriteA1],   (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 843
 844 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 845 def : InstRW<[M4WriteVLDA,
 846               M4WriteA1],   (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 847 def : InstRW<[M4WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 848 def : InstRW<[M4WriteVLDA,
 849               M4WriteA1],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 850
 851 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 852 def : InstRW<[M4WriteVLDB,
 853               M4WriteA1],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 854 def : InstRW<[M4WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 855 def : InstRW<[M4WriteVLDB,
 856               M4WriteA1],   (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 857
 858 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 859 def : InstRW<[M4WriteVLDC,
 860               M4WriteA1],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 861 def : InstRW<[M4WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 862 def : InstRW<[M4WriteVLDC,
 863               M4WriteA1],   (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 864
 865 def : InstRW<[M4WriteVLDD], (instregex "LD1i(8|16|32|64)$")>;
 866 def : InstRW<[M4WriteVLDD,
 867               M4WriteA1],   (instregex "LD1i(8|16|32|64)_POST$")>;
 868
 869 def : InstRW<[WriteVLD],    (instregex "LD1Rv(8b|4h|2s|1d)$")>;
 870 def : InstRW<[WriteVLD,
 871               M4WriteA1],   (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
 872 def : InstRW<[WriteVLD],    (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 873 def : InstRW<[WriteVLD,
 874               M4WriteA1],   (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 875
 876 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
 877 def : InstRW<[M4WriteVLDF,
 878               M4WriteA1],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 879 def : InstRW<[M4WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
 880 def : InstRW<[M4WriteVLDF,
 881               M4WriteA1],   (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
 882
 883 def : InstRW<[M4WriteVLDG], (instregex "LD2i(8|16|32|64)$")>;
 884 def : InstRW<[M4WriteVLDG,
 885               M4WriteA1],   (instregex "LD2i(8|16|32|64)_POST$")>;
 886
 887 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
 888 def : InstRW<[M4WriteVLDA,
 889               M4WriteA1],   (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
 890 def : InstRW<[M4WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 891 def : InstRW<[M4WriteVLDA,
 892               M4WriteA1],   (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 893
 894 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
 895 def : InstRW<[M4WriteVLDI,
 896               M4WriteA1],   (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 897 def : InstRW<[M4WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
 898 def : InstRW<[M4WriteVLDI,
 899               M4WriteA1],   (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
 900
 901 def : InstRW<[M4WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
 902 def : InstRW<[M4WriteVLDJ,
 903               M4WriteA1],   (instregex "LD3i(8|16|32)_POST$")>;
 904 def : InstRW<[M4WriteVLDL], (instregex "LD3i64$")>;
 905 def : InstRW<[M4WriteVLDL,
 906               M4WriteA1],   (instregex "LD3i64_POST$")>;
 907
 908 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
 909 def : InstRW<[M4WriteVLDB,
 910               M4WriteA1],   (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
 911 def : InstRW<[M4WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
 912 def : InstRW<[M4WriteVLDB,
 913               M4WriteA1],   (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
 914
 915 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
 916 def : InstRW<[M4WriteVLDN,
 917               M4WriteA1],   (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 918 def : InstRW<[M4WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
 919 def : InstRW<[M4WriteVLDN,
 920               M4WriteA1],   (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
 921
 922 def : InstRW<[M4WriteVLDK], (instregex "LD4i(8|16|32)$")>;
 923 def : InstRW<[M4WriteVLDK,
 924               M4WriteA1],   (instregex "LD4i(8|16|32)_POST$")>;
 925 def : InstRW<[M4WriteVLDM], (instregex "LD4i64$")>;
 926 def : InstRW<[M4WriteVLDM,
 927               M4WriteA1],   (instregex "LD4i64_POST$")>;
 928
 929 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
 930 def : InstRW<[M4WriteVLDC,
 931               M4WriteA1],   (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
 932 def : InstRW<[M4WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
 933 def : InstRW<[M4WriteVLDC,
 934               M4WriteA1],   (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
 935
 936 // ASIMD store instructions.
 937 def : InstRW<[WriteVST],    (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 938 def : InstRW<[WriteVST,
 939               M4WriteA1],   (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 940 def : InstRW<[WriteVST],    (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 941 def : InstRW<[WriteVST,
 942               M4WriteA1],   (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 943
 944 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 945 def : InstRW<[M4WriteVSTA,
 946               M4WriteA1],   (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 947 def : InstRW<[M4WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 948 def : InstRW<[M4WriteVSTA,
 949               M4WriteA1],   (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 950
 951 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 952 def : InstRW<[M4WriteVSTB,
 953               M4WriteA1],   (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 954 def : InstRW<[M4WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 955 def : InstRW<[M4WriteVSTB,
 956               M4WriteA1],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 957
 958 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 959 def : InstRW<[M4WriteVSTC,
 960               M4WriteA1],   (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 961 def : InstRW<[M4WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 962 def : InstRW<[M4WriteVSTC,
 963               M4WriteA1],   (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 964
 965 def : InstRW<[WriteVST],    (instregex "ST1i(8|16|32|64)$")>;
 966 def : InstRW<[WriteVST,
 967               M4WriteA1],   (instregex "ST1i(8|16|32|64)_POST$")>;
 968
 969 def : InstRW<[M4WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
 970 def : InstRW<[M4WriteVSTD,
 971               M4WriteA1],   (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 972 def : InstRW<[M4WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
 973 def : InstRW<[M4WriteVSTE,
 974               M4WriteA1],   (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
 975
 976 def : InstRW<[M4WriteVSTD], (instregex "ST2i(8|16|32|64)$")>;
 977 def : InstRW<[M4WriteVSTD,
 978               M4WriteA1],   (instregex "ST2i(8|16|32|64)_POST$")>;
 979
 980 def : InstRW<[M4WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
 981 def : InstRW<[M4WriteVSTF,
 982               M4WriteA1],   (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 983 def : InstRW<[M4WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
 984 def : InstRW<[M4WriteVSTG,
 985               M4WriteA1],   (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
 986
 987 def : InstRW<[M4WriteVSTE], (instregex "ST3i(8|16|32|64)$")>;
 988 def : InstRW<[M4WriteVSTE,
 989               M4WriteA1],   (instregex "ST3i(8|16|32|64)_POST$")>;
 990
 991 def : InstRW<[M4WriteVSTL], (instregex "ST4Fourv(8b|4h|2s)$")>;
 992 def : InstRW<[M4WriteVSTL,
 993               M4WriteA1],   (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 994 def : InstRW<[M4WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
 995 def : InstRW<[M4WriteVSTI,
 996               M4WriteA1],   (instregex "ST4Fourv(16b|8h|4s|2d)_POST$")>;
 997
 998 def : InstRW<[M4WriteVSTE], (instregex "ST4i(8|16|32|64)$")>;
 999 def : InstRW<[M4WriteVSTE,
1000               M4WriteA1],   (instregex "ST4i(8|16|32|64)_POST$")>;
1001
1002 // Cryptography instructions.
1003 def : InstRW<[M4WriteNCRY1],  (instregex "^AES[DE]")>;
1004 def : InstRW<[M4WriteNCRY1,
1005               M4ReadAESM1],   (instregex "^AESI?MC")>;
1006 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULv")>;
1007 def : InstRW<[M4WriteNCRY1A], (instregex "^PMULLv(1|8)i")>;
1008 def : InstRW<[M4WriteNCRY3A], (instregex "^PMULLv(2|16)i")>;
1009 def : InstRW<[M4WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
1010 def : InstRW<[M4WriteNCRY1A], (instrs SHA256SU0rr)>;
1011 def : InstRW<[M4WriteNCRY5A], (instrs SHA256SU1rrr)>;
1012 def : InstRW<[M4WriteNCRY5A], (instrs SHA256H2rrr)>;
1013
1014 // CRC instructions.
1015 def : InstRW<[M4WriteE2], (instregex "^CRC32C?[BHWX]rr$")>;
1016
1017 } // SchedModel = ExynosM4Model