[RISCV] Relax march string order constraint (#78120)
[llvm-project.git] / flang / module / __cuda_builtins.f90
blob50e0d2682ef301537387b86d7d145c3fd67138a2
1 !===-- module/__cuda_builtins.f90 ------------------------------------------===!
3 ! Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 ! See https://llvm.org/LICENSE.txt for license information.
5 ! SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 !===------------------------------------------------------------------------===!
9 ! These CUDA predefined variables are automatically available in device
10 ! subprograms.
12 module __CUDA_builtins
13 use __fortran_builtins, only: &
14 threadIdx => __builtin_threadIdx, &
15 blockDim => __builtin_blockDim, &
16 blockIdx => __builtin_blockIdx, &
17 gridDim => __builtin_gridDim, &
18 warpsize => __builtin_warpsize
19 end module