llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fminmax.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
   3
   4 ---
   5 name:            fmin_v2s32
   6 tracksRegLiveness: true
   7 body:             |
   8   bb.1:
   9     liveins: $d0
  10
  11     ; CHECK-LABEL: name: fmin_v2s32
  12     ; CHECK: liveins: $d0
  13     ; CHECK-NEXT: {{  $}}
  14     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
  15     ; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[COPY]](<2 x s32>)
  16     ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)
  17     ; CHECK-NEXT: RET_ReallyLR implicit $s0
  18     %0:_(<2 x s32>) = COPY $d0
  19     %1:_(s32) = G_VECREDUCE_FMIN %0(<2 x s32>)
  20     $s0 = COPY %1(s32)
  21     RET_ReallyLR implicit $s0
  22
  23 ...
  24 ---
  25 name:            fmax_v8s16
  26 tracksRegLiveness: true
  27 body:             |
  28   bb.1:
  29     liveins: $q0
  30
  31     ; CHECK-LABEL: name: fmax_v8s16
  32     ; CHECK: liveins: $q0
  33     ; CHECK-NEXT: {{  $}}
  34     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
  35     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
  36     ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
  37     ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
  38     ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(<4 x s32>) = G_FMAXNUM [[FPEXT]], [[FPEXT1]]
  39     ; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[FMAXNUM]](<4 x s32>)
  40     ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[VECREDUCE_FMAX]](s32)
  41     ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
  42     ; CHECK-NEXT: RET_ReallyLR implicit $h0
  43     %0:_(<8 x s16>) = COPY $q0
  44     %1:_(s16) = G_VECREDUCE_FMAX %0(<8 x s16>)
  45     $h0 = COPY %1(s16)
  46     RET_ReallyLR implicit $h0
  47
  48 ...
  49 ---
  50 name:            fminimum_v2s32
  51 tracksRegLiveness: true
  52 body:             |
  53   bb.1:
  54     liveins: $d0
  55
  56     ; CHECK-LABEL: name: fminimum_v2s32
  57     ; CHECK: liveins: $d0
  58     ; CHECK-NEXT: {{  $}}
  59     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
  60     ; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMINIMUM [[COPY]](<2 x s32>)
  61     ; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)
  62     ; CHECK-NEXT: RET_ReallyLR implicit $s0
  63     %0:_(<2 x s32>) = COPY $d0
  64     %1:_(s32) = G_VECREDUCE_FMINIMUM %0(<2 x s32>)
  65     $s0 = COPY %1(s32)
  66     RET_ReallyLR implicit $s0
  67
  68 ...
  69 ---
  70 name:            fmaximum_v8s16
  71 tracksRegLiveness: true
  72 body:             |
  73   bb.1:
  74     liveins: $q0
  75
  76     ; CHECK-LABEL: name: fmaximum_v8s16
  77     ; CHECK: liveins: $q0
  78     ; CHECK-NEXT: {{  $}}
  79     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
  80     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
  81     ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
  82     ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
  83     ; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMAXIMUM [[FPEXT]], [[FPEXT1]]
  84     ; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAXIMUM [[FMAXIMUM]](<4 x s32>)
  85     ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[VECREDUCE_FMAXIMUM]](s32)
  86     ; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
  87     ; CHECK-NEXT: RET_ReallyLR implicit $h0
  88     %0:_(<8 x s16>) = COPY $q0
  89     %1:_(s16) = G_VECREDUCE_FMAXIMUM %0(<8 x s16>)
  90     $h0 = COPY %1(s16)
  91     RET_ReallyLR implicit $h0
  92
  93 ...