1 # RUN: llc -verify-machineinstrs -mtriple aarch64--- \
2 # RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \
8 tracksRegLiveness: true
15 ; CHECK-LABEL: name: test_v4f16.sin
16 ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>)
18 ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16)
19 ; CHECK-NEXT: ADJCALLSTACKDOWN
20 ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
21 ; CHECK-NEXT: BL &sinf
22 ; CHECK-NEXT: ADJCALLSTACKUP
23 ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
24 ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
26 ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
27 ; CHECK-NEXT: ADJCALLSTACKDOWN
28 ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
29 ; CHECK-NEXT: BL &sinf
30 ; CHECK-NEXT: ADJCALLSTACKUP
31 ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
32 ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
34 ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
35 ; CHECK-NEXT: ADJCALLSTACKDOWN
36 ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
37 ; CHECK-NEXT: BL &sinf
38 ; CHECK-NEXT: ADJCALLSTACKUP
39 ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
40 ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
42 ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
43 ; CHECK-NEXT: ADJCALLSTACKDOWN
44 ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
45 ; CHECK-NEXT: BL &sinf
46 ; CHECK-NEXT: ADJCALLSTACKUP
47 ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
48 ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
50 ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
52 %0:_(<4 x s16>) = COPY $d0
53 %1:_(<4 x s16>) = G_FSIN %0
54 $d0 = COPY %1(<4 x s16>)
55 RET_ReallyLR implicit $d0
61 tracksRegLiveness: true
69 ; CHECK-LABEL: name: test_v8f16.sin
71 ; This is big, so let's just check for the 8 calls to sinf, the the
72 ; G_UNMERGE_VALUES, and the G_BUILD_VECTOR. The other instructions ought
73 ; to be covered by the other tests.
75 ; CHECK: G_UNMERGE_VALUES
84 ; CHECK-DAG: G_BUILD_VECTOR
86 %0:_(<8 x s16>) = COPY $q0
87 %1:_(<8 x s16>) = G_FSIN %0
88 $q0 = COPY %1(<8 x s16>)
89 RET_ReallyLR implicit $q0
95 tracksRegLiveness: true
103 ; CHECK-LABEL: name: test_v2f32.sin
104 ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>)
106 ; CHECK-NEXT: ADJCALLSTACKDOWN
107 ; CHECK-DAG: $s0 = COPY [[V1]](s32)
108 ; CHECK-DAG: BL &sinf
109 ; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
110 ; CHECK-DAG: ADJCALLSTACKUP
112 ; CHECK-DAG: ADJCALLSTACKDOWN
113 ; CHECK-DAG: $s0 = COPY [[V2]](s32)
114 ; CHECK-DAG: BL &sinf
115 ; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
116 ; CHECK-DAG: ADJCALLSTACKUP
118 ; CHECK-DAG: %1:_(<2 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32)
120 %0:_(<2 x s32>) = COPY $d0
121 %1:_(<2 x s32>) = G_FSIN %0
122 $d0 = COPY %1(<2 x s32>)
123 RET_ReallyLR implicit $d0
129 tracksRegLiveness: true
131 - { id: 0, class: _ }
132 - { id: 1, class: _ }
136 ; CHECK-LABEL: name: test_v4f32.sin
137 ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32), [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>)
139 ; CHECK-NEXT: ADJCALLSTACKDOWN
140 ; CHECK-DAG: $s0 = COPY [[V1]](s32)
141 ; CHECK-DAG: BL &sinf
142 ; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0
143 ; CHECK-DAG: ADJCALLSTACKUP
145 ; CHECK-DAG: ADJCALLSTACKDOWN
146 ; CHECK-DAG: $s0 = COPY [[V2]](s32)
147 ; CHECK-DAG: BL &sinf
148 ; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0
149 ; CHECK-DAG: ADJCALLSTACKUP
151 ; CHECK-DAG: ADJCALLSTACKDOWN
152 ; CHECK-DAG: $s0 = COPY [[V3]](s32)
153 ; CHECK-DAG: BL &sinf
154 ; CHECK-DAG: [[ELT3:%[0-9]+]]:_(s32) = COPY $s0
155 ; CHECK-DAG: ADJCALLSTACKUP
157 ; CHECK-DAG: ADJCALLSTACKDOWN
158 ; CHECK-DAG: $s0 = COPY [[V4]](s32)
159 ; CHECK-DAG: BL &sinf
160 ; CHECK-DAG: [[ELT4:%[0-9]+]]:_(s32) = COPY $s0
161 ; CHECK-DAG: ADJCALLSTACKUP
163 ; CHECK-DAG: %1:_(<4 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32), [[ELT3]](s32), [[ELT4]](s32)
165 %0:_(<4 x s32>) = COPY $q0
166 %1:_(<4 x s32>) = G_FSIN %0
167 $q0 = COPY %1(<4 x s32>)
168 RET_ReallyLR implicit $q0
174 tracksRegLiveness: true
176 - { id: 0, class: _ }
177 - { id: 1, class: _ }
182 ; CHECK-LABEL: name: test_v2f64.sin
183 ; CHECK: [[V1:%[0-9]+]]:_(s64), [[V2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>)
185 ; CHECK-NEXT: ADJCALLSTACKDOWN
186 ; CHECK-DAG: $d0 = COPY [[V1]](s64)
188 ; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s64) = COPY $d0
189 ; CHECK-DAG: ADJCALLSTACKUP
191 ; CHECK-DAG: ADJCALLSTACKDOWN
192 ; CHECK-DAG: $d0 = COPY [[V2]](s64)
194 ; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s64) = COPY $d0
195 ; CHECK-DAG: ADJCALLSTACKUP
197 ; CHECK-DAG: %1:_(<2 x s64>) = G_BUILD_VECTOR [[ELT1]](s64), [[ELT2]](s64)
199 %0:_(<2 x s64>) = COPY $q0
200 %1:_(<2 x s64>) = G_FSIN %0
201 $q0 = COPY %1(<2 x s64>)
202 RET_ReallyLR implicit $q0
208 tracksRegLiveness: true
210 - { id: 0, class: _ }
211 - { id: 1, class: _ }
215 ; CHECK-LABEL: name: test_sin_half
216 ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16)
217 ; CHECK-NEXT: ADJCALLSTACKDOWN
218 ; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
219 ; CHECK-NEXT: BL &sinf
220 ; CHECK-NEXT: ADJCALLSTACKUP
221 ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
222 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
225 %1:_(s16) = G_FSIN %0
227 RET_ReallyLR implicit $h0