1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s
3 # RUN: llc -mtriple=aarch64 -global-isel -start-before=aarch64-postlegalizer-lowering -stop-after=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=SELECTED
9 tracksRegLiveness: true
14 ; CHECK-LABEL: name: duplane64
16 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
17 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
18 ; CHECK: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](s64)
19 ; CHECK: $q0 = COPY [[DUPLANE64_]](<2 x s64>)
20 ; CHECK: RET_ReallyLR implicit $q0
21 ; SELECTED-LABEL: name: duplane64
22 ; SELECTED: liveins: $q0
23 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
24 ; SELECTED: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY]], 0
25 ; SELECTED: $q0 = COPY [[DUPv2i64lane]]
26 ; SELECTED: RET_ReallyLR implicit $q0
27 %1:_(<2 x s64>) = COPY $q0
28 %2:_(<2 x s64>) = G_IMPLICIT_DEF
29 %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0)
30 $q0 = COPY %4(<2 x s64>)
31 RET_ReallyLR implicit $q0
38 tracksRegLiveness: true
43 ; CHECK-LABEL: name: duplane32
45 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
46 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
47 ; CHECK: [[DUPLANE32_:%[0-9]+]]:_(<4 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64)
48 ; CHECK: $q0 = COPY [[DUPLANE32_]](<4 x s32>)
49 ; CHECK: RET_ReallyLR implicit $q0
50 ; SELECTED-LABEL: name: duplane32
51 ; SELECTED: liveins: $q0
52 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
53 ; SELECTED: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY]], 0
54 ; SELECTED: $q0 = COPY [[DUPv4i32lane]]
55 ; SELECTED: RET_ReallyLR implicit $q0
56 %1:_(<4 x s32>) = COPY $q0
57 %2:_(<4 x s32>) = G_IMPLICIT_DEF
58 %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0)
59 $q0 = COPY %4(<4 x s32>)
60 RET_ReallyLR implicit $q0
67 tracksRegLiveness: true
72 ; CHECK-LABEL: name: duplane16
74 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
75 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
76 ; CHECK: [[DUPLANE16_:%[0-9]+]]:_(<8 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64)
77 ; CHECK: $q0 = COPY [[DUPLANE16_]](<8 x s16>)
78 ; CHECK: RET_ReallyLR implicit $q0
79 ; SELECTED-LABEL: name: duplane16
80 ; SELECTED: liveins: $q0
81 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
82 ; SELECTED: [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY]], 0
83 ; SELECTED: $q0 = COPY [[DUPv8i16lane]]
84 ; SELECTED: RET_ReallyLR implicit $q0
85 %1:_(<8 x s16>) = COPY $q0
86 %2:_(<8 x s16>) = G_IMPLICIT_DEF
87 %4:_(<8 x s16>) = G_SHUFFLE_VECTOR %1(<8 x s16>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0)
88 $q0 = COPY %4(<8 x s16>)
89 RET_ReallyLR implicit $q0
96 tracksRegLiveness: true
101 ; CHECK-LABEL: name: duplane8
102 ; CHECK: liveins: $q0
103 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
104 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
105 ; CHECK: [[DUPLANE8_:%[0-9]+]]:_(<16 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64)
106 ; CHECK: $q0 = COPY [[DUPLANE8_]](<16 x s8>)
107 ; CHECK: RET_ReallyLR implicit $q0
108 ; SELECTED-LABEL: name: duplane8
109 ; SELECTED: liveins: $q0
110 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
111 ; SELECTED: [[DUPv16i8lane:%[0-9]+]]:fpr128 = DUPv16i8lane [[COPY]], 0
112 ; SELECTED: $q0 = COPY [[DUPv16i8lane]]
113 ; SELECTED: RET_ReallyLR implicit $q0
114 %1:_(<16 x s8>) = COPY $q0
115 %2:_(<16 x s8>) = G_IMPLICIT_DEF
116 %4:_(<16 x s8>) = G_SHUFFLE_VECTOR %1(<16 x s8>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
117 $q0 = COPY %4(<16 x s8>)
118 RET_ReallyLR implicit $q0
122 name: v2s32_duplane32
125 tracksRegLiveness: true
131 machineFunctionInfo: {}
136 ; CHECK-LABEL: name: v2s32_duplane32
137 ; CHECK: liveins: $d0, $d1
138 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d1
139 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
140 ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
141 ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s32>) = G_CONCAT_VECTORS [[COPY]](<2 x s32>), [[DEF]](<2 x s32>)
142 ; CHECK: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[CONCAT_VECTORS]], [[C]](s64)
143 ; CHECK: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
144 ; CHECK: RET_ReallyLR implicit $d0
145 ; SELECTED-LABEL: name: v2s32_duplane32
146 ; SELECTED: liveins: $d0, $d1
147 ; SELECTED: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
148 ; SELECTED: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
149 ; SELECTED: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
150 ; SELECTED: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
151 ; SELECTED: $d0 = COPY [[DUPv2i32lane]]
152 ; SELECTED: RET_ReallyLR implicit $d0
153 %0:_(<2 x s32>) = COPY $d0
154 %1:_(<2 x s32>) = COPY $d1
155 %2:_(<2 x s32>) = G_IMPLICIT_DEF
156 %3:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0)
157 $d0 = COPY %3(<2 x s32>)
158 RET_ReallyLR implicit $d0