1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
7 tracksRegLiveness: true
14 ; Ensure that the dest regs have FPR since we're unmerging from a vector
15 ; CHECK-LABEL: name: unmerge
17 ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
18 ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
19 ; CHECK: $x0 = COPY [[UV]](s64)
20 ; CHECK: RET_ReallyLR implicit $x0
21 %0:_(<2 x s64>) = COPY $q0
22 %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
24 RET_ReallyLR implicit $x0
31 tracksRegLiveness: true
38 ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
39 ; CHECK-LABEL: name: unmerge_s128
41 ; CHECK: [[COPY:%[0-9]+]]:fpr(s128) = COPY $q0
42 ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](s128)
43 ; CHECK: $x0 = COPY [[UV]](s64)
44 ; CHECK: RET_ReallyLR implicit $x0
46 %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128)
48 RET_ReallyLR implicit $x0