llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir

   1 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
   2
   3 --- |
   4   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   5
   6   define void @unconditional_br() { ret void }
   7   define void @conditional_br() { ret void }
   8   define void @indirect_br() { ret void }
   9 ...
  10
  11 ---
  12 # CHECK-LABEL: name: unconditional_br
  13 name:            unconditional_br
  14 legalized:       true
  15 regBankSelected: true
  16
  17 # CHECK:  body:
  18 # CHECK:   bb.0:
  19 # CHECK:    successors: %bb.0
  20 # CHECK:    B %bb.0
  21 body:             |
  22   bb.0:
  23     successors: %bb.0
  24
  25     G_BR %bb.0
  26 ...
  27
  28 ---
  29 # CHECK-LABEL: name: conditional_br
  30 name:            conditional_br
  31 legalized:       true
  32 regBankSelected: true
  33
  34 registers:
  35   - { id: 0, class: gpr }
  36   - { id: 1, class: gpr }
  37
  38 # CHECK:  body:
  39 # CHECK:   bb.0:
  40 # CHECK:    TBNZW %1, 0, %bb.1
  41 # CHECK:    B %bb.0
  42 body:             |
  43   bb.0:
  44     successors: %bb.0, %bb.1
  45     %1(s32) = COPY $w0
  46     G_BRCOND %1, %bb.1
  47     G_BR %bb.0
  48
  49   bb.1:
  50 ...
  51
  52 ---
  53 # CHECK-LABEL: name: indirect_br
  54 name:            indirect_br
  55 legalized:       true
  56 regBankSelected: true
  57
  58 registers:
  59   - { id: 0, class: gpr }
  60
  61 # CHECK:  body:
  62 # CHECK:   bb.0:
  63 # CHECK:    %0:gpr64 = COPY $x0
  64 # CHECK:    BR %0
  65 body:             |
  66   bb.0:
  67     successors: %bb.0, %bb.1
  68     %0(p0) = COPY $x0
  69     G_BRINDIRECT %0(p0)
  70
  71   bb.1:
  72 ...