| blob | b6e831b73df97cbd88079047065f4d8119c7a728 |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s
4 ...
5 ---
6 name: test_f16.rint
7 alignment: 4
8 legalized: true
9 regBankSelected: true
10 tracksRegLiveness: true
11 machineFunctionInfo: {}
12 body: |
13 bb.0:
14 liveins: $h0
16 ; CHECK-LABEL: name: test_f16.rint
17 ; CHECK: liveins: $h0
18 ; CHECK-NEXT: {{ $}}
19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
20 ; CHECK-NEXT: %1:fpr32 = nofpexcept FCVTSHr [[COPY]], implicit $fpcr
21 ; CHECK-NEXT: %2:fpr32 = nofpexcept FRINTXSr %1, implicit $fpcr
22 ; CHECK-NEXT: %3:fpr16 = nofpexcept FCVTHSr %2, implicit $fpcr
23 ; CHECK-NEXT: $h0 = COPY %3
24 ; CHECK-NEXT: RET_ReallyLR implicit $h0
25 %0:fpr(s16) = COPY $h0
26 %2:fpr(s32) = G_FPEXT %0(s16)
27 %3:fpr(s32) = G_FRINT %2
28 %1:fpr(s16) = G_FPTRUNC %3(s32)
29 $h0 = COPY %1(s16)
30 RET_ReallyLR implicit $h0
32 ...
33 ---
34 name: test_v4f16.rint
35 alignment: 4
36 legalized: true
37 regBankSelected: true
38 tracksRegLiveness: true
39 machineFunctionInfo: {}
40 body: |
41 bb.0:
42 liveins: $d0
44 ; CHECK-LABEL: name: test_v4f16.rint
45 ; CHECK: liveins: $d0
46 ; CHECK-NEXT: {{ $}}
47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
48 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
49 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
50 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
51 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
52 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
53 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
54 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
55 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
56 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2
57 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3
58 ; CHECK-NEXT: %5:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr
59 ; CHECK-NEXT: %6:fpr32 = nofpexcept FRINTXSr %5, implicit $fpcr
60 ; CHECK-NEXT: %7:fpr16 = nofpexcept FCVTHSr %6, implicit $fpcr
61 ; CHECK-NEXT: %8:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr
62 ; CHECK-NEXT: %9:fpr32 = nofpexcept FRINTXSr %8, implicit $fpcr
63 ; CHECK-NEXT: %10:fpr16 = nofpexcept FCVTHSr %9, implicit $fpcr
64 ; CHECK-NEXT: %11:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr
65 ; CHECK-NEXT: %12:fpr32 = nofpexcept FRINTXSr %11, implicit $fpcr
66 ; CHECK-NEXT: %13:fpr16 = nofpexcept FCVTHSr %12, implicit $fpcr
67 ; CHECK-NEXT: %14:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr
68 ; CHECK-NEXT: %15:fpr32 = nofpexcept FRINTXSr %14, implicit $fpcr
69 ; CHECK-NEXT: %16:fpr16 = nofpexcept FCVTHSr %15, implicit $fpcr
70 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
71 ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %7, %subreg.hsub
72 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
73 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %10, %subreg.hsub
74 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
75 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
76 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %13, %subreg.hsub
77 ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
78 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
79 ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %16, %subreg.hsub
80 ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
81 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
82 ; CHECK-NEXT: $d0 = COPY [[COPY2]]
83 ; CHECK-NEXT: RET_ReallyLR implicit $d0
84 %0:fpr(<4 x s16>) = COPY $d0
85 %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
86 %16:fpr(s32) = G_FPEXT %2(s16)
87 %17:fpr(s32) = G_FRINT %16
88 %6:fpr(s16) = G_FPTRUNC %17(s32)
89 %14:fpr(s32) = G_FPEXT %3(s16)
90 %15:fpr(s32) = G_FRINT %14
91 %7:fpr(s16) = G_FPTRUNC %15(s32)
92 %12:fpr(s32) = G_FPEXT %4(s16)
93 %13:fpr(s32) = G_FRINT %12
94 %8:fpr(s16) = G_FPTRUNC %13(s32)
95 %10:fpr(s32) = G_FPEXT %5(s16)
96 %11:fpr(s32) = G_FRINT %10
97 %9:fpr(s16) = G_FPTRUNC %11(s32)
98 %1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16)
99 $d0 = COPY %1(<4 x s16>)
100 RET_ReallyLR implicit $d0
102 ...
103 ---
104 name: test_v8f16.rint
105 alignment: 4
106 legalized: true
107 regBankSelected: true
108 tracksRegLiveness: true
109 machineFunctionInfo: {}
110 body: |
111 bb.0:
112 liveins: $q0
114 ; CHECK-LABEL: name: test_v8f16.rint
115 ; CHECK: liveins: $q0
116 ; CHECK-NEXT: {{ $}}
117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
119 ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
120 ; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 2
121 ; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 3
122 ; CHECK-NEXT: [[DUPi16_3:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 4
123 ; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5
124 ; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6
125 ; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7
126 ; CHECK-NEXT: %9:fpr32 = nofpexcept FCVTSHr [[COPY1]], implicit $fpcr
127 ; CHECK-NEXT: %10:fpr32 = nofpexcept FRINTXSr %9, implicit $fpcr
128 ; CHECK-NEXT: %11:fpr16 = nofpexcept FCVTHSr %10, implicit $fpcr
129 ; CHECK-NEXT: %12:fpr32 = nofpexcept FCVTSHr [[DUPi16_]], implicit $fpcr
130 ; CHECK-NEXT: %13:fpr32 = nofpexcept FRINTXSr %12, implicit $fpcr
131 ; CHECK-NEXT: %14:fpr16 = nofpexcept FCVTHSr %13, implicit $fpcr
132 ; CHECK-NEXT: %15:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]], implicit $fpcr
133 ; CHECK-NEXT: %16:fpr32 = nofpexcept FRINTXSr %15, implicit $fpcr
134 ; CHECK-NEXT: %17:fpr16 = nofpexcept FCVTHSr %16, implicit $fpcr
135 ; CHECK-NEXT: %18:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]], implicit $fpcr
136 ; CHECK-NEXT: %19:fpr32 = nofpexcept FRINTXSr %18, implicit $fpcr
137 ; CHECK-NEXT: %20:fpr16 = nofpexcept FCVTHSr %19, implicit $fpcr
138 ; CHECK-NEXT: %21:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]], implicit $fpcr
139 ; CHECK-NEXT: %22:fpr32 = nofpexcept FRINTXSr %21, implicit $fpcr
140 ; CHECK-NEXT: %23:fpr16 = nofpexcept FCVTHSr %22, implicit $fpcr
141 ; CHECK-NEXT: %24:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]], implicit $fpcr
142 ; CHECK-NEXT: %25:fpr32 = nofpexcept FRINTXSr %24, implicit $fpcr
143 ; CHECK-NEXT: %26:fpr16 = nofpexcept FCVTHSr %25, implicit $fpcr
144 ; CHECK-NEXT: %27:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]], implicit $fpcr
145 ; CHECK-NEXT: %28:fpr32 = nofpexcept FRINTXSr %27, implicit $fpcr
146 ; CHECK-NEXT: %29:fpr16 = nofpexcept FCVTHSr %28, implicit $fpcr
147 ; CHECK-NEXT: %30:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]], implicit $fpcr
148 ; CHECK-NEXT: %31:fpr32 = nofpexcept FRINTXSr %30, implicit $fpcr
149 ; CHECK-NEXT: %32:fpr16 = nofpexcept FCVTHSr %31, implicit $fpcr
150 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
151 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %11, %subreg.hsub
152 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
153 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %14, %subreg.hsub
154 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
155 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
156 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %17, %subreg.hsub
157 ; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
158 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
159 ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %20, %subreg.hsub
160 ; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
161 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
162 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %23, %subreg.hsub
163 ; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
164 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
165 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %26, %subreg.hsub
166 ; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
167 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
168 ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %29, %subreg.hsub
169 ; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
170 ; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
171 ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], %32, %subreg.hsub
172 ; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
173 ; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
174 ; CHECK-NEXT: RET_ReallyLR implicit $q0
175 %0:fpr(<8 x s16>) = COPY $q0
176 %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
177 %32:fpr(s32) = G_FPEXT %2(s16)
178 %33:fpr(s32) = G_FRINT %32
179 %10:fpr(s16) = G_FPTRUNC %33(s32)
180 %30:fpr(s32) = G_FPEXT %3(s16)
181 %31:fpr(s32) = G_FRINT %30
182 %11:fpr(s16) = G_FPTRUNC %31(s32)
183 %28:fpr(s32) = G_FPEXT %4(s16)
184 %29:fpr(s32) = G_FRINT %28
185 %12:fpr(s16) = G_FPTRUNC %29(s32)
186 %26:fpr(s32) = G_FPEXT %5(s16)
187 %27:fpr(s32) = G_FRINT %26
188 %13:fpr(s16) = G_FPTRUNC %27(s32)
189 %24:fpr(s32) = G_FPEXT %6(s16)
190 %25:fpr(s32) = G_FRINT %24
191 %14:fpr(s16) = G_FPTRUNC %25(s32)
192 %22:fpr(s32) = G_FPEXT %7(s16)
193 %23:fpr(s32) = G_FRINT %22
194 %15:fpr(s16) = G_FPTRUNC %23(s32)
195 %20:fpr(s32) = G_FPEXT %8(s16)
196 %21:fpr(s32) = G_FRINT %20
197 %16:fpr(s16) = G_FPTRUNC %21(s32)
198 %18:fpr(s32) = G_FPEXT %9(s16)
199 %19:fpr(s32) = G_FRINT %18
200 %17:fpr(s16) = G_FPTRUNC %19(s32)
201 %1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16)
202 $q0 = COPY %1(<8 x s16>)
203 RET_ReallyLR implicit $q0