| blob | 30db00aa97813f35bd4b30371327b670137f936a |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3 #
4 # Test that we can produce a TBNZ when we have a slt compare against 0.
5 #
6 # The bit tested should be the size of the test register minus 1.
7 #
9 ...
10 ---
11 name: tbnzx_slt
12 alignment: 4
13 legalized: true
14 regBankSelected: true
15 body: |
16 ; CHECK-LABEL: name: tbnzx_slt
17 ; CHECK: bb.0:
18 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
19 ; CHECK-NEXT: liveins: $x0
20 ; CHECK-NEXT: {{ $}}
21 ; CHECK-NEXT: %copy:gpr64 = COPY $x0
22 ; CHECK-NEXT: TBNZX %copy, 63, %bb.1
23 ; CHECK-NEXT: B %bb.0
24 ; CHECK-NEXT: {{ $}}
25 ; CHECK-NEXT: bb.1:
26 ; CHECK-NEXT: RET_ReallyLR
27 bb.0:
28 successors: %bb.0, %bb.1
29 liveins: $x0
30 %copy:gpr(s64) = COPY $x0
31 %zero:gpr(s64) = G_CONSTANT i64 0
32 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s64), %zero
33 G_BRCOND %cmp, %bb.1
34 G_BR %bb.0
35 bb.1:
36 RET_ReallyLR
38 ...
39 ---
40 name: tbnzw_slt
41 alignment: 4
42 legalized: true
43 regBankSelected: true
44 body: |
45 ; CHECK-LABEL: name: tbnzw_slt
46 ; CHECK: bb.0:
47 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
48 ; CHECK-NEXT: liveins: $x0
49 ; CHECK-NEXT: {{ $}}
50 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
51 ; CHECK-NEXT: TBNZW %copy, 31, %bb.1
52 ; CHECK-NEXT: B %bb.0
53 ; CHECK-NEXT: {{ $}}
54 ; CHECK-NEXT: bb.1:
55 ; CHECK-NEXT: RET_ReallyLR
56 bb.0:
57 successors: %bb.0, %bb.1
58 liveins: $x0
59 %copy:gpr(s32) = COPY $w0
60 %zero:gpr(s32) = G_CONSTANT i32 0
61 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %zero
62 G_BRCOND %cmp, %bb.1
63 G_BR %bb.0
64 bb.1:
65 RET_ReallyLR
67 ...
68 ---
69 name: tbnzx_sge
70 alignment: 4
71 legalized: true
72 regBankSelected: true
73 body: |
74 ; CHECK-LABEL: name: tbnzx_sge
75 ; CHECK: bb.0:
76 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
77 ; CHECK-NEXT: liveins: $x0
78 ; CHECK-NEXT: {{ $}}
79 ; CHECK-NEXT: %copy:gpr64 = COPY $x0
80 ; CHECK-NEXT: TBZX %copy, 63, %bb.1
81 ; CHECK-NEXT: B %bb.0
82 ; CHECK-NEXT: {{ $}}
83 ; CHECK-NEXT: bb.1:
84 ; CHECK-NEXT: RET_ReallyLR
85 bb.0:
86 successors: %bb.0, %bb.1
87 liveins: $x0
88 %copy:gpr(s64) = COPY $x0
89 %zero:gpr(s64) = G_CONSTANT i64 0
90 %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s64), %zero
91 G_BRCOND %cmp, %bb.1
92 G_BR %bb.0
93 bb.1:
94 RET_ReallyLR
96 ...
97 ---
98 name: tbnzw_sge
99 alignment: 4
100 legalized: true
101 regBankSelected: true
102 body: |
103 ; CHECK-LABEL: name: tbnzw_sge
104 ; CHECK: bb.0:
105 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
106 ; CHECK-NEXT: liveins: $x0
107 ; CHECK-NEXT: {{ $}}
108 ; CHECK-NEXT: %copy:gpr32 = COPY $w0
109 ; CHECK-NEXT: TBZW %copy, 31, %bb.1
110 ; CHECK-NEXT: B %bb.0
111 ; CHECK-NEXT: {{ $}}
112 ; CHECK-NEXT: bb.1:
113 ; CHECK-NEXT: RET_ReallyLR
114 bb.0:
115 successors: %bb.0, %bb.1
116 liveins: $x0
117 %copy:gpr(s32) = COPY $w0
118 %zero:gpr(s32) = G_CONSTANT i32 0
119 %cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s32), %zero
120 G_BRCOND %cmp, %bb.1
121 G_BR %bb.0
122 bb.1:
123 RET_ReallyLR
125 ...
126 ---
127 name: no_tbnz_not_zero
128 alignment: 4
129 legalized: true
130 regBankSelected: true
131 body: |
132 ; CHECK-LABEL: name: no_tbnz_not_zero
133 ; CHECK: bb.0:
134 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
135 ; CHECK-NEXT: liveins: $x0
136 ; CHECK-NEXT: {{ $}}
137 ; CHECK-NEXT: %copy:gpr32sp = COPY $w0
138 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
139 ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
140 ; CHECK-NEXT: B %bb.0
141 ; CHECK-NEXT: {{ $}}
142 ; CHECK-NEXT: bb.1:
143 ; CHECK-NEXT: RET_ReallyLR
144 bb.0:
145 successors: %bb.0, %bb.1
146 liveins: $x0
147 %copy:gpr(s32) = COPY $w0
148 %one:gpr(s32) = G_CONSTANT i32 1
149 %cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %one
150 G_BRCOND %cmp, %bb.1
151 G_BR %bb.0
152 bb.1:
153 RET_ReallyLR
155 ...
156 ---
157 name: dont_fold_and
158 alignment: 4
159 legalized: true
160 regBankSelected: true
161 body: |
162 ; CHECK-LABEL: name: dont_fold_and
163 ; CHECK: bb.0:
164 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
165 ; CHECK-NEXT: liveins: $x0
166 ; CHECK-NEXT: {{ $}}
167 ; CHECK-NEXT: %copy:gpr64 = COPY $x0
168 ; CHECK-NEXT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv
169 ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
170 ; CHECK-NEXT: B %bb.0
171 ; CHECK-NEXT: {{ $}}
172 ; CHECK-NEXT: bb.1:
173 ; CHECK-NEXT: RET_ReallyLR
174 bb.0:
175 successors: %bb.0, %bb.1
176 liveins: $x0
177 %copy:gpr(s64) = COPY $x0
178 %bit:gpr(s64) = G_CONSTANT i64 8
179 %zero:gpr(s64) = G_CONSTANT i64 0
180 %c:gpr(s64) = G_CONSTANT i64 8
181 %and:gpr(s64) = G_AND %copy, %bit
182 %cmp:gpr(s32) = G_ICMP intpred(slt), %and(s64), %zero
183 G_BRCOND %cmp, %bb.1
184 G_BR %bb.0
185 bb.1:
186 RET_ReallyLR
188 ...
189 ---
190 name: dont_commute
191 alignment: 4
192 legalized: true
193 regBankSelected: true
194 body: |
195 ; CHECK-LABEL: name: dont_commute
196 ; CHECK: bb.0:
197 ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
198 ; CHECK-NEXT: liveins: $x0
199 ; CHECK-NEXT: {{ $}}
200 ; CHECK-NEXT: %copy:gpr64 = COPY $x0
201 ; CHECK-NEXT: %zero:gpr64 = COPY $xzr
202 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %zero, %copy, implicit-def $nzcv
203 ; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
204 ; CHECK-NEXT: B %bb.0
205 ; CHECK-NEXT: {{ $}}
206 ; CHECK-NEXT: bb.1:
207 ; CHECK-NEXT: RET_ReallyLR
208 bb.0:
209 successors: %bb.0, %bb.1
210 liveins: $x0
211 %copy:gpr(s64) = COPY $x0
212 %zero:gpr(s64) = G_CONSTANT i64 0
213 %cmp:gpr(s32) = G_ICMP intpred(slt), %zero, %copy(s64)
214 G_BRCOND %cmp, %bb.1
215 G_BR %bb.0
216 bb.1:
217 RET_ReallyLR