1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -O3 < %s -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-gep-opt=false -verify-machineinstrs | FileCheck %s
3 target triple = "arm64-apple-ios"
6 ; CSE between "icmp reg reg" and "sub reg reg".
7 ; Both can be in the same basic block or in different basic blocks.
8 define ptr @t1(ptr %base, ptr nocapture %offset, i32 %size) nounwind {
10 ; CHECK: ; %bb.0: ; %entry
11 ; CHECK-NEXT: ldr w9, [x1]
12 ; CHECK-NEXT: subs w8, w9, w2
13 ; CHECK-NEXT: b.ge LBB0_2
14 ; CHECK-NEXT: ; %bb.1:
15 ; CHECK-NEXT: mov x0, xzr
17 ; CHECK-NEXT: LBB0_2: ; %if.end
18 ; CHECK-NEXT: add x0, x0, w8, sxtw
19 ; CHECK-NEXT: sub w9, w9, w8
20 ; CHECK-NEXT: str w9, [x1]
23 %0 = load i32, ptr %offset, align 4
24 %cmp = icmp slt i32 %0, %size
25 %s = sub nsw i32 %0, %size
26 br i1 %cmp, label %return, label %if.end
29 %sub = sub nsw i32 %0, %size
30 %s2 = sub nsw i32 %s, %size
31 %s3 = sub nsw i32 %sub, %s2
32 store i32 %s3, ptr %offset, align 4
33 %add.ptr = getelementptr inbounds i8, ptr %base, i32 %sub
37 %retval.0 = phi ptr [ %add.ptr, %if.end ], [ null, %entry ]
41 ; CSE between "icmp reg imm" and "sub reg imm".
42 define ptr @t2(ptr %base, ptr nocapture %offset) nounwind {
44 ; CHECK: ; %bb.0: ; %entry
45 ; CHECK-NEXT: ldr w8, [x1]
46 ; CHECK-NEXT: subs w8, w8, #1
47 ; CHECK-NEXT: b.lt LBB1_2
48 ; CHECK-NEXT: ; %bb.1: ; %if.end
49 ; CHECK-NEXT: add x0, x0, w8, sxtw
50 ; CHECK-NEXT: str w8, [x1]
53 ; CHECK-NEXT: mov x0, xzr
56 %0 = load i32, ptr %offset, align 4
57 %cmp = icmp slt i32 %0, 1
58 br i1 %cmp, label %return, label %if.end
61 %sub = sub nsw i32 %0, 1
62 store i32 %sub, ptr %offset, align 4
63 %add.ptr = getelementptr inbounds i8, ptr %base, i32 %sub
67 %retval.0 = phi ptr [ %add.ptr, %if.end ], [ null, %entry ]