| blob | eeb1504d8dc77ba6e0fb58dbcbc017313c404e9f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
3 ; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
5 ;
6 ; 32-bit float to signed integer
7 ;
9 declare i1 @llvm.fptosi.sat.i1.f32 (float)
10 declare i8 @llvm.fptosi.sat.i8.f32 (float)
11 declare i13 @llvm.fptosi.sat.i13.f32 (float)
12 declare i16 @llvm.fptosi.sat.i16.f32 (float)
13 declare i19 @llvm.fptosi.sat.i19.f32 (float)
14 declare i32 @llvm.fptosi.sat.i32.f32 (float)
15 declare i50 @llvm.fptosi.sat.i50.f32 (float)
16 declare i64 @llvm.fptosi.sat.i64.f32 (float)
17 declare i100 @llvm.fptosi.sat.i100.f32(float)
18 declare i128 @llvm.fptosi.sat.i128.f32(float)
20 define i1 @test_signed_i1_f32(float %f) nounwind {
21 ; CHECK-LABEL: test_signed_i1_f32:
22 ; CHECK: // %bb.0:
23 ; CHECK-NEXT: fcvtzs w8, s0
24 ; CHECK-NEXT: ands w8, w8, w8, asr #31
25 ; CHECK-NEXT: csinv w8, w8, wzr, ge
26 ; CHECK-NEXT: and w0, w8, #0x1
27 ; CHECK-NEXT: ret
28 %x = call i1 @llvm.fptosi.sat.i1.f32(float %f)
29 ret i1 %x
30 }
32 define i8 @test_signed_i8_f32(float %f) nounwind {
33 ; CHECK-LABEL: test_signed_i8_f32:
34 ; CHECK: // %bb.0:
35 ; CHECK-NEXT: fcvtzs w9, s0
36 ; CHECK-NEXT: mov w8, #127 // =0x7f
37 ; CHECK-NEXT: cmp w9, #127
38 ; CHECK-NEXT: csel w8, w9, w8, lt
39 ; CHECK-NEXT: mov w9, #-128 // =0xffffff80
40 ; CHECK-NEXT: cmn w8, #128
41 ; CHECK-NEXT: csel w0, w8, w9, gt
42 ; CHECK-NEXT: ret
43 %x = call i8 @llvm.fptosi.sat.i8.f32(float %f)
44 ret i8 %x
45 }
47 define i13 @test_signed_i13_f32(float %f) nounwind {
48 ; CHECK-LABEL: test_signed_i13_f32:
49 ; CHECK: // %bb.0:
50 ; CHECK-NEXT: fcvtzs w9, s0
51 ; CHECK-NEXT: mov w8, #4095 // =0xfff
52 ; CHECK-NEXT: cmp w9, #4095
53 ; CHECK-NEXT: csel w8, w9, w8, lt
54 ; CHECK-NEXT: mov w9, #-4096 // =0xfffff000
55 ; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
56 ; CHECK-NEXT: csel w0, w8, w9, gt
57 ; CHECK-NEXT: ret
58 %x = call i13 @llvm.fptosi.sat.i13.f32(float %f)
59 ret i13 %x
60 }
62 define i16 @test_signed_i16_f32(float %f) nounwind {
63 ; CHECK-LABEL: test_signed_i16_f32:
64 ; CHECK: // %bb.0:
65 ; CHECK-NEXT: fcvtzs w8, s0
66 ; CHECK-NEXT: mov w9, #32767 // =0x7fff
67 ; CHECK-NEXT: cmp w8, w9
68 ; CHECK-NEXT: csel w8, w8, w9, lt
69 ; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
70 ; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
71 ; CHECK-NEXT: csel w0, w8, w9, gt
72 ; CHECK-NEXT: ret
73 %x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
74 ret i16 %x
75 }
77 define i19 @test_signed_i19_f32(float %f) nounwind {
78 ; CHECK-LABEL: test_signed_i19_f32:
79 ; CHECK: // %bb.0:
80 ; CHECK-NEXT: fcvtzs w8, s0
81 ; CHECK-NEXT: mov w9, #262143 // =0x3ffff
82 ; CHECK-NEXT: cmp w8, w9
83 ; CHECK-NEXT: csel w8, w8, w9, lt
84 ; CHECK-NEXT: mov w9, #-262144 // =0xfffc0000
85 ; CHECK-NEXT: cmn w8, #64, lsl #12 // =262144
86 ; CHECK-NEXT: csel w0, w8, w9, gt
87 ; CHECK-NEXT: ret
88 %x = call i19 @llvm.fptosi.sat.i19.f32(float %f)
89 ret i19 %x
90 }
92 define i32 @test_signed_i32_f32(float %f) nounwind {
93 ; CHECK-LABEL: test_signed_i32_f32:
94 ; CHECK: // %bb.0:
95 ; CHECK-NEXT: fcvtzs w0, s0
96 ; CHECK-NEXT: ret
97 %x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
98 ret i32 %x
99 }
101 define i50 @test_signed_i50_f32(float %f) nounwind {
102 ; CHECK-LABEL: test_signed_i50_f32:
103 ; CHECK: // %bb.0:
104 ; CHECK-NEXT: fcvtzs x8, s0
105 ; CHECK-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
106 ; CHECK-NEXT: cmp x8, x9
107 ; CHECK-NEXT: csel x8, x8, x9, lt
108 ; CHECK-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
109 ; CHECK-NEXT: cmp x8, x9
110 ; CHECK-NEXT: csel x0, x8, x9, gt
111 ; CHECK-NEXT: ret
112 %x = call i50 @llvm.fptosi.sat.i50.f32(float %f)
113 ret i50 %x
114 }
116 define i64 @test_signed_i64_f32(float %f) nounwind {
117 ; CHECK-LABEL: test_signed_i64_f32:
118 ; CHECK: // %bb.0:
119 ; CHECK-NEXT: fcvtzs x0, s0
120 ; CHECK-NEXT: ret
121 %x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
122 ret i64 %x
123 }
125 define i100 @test_signed_i100_f32(float %f) nounwind {
126 ; CHECK-LABEL: test_signed_i100_f32:
127 ; CHECK: // %bb.0:
128 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
129 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
130 ; CHECK-NEXT: fmov s8, s0
131 ; CHECK-NEXT: bl __fixsfti
132 ; CHECK-NEXT: movi v0.2s, #241, lsl #24
133 ; CHECK-NEXT: mov w8, #1895825407 // =0x70ffffff
134 ; CHECK-NEXT: mov x10, #34359738367 // =0x7ffffffff
135 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
136 ; CHECK-NEXT: fcmp s8, s0
137 ; CHECK-NEXT: fmov s0, w8
138 ; CHECK-NEXT: mov x8, #-34359738368 // =0xfffffff800000000
139 ; CHECK-NEXT: csel x9, xzr, x0, lt
140 ; CHECK-NEXT: csel x8, x8, x1, lt
141 ; CHECK-NEXT: fcmp s8, s0
142 ; CHECK-NEXT: csel x8, x10, x8, gt
143 ; CHECK-NEXT: csinv x9, x9, xzr, le
144 ; CHECK-NEXT: fcmp s8, s8
145 ; CHECK-NEXT: csel x0, xzr, x9, vs
146 ; CHECK-NEXT: csel x1, xzr, x8, vs
147 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
148 ; CHECK-NEXT: ret
149 %x = call i100 @llvm.fptosi.sat.i100.f32(float %f)
150 ret i100 %x
151 }
153 define i128 @test_signed_i128_f32(float %f) nounwind {
154 ; CHECK-LABEL: test_signed_i128_f32:
155 ; CHECK: // %bb.0:
156 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
157 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
158 ; CHECK-NEXT: fmov s8, s0
159 ; CHECK-NEXT: bl __fixsfti
160 ; CHECK-NEXT: movi v0.2s, #255, lsl #24
161 ; CHECK-NEXT: mov w8, #2130706431 // =0x7effffff
162 ; CHECK-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
163 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
164 ; CHECK-NEXT: fcmp s8, s0
165 ; CHECK-NEXT: fmov s0, w8
166 ; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
167 ; CHECK-NEXT: csel x9, xzr, x0, lt
168 ; CHECK-NEXT: csel x8, x8, x1, lt
169 ; CHECK-NEXT: fcmp s8, s0
170 ; CHECK-NEXT: csel x8, x10, x8, gt
171 ; CHECK-NEXT: csinv x9, x9, xzr, le
172 ; CHECK-NEXT: fcmp s8, s8
173 ; CHECK-NEXT: csel x0, xzr, x9, vs
174 ; CHECK-NEXT: csel x1, xzr, x8, vs
175 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
176 ; CHECK-NEXT: ret
177 %x = call i128 @llvm.fptosi.sat.i128.f32(float %f)
178 ret i128 %x
179 }
181 ;
182 ; 64-bit float to signed integer
183 ;
185 declare i1 @llvm.fptosi.sat.i1.f64 (double)
186 declare i8 @llvm.fptosi.sat.i8.f64 (double)
187 declare i13 @llvm.fptosi.sat.i13.f64 (double)
188 declare i16 @llvm.fptosi.sat.i16.f64 (double)
189 declare i19 @llvm.fptosi.sat.i19.f64 (double)
190 declare i32 @llvm.fptosi.sat.i32.f64 (double)
191 declare i50 @llvm.fptosi.sat.i50.f64 (double)
192 declare i64 @llvm.fptosi.sat.i64.f64 (double)
193 declare i100 @llvm.fptosi.sat.i100.f64(double)
194 declare i128 @llvm.fptosi.sat.i128.f64(double)
196 define i1 @test_signed_i1_f64(double %f) nounwind {
197 ; CHECK-LABEL: test_signed_i1_f64:
198 ; CHECK: // %bb.0:
199 ; CHECK-NEXT: fcvtzs w8, d0
200 ; CHECK-NEXT: ands w8, w8, w8, asr #31
201 ; CHECK-NEXT: csinv w8, w8, wzr, ge
202 ; CHECK-NEXT: and w0, w8, #0x1
203 ; CHECK-NEXT: ret
204 %x = call i1 @llvm.fptosi.sat.i1.f64(double %f)
205 ret i1 %x
206 }
208 define i8 @test_signed_i8_f64(double %f) nounwind {
209 ; CHECK-LABEL: test_signed_i8_f64:
210 ; CHECK: // %bb.0:
211 ; CHECK-NEXT: fcvtzs w9, d0
212 ; CHECK-NEXT: mov w8, #127 // =0x7f
213 ; CHECK-NEXT: cmp w9, #127
214 ; CHECK-NEXT: csel w8, w9, w8, lt
215 ; CHECK-NEXT: mov w9, #-128 // =0xffffff80
216 ; CHECK-NEXT: cmn w8, #128
217 ; CHECK-NEXT: csel w0, w8, w9, gt
218 ; CHECK-NEXT: ret
219 %x = call i8 @llvm.fptosi.sat.i8.f64(double %f)
220 ret i8 %x
221 }
223 define i13 @test_signed_i13_f64(double %f) nounwind {
224 ; CHECK-LABEL: test_signed_i13_f64:
225 ; CHECK: // %bb.0:
226 ; CHECK-NEXT: fcvtzs w9, d0
227 ; CHECK-NEXT: mov w8, #4095 // =0xfff
228 ; CHECK-NEXT: cmp w9, #4095
229 ; CHECK-NEXT: csel w8, w9, w8, lt
230 ; CHECK-NEXT: mov w9, #-4096 // =0xfffff000
231 ; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
232 ; CHECK-NEXT: csel w0, w8, w9, gt
233 ; CHECK-NEXT: ret
234 %x = call i13 @llvm.fptosi.sat.i13.f64(double %f)
235 ret i13 %x
236 }
238 define i16 @test_signed_i16_f64(double %f) nounwind {
239 ; CHECK-LABEL: test_signed_i16_f64:
240 ; CHECK: // %bb.0:
241 ; CHECK-NEXT: fcvtzs w8, d0
242 ; CHECK-NEXT: mov w9, #32767 // =0x7fff
243 ; CHECK-NEXT: cmp w8, w9
244 ; CHECK-NEXT: csel w8, w8, w9, lt
245 ; CHECK-NEXT: mov w9, #-32768 // =0xffff8000
246 ; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
247 ; CHECK-NEXT: csel w0, w8, w9, gt
248 ; CHECK-NEXT: ret
249 %x = call i16 @llvm.fptosi.sat.i16.f64(double %f)
250 ret i16 %x
251 }
253 define i19 @test_signed_i19_f64(double %f) nounwind {
254 ; CHECK-LABEL: test_signed_i19_f64:
255 ; CHECK: // %bb.0:
256 ; CHECK-NEXT: fcvtzs w8, d0
257 ; CHECK-NEXT: mov w9, #262143 // =0x3ffff
258 ; CHECK-NEXT: cmp w8, w9
259 ; CHECK-NEXT: csel w8, w8, w9, lt
260 ; CHECK-NEXT: mov w9, #-262144 // =0xfffc0000
261 ; CHECK-NEXT: cmn w8, #64, lsl #12 // =262144
262 ; CHECK-NEXT: csel w0, w8, w9, gt
263 ; CHECK-NEXT: ret
264 %x = call i19 @llvm.fptosi.sat.i19.f64(double %f)
265 ret i19 %x
266 }
268 define i32 @test_signed_i32_f64(double %f) nounwind {
269 ; CHECK-LABEL: test_signed_i32_f64:
270 ; CHECK: // %bb.0:
271 ; CHECK-NEXT: fcvtzs w0, d0
272 ; CHECK-NEXT: ret
273 %x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
274 ret i32 %x
275 }
277 define i50 @test_signed_i50_f64(double %f) nounwind {
278 ; CHECK-LABEL: test_signed_i50_f64:
279 ; CHECK: // %bb.0:
280 ; CHECK-NEXT: fcvtzs x8, d0
281 ; CHECK-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
282 ; CHECK-NEXT: cmp x8, x9
283 ; CHECK-NEXT: csel x8, x8, x9, lt
284 ; CHECK-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
285 ; CHECK-NEXT: cmp x8, x9
286 ; CHECK-NEXT: csel x0, x8, x9, gt
287 ; CHECK-NEXT: ret
288 %x = call i50 @llvm.fptosi.sat.i50.f64(double %f)
289 ret i50 %x
290 }
292 define i64 @test_signed_i64_f64(double %f) nounwind {
293 ; CHECK-LABEL: test_signed_i64_f64:
294 ; CHECK: // %bb.0:
295 ; CHECK-NEXT: fcvtzs x0, d0
296 ; CHECK-NEXT: ret
297 %x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
298 ret i64 %x
299 }
301 define i100 @test_signed_i100_f64(double %f) nounwind {
302 ; CHECK-LABEL: test_signed_i100_f64:
303 ; CHECK: // %bb.0:
304 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
305 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
306 ; CHECK-NEXT: fmov d8, d0
307 ; CHECK-NEXT: bl __fixdfti
308 ; CHECK-NEXT: mov x8, #-4170333254945079296 // =0xc620000000000000
309 ; CHECK-NEXT: mov x10, #34359738367 // =0x7ffffffff
310 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
311 ; CHECK-NEXT: fmov d0, x8
312 ; CHECK-NEXT: mov x8, #5053038781909696511 // =0x461fffffffffffff
313 ; CHECK-NEXT: fcmp d8, d0
314 ; CHECK-NEXT: fmov d0, x8
315 ; CHECK-NEXT: mov x8, #-34359738368 // =0xfffffff800000000
316 ; CHECK-NEXT: csel x9, xzr, x0, lt
317 ; CHECK-NEXT: csel x8, x8, x1, lt
318 ; CHECK-NEXT: fcmp d8, d0
319 ; CHECK-NEXT: csel x8, x10, x8, gt
320 ; CHECK-NEXT: csinv x9, x9, xzr, le
321 ; CHECK-NEXT: fcmp d8, d8
322 ; CHECK-NEXT: csel x0, xzr, x9, vs
323 ; CHECK-NEXT: csel x1, xzr, x8, vs
324 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
325 ; CHECK-NEXT: ret
326 %x = call i100 @llvm.fptosi.sat.i100.f64(double %f)
327 ret i100 %x
328 }
330 define i128 @test_signed_i128_f64(double %f) nounwind {
331 ; CHECK-LABEL: test_signed_i128_f64:
332 ; CHECK: // %bb.0:
333 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
334 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
335 ; CHECK-NEXT: fmov d8, d0
336 ; CHECK-NEXT: bl __fixdfti
337 ; CHECK-NEXT: mov x8, #-4044232465378705408 // =0xc7e0000000000000
338 ; CHECK-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
339 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
340 ; CHECK-NEXT: fmov d0, x8
341 ; CHECK-NEXT: mov x8, #5179139571476070399 // =0x47dfffffffffffff
342 ; CHECK-NEXT: fcmp d8, d0
343 ; CHECK-NEXT: fmov d0, x8
344 ; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
345 ; CHECK-NEXT: csel x9, xzr, x0, lt
346 ; CHECK-NEXT: csel x8, x8, x1, lt
347 ; CHECK-NEXT: fcmp d8, d0
348 ; CHECK-NEXT: csel x8, x10, x8, gt
349 ; CHECK-NEXT: csinv x9, x9, xzr, le
350 ; CHECK-NEXT: fcmp d8, d8
351 ; CHECK-NEXT: csel x0, xzr, x9, vs
352 ; CHECK-NEXT: csel x1, xzr, x8, vs
353 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
354 ; CHECK-NEXT: ret
355 %x = call i128 @llvm.fptosi.sat.i128.f64(double %f)
356 ret i128 %x
357 }
359 ;
360 ; 16-bit float to signed integer
361 ;
363 declare i1 @llvm.fptosi.sat.i1.f16 (half)
364 declare i8 @llvm.fptosi.sat.i8.f16 (half)
365 declare i13 @llvm.fptosi.sat.i13.f16 (half)
366 declare i16 @llvm.fptosi.sat.i16.f16 (half)
367 declare i19 @llvm.fptosi.sat.i19.f16 (half)
368 declare i32 @llvm.fptosi.sat.i32.f16 (half)
369 declare i50 @llvm.fptosi.sat.i50.f16 (half)
370 declare i64 @llvm.fptosi.sat.i64.f16 (half)
371 declare i100 @llvm.fptosi.sat.i100.f16(half)
372 declare i128 @llvm.fptosi.sat.i128.f16(half)
374 define i1 @test_signed_i1_f16(half %f) nounwind {
375 ; CHECK-CVT-LABEL: test_signed_i1_f16:
376 ; CHECK-CVT: // %bb.0:
377 ; CHECK-CVT-NEXT: fcvt s0, h0
378 ; CHECK-CVT-NEXT: fcvtzs w8, s0
379 ; CHECK-CVT-NEXT: ands w8, w8, w8, asr #31
380 ; CHECK-CVT-NEXT: csinv w8, w8, wzr, ge
381 ; CHECK-CVT-NEXT: and w0, w8, #0x1
382 ; CHECK-CVT-NEXT: ret
383 ;
384 ; CHECK-FP16-LABEL: test_signed_i1_f16:
385 ; CHECK-FP16: // %bb.0:
386 ; CHECK-FP16-NEXT: fcvtzs w8, h0
387 ; CHECK-FP16-NEXT: ands w8, w8, w8, asr #31
388 ; CHECK-FP16-NEXT: csinv w8, w8, wzr, ge
389 ; CHECK-FP16-NEXT: and w0, w8, #0x1
390 ; CHECK-FP16-NEXT: ret
391 %x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
392 ret i1 %x
393 }
395 define i8 @test_signed_i8_f16(half %f) nounwind {
396 ; CHECK-CVT-LABEL: test_signed_i8_f16:
397 ; CHECK-CVT: // %bb.0:
398 ; CHECK-CVT-NEXT: fcvt s0, h0
399 ; CHECK-CVT-NEXT: mov w8, #127 // =0x7f
400 ; CHECK-CVT-NEXT: fcvtzs w9, s0
401 ; CHECK-CVT-NEXT: cmp w9, #127
402 ; CHECK-CVT-NEXT: csel w8, w9, w8, lt
403 ; CHECK-CVT-NEXT: mov w9, #-128 // =0xffffff80
404 ; CHECK-CVT-NEXT: cmn w8, #128
405 ; CHECK-CVT-NEXT: csel w0, w8, w9, gt
406 ; CHECK-CVT-NEXT: ret
407 ;
408 ; CHECK-FP16-LABEL: test_signed_i8_f16:
409 ; CHECK-FP16: // %bb.0:
410 ; CHECK-FP16-NEXT: fcvtzs w9, h0
411 ; CHECK-FP16-NEXT: mov w8, #127 // =0x7f
412 ; CHECK-FP16-NEXT: cmp w9, #127
413 ; CHECK-FP16-NEXT: csel w8, w9, w8, lt
414 ; CHECK-FP16-NEXT: mov w9, #-128 // =0xffffff80
415 ; CHECK-FP16-NEXT: cmn w8, #128
416 ; CHECK-FP16-NEXT: csel w0, w8, w9, gt
417 ; CHECK-FP16-NEXT: ret
418 %x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
419 ret i8 %x
420 }
422 define i13 @test_signed_i13_f16(half %f) nounwind {
423 ; CHECK-CVT-LABEL: test_signed_i13_f16:
424 ; CHECK-CVT: // %bb.0:
425 ; CHECK-CVT-NEXT: fcvt s0, h0
426 ; CHECK-CVT-NEXT: mov w8, #4095 // =0xfff
427 ; CHECK-CVT-NEXT: fcvtzs w9, s0
428 ; CHECK-CVT-NEXT: cmp w9, #4095
429 ; CHECK-CVT-NEXT: csel w8, w9, w8, lt
430 ; CHECK-CVT-NEXT: mov w9, #-4096 // =0xfffff000
431 ; CHECK-CVT-NEXT: cmn w8, #1, lsl #12 // =4096
432 ; CHECK-CVT-NEXT: csel w0, w8, w9, gt
433 ; CHECK-CVT-NEXT: ret
434 ;
435 ; CHECK-FP16-LABEL: test_signed_i13_f16:
436 ; CHECK-FP16: // %bb.0:
437 ; CHECK-FP16-NEXT: fcvtzs w9, h0
438 ; CHECK-FP16-NEXT: mov w8, #4095 // =0xfff
439 ; CHECK-FP16-NEXT: cmp w9, #4095
440 ; CHECK-FP16-NEXT: csel w8, w9, w8, lt
441 ; CHECK-FP16-NEXT: mov w9, #-4096 // =0xfffff000
442 ; CHECK-FP16-NEXT: cmn w8, #1, lsl #12 // =4096
443 ; CHECK-FP16-NEXT: csel w0, w8, w9, gt
444 ; CHECK-FP16-NEXT: ret
445 %x = call i13 @llvm.fptosi.sat.i13.f16(half %f)
446 ret i13 %x
447 }
449 define i16 @test_signed_i16_f16(half %f) nounwind {
450 ; CHECK-CVT-LABEL: test_signed_i16_f16:
451 ; CHECK-CVT: // %bb.0:
452 ; CHECK-CVT-NEXT: fcvt s0, h0
453 ; CHECK-CVT-NEXT: mov w9, #32767 // =0x7fff
454 ; CHECK-CVT-NEXT: fcvtzs w8, s0
455 ; CHECK-CVT-NEXT: cmp w8, w9
456 ; CHECK-CVT-NEXT: csel w8, w8, w9, lt
457 ; CHECK-CVT-NEXT: mov w9, #-32768 // =0xffff8000
458 ; CHECK-CVT-NEXT: cmn w8, #8, lsl #12 // =32768
459 ; CHECK-CVT-NEXT: csel w0, w8, w9, gt
460 ; CHECK-CVT-NEXT: ret
461 ;
462 ; CHECK-FP16-LABEL: test_signed_i16_f16:
463 ; CHECK-FP16: // %bb.0:
464 ; CHECK-FP16-NEXT: fcvtzs w8, h0
465 ; CHECK-FP16-NEXT: mov w9, #32767 // =0x7fff
466 ; CHECK-FP16-NEXT: cmp w8, w9
467 ; CHECK-FP16-NEXT: csel w8, w8, w9, lt
468 ; CHECK-FP16-NEXT: mov w9, #-32768 // =0xffff8000
469 ; CHECK-FP16-NEXT: cmn w8, #8, lsl #12 // =32768
470 ; CHECK-FP16-NEXT: csel w0, w8, w9, gt
471 ; CHECK-FP16-NEXT: ret
472 %x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
473 ret i16 %x
474 }
476 define i19 @test_signed_i19_f16(half %f) nounwind {
477 ; CHECK-CVT-LABEL: test_signed_i19_f16:
478 ; CHECK-CVT: // %bb.0:
479 ; CHECK-CVT-NEXT: fcvt s0, h0
480 ; CHECK-CVT-NEXT: mov w9, #262143 // =0x3ffff
481 ; CHECK-CVT-NEXT: fcvtzs w8, s0
482 ; CHECK-CVT-NEXT: cmp w8, w9
483 ; CHECK-CVT-NEXT: csel w8, w8, w9, lt
484 ; CHECK-CVT-NEXT: mov w9, #-262144 // =0xfffc0000
485 ; CHECK-CVT-NEXT: cmn w8, #64, lsl #12 // =262144
486 ; CHECK-CVT-NEXT: csel w0, w8, w9, gt
487 ; CHECK-CVT-NEXT: ret
488 ;
489 ; CHECK-FP16-LABEL: test_signed_i19_f16:
490 ; CHECK-FP16: // %bb.0:
491 ; CHECK-FP16-NEXT: fcvtzs w8, h0
492 ; CHECK-FP16-NEXT: mov w9, #262143 // =0x3ffff
493 ; CHECK-FP16-NEXT: cmp w8, w9
494 ; CHECK-FP16-NEXT: csel w8, w8, w9, lt
495 ; CHECK-FP16-NEXT: mov w9, #-262144 // =0xfffc0000
496 ; CHECK-FP16-NEXT: cmn w8, #64, lsl #12 // =262144
497 ; CHECK-FP16-NEXT: csel w0, w8, w9, gt
498 ; CHECK-FP16-NEXT: ret
499 %x = call i19 @llvm.fptosi.sat.i19.f16(half %f)
500 ret i19 %x
501 }
503 define i32 @test_signed_i32_f16(half %f) nounwind {
504 ; CHECK-CVT-LABEL: test_signed_i32_f16:
505 ; CHECK-CVT: // %bb.0:
506 ; CHECK-CVT-NEXT: fcvt s0, h0
507 ; CHECK-CVT-NEXT: fcvtzs w0, s0
508 ; CHECK-CVT-NEXT: ret
509 ;
510 ; CHECK-FP16-LABEL: test_signed_i32_f16:
511 ; CHECK-FP16: // %bb.0:
512 ; CHECK-FP16-NEXT: fcvtzs w0, h0
513 ; CHECK-FP16-NEXT: ret
514 %x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
515 ret i32 %x
516 }
518 define i50 @test_signed_i50_f16(half %f) nounwind {
519 ; CHECK-CVT-LABEL: test_signed_i50_f16:
520 ; CHECK-CVT: // %bb.0:
521 ; CHECK-CVT-NEXT: fcvt s0, h0
522 ; CHECK-CVT-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
523 ; CHECK-CVT-NEXT: fcvtzs x8, s0
524 ; CHECK-CVT-NEXT: cmp x8, x9
525 ; CHECK-CVT-NEXT: csel x8, x8, x9, lt
526 ; CHECK-CVT-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
527 ; CHECK-CVT-NEXT: cmp x8, x9
528 ; CHECK-CVT-NEXT: csel x0, x8, x9, gt
529 ; CHECK-CVT-NEXT: ret
530 ;
531 ; CHECK-FP16-LABEL: test_signed_i50_f16:
532 ; CHECK-FP16: // %bb.0:
533 ; CHECK-FP16-NEXT: fcvtzs x8, h0
534 ; CHECK-FP16-NEXT: mov x9, #562949953421311 // =0x1ffffffffffff
535 ; CHECK-FP16-NEXT: cmp x8, x9
536 ; CHECK-FP16-NEXT: csel x8, x8, x9, lt
537 ; CHECK-FP16-NEXT: mov x9, #-562949953421312 // =0xfffe000000000000
538 ; CHECK-FP16-NEXT: cmp x8, x9
539 ; CHECK-FP16-NEXT: csel x0, x8, x9, gt
540 ; CHECK-FP16-NEXT: ret
541 %x = call i50 @llvm.fptosi.sat.i50.f16(half %f)
542 ret i50 %x
543 }
545 define i64 @test_signed_i64_f16(half %f) nounwind {
546 ; CHECK-CVT-LABEL: test_signed_i64_f16:
547 ; CHECK-CVT: // %bb.0:
548 ; CHECK-CVT-NEXT: fcvt s0, h0
549 ; CHECK-CVT-NEXT: fcvtzs x0, s0
550 ; CHECK-CVT-NEXT: ret
551 ;
552 ; CHECK-FP16-LABEL: test_signed_i64_f16:
553 ; CHECK-FP16: // %bb.0:
554 ; CHECK-FP16-NEXT: fcvtzs x0, h0
555 ; CHECK-FP16-NEXT: ret
556 %x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
557 ret i64 %x
558 }
560 define i100 @test_signed_i100_f16(half %f) nounwind {
561 ; CHECK-LABEL: test_signed_i100_f16:
562 ; CHECK: // %bb.0:
563 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
564 ; CHECK-NEXT: fcvt s8, h0
565 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
566 ; CHECK-NEXT: fmov s0, s8
567 ; CHECK-NEXT: bl __fixsfti
568 ; CHECK-NEXT: movi v0.2s, #241, lsl #24
569 ; CHECK-NEXT: mov w8, #1895825407 // =0x70ffffff
570 ; CHECK-NEXT: mov x10, #34359738367 // =0x7ffffffff
571 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
572 ; CHECK-NEXT: fcmp s8, s0
573 ; CHECK-NEXT: fmov s0, w8
574 ; CHECK-NEXT: mov x8, #-34359738368 // =0xfffffff800000000
575 ; CHECK-NEXT: csel x9, xzr, x0, lt
576 ; CHECK-NEXT: csel x8, x8, x1, lt
577 ; CHECK-NEXT: fcmp s8, s0
578 ; CHECK-NEXT: csel x8, x10, x8, gt
579 ; CHECK-NEXT: csinv x9, x9, xzr, le
580 ; CHECK-NEXT: fcmp s8, s8
581 ; CHECK-NEXT: csel x0, xzr, x9, vs
582 ; CHECK-NEXT: csel x1, xzr, x8, vs
583 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
584 ; CHECK-NEXT: ret
585 %x = call i100 @llvm.fptosi.sat.i100.f16(half %f)
586 ret i100 %x
587 }
589 define i128 @test_signed_i128_f16(half %f) nounwind {
590 ; CHECK-LABEL: test_signed_i128_f16:
591 ; CHECK: // %bb.0:
592 ; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
593 ; CHECK-NEXT: fcvt s8, h0
594 ; CHECK-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
595 ; CHECK-NEXT: fmov s0, s8
596 ; CHECK-NEXT: bl __fixsfti
597 ; CHECK-NEXT: movi v0.2s, #255, lsl #24
598 ; CHECK-NEXT: mov w8, #2130706431 // =0x7effffff
599 ; CHECK-NEXT: mov x10, #9223372036854775807 // =0x7fffffffffffffff
600 ; CHECK-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
601 ; CHECK-NEXT: fcmp s8, s0
602 ; CHECK-NEXT: fmov s0, w8
603 ; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
604 ; CHECK-NEXT: csel x9, xzr, x0, lt
605 ; CHECK-NEXT: csel x8, x8, x1, lt
606 ; CHECK-NEXT: fcmp s8, s0
607 ; CHECK-NEXT: csel x8, x10, x8, gt
608 ; CHECK-NEXT: csinv x9, x9, xzr, le
609 ; CHECK-NEXT: fcmp s8, s8
610 ; CHECK-NEXT: csel x0, xzr, x9, vs
611 ; CHECK-NEXT: csel x1, xzr, x8, vs
612 ; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
613 ; CHECK-NEXT: ret
614 %x = call i128 @llvm.fptosi.sat.i128.f16(half %f)
615 ret i128 %x
616 }