| blob | 1919a42e0a2f8ce4261c79c4210335238c0fe88e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) {
6 ; CHECK-LABEL: cmeq8xi8:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
9 ; CHECK-NEXT: ret
10 %tmp3 = icmp eq <8 x i8> %A, %B;
11 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
12 ret <8 x i8> %tmp4
13 }
15 define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) {
16 ; CHECK-LABEL: cmeq16xi8:
17 ; CHECK: // %bb.0:
18 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
19 ; CHECK-NEXT: ret
20 %tmp3 = icmp eq <16 x i8> %A, %B;
21 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
22 ret <16 x i8> %tmp4
23 }
25 define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) {
26 ; CHECK-LABEL: cmeq4xi16:
27 ; CHECK: // %bb.0:
28 ; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h
29 ; CHECK-NEXT: ret
30 %tmp3 = icmp eq <4 x i16> %A, %B;
31 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
32 ret <4 x i16> %tmp4
33 }
35 define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) {
36 ; CHECK-LABEL: cmeq8xi16:
37 ; CHECK: // %bb.0:
38 ; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h
39 ; CHECK-NEXT: ret
40 %tmp3 = icmp eq <8 x i16> %A, %B;
41 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
42 ret <8 x i16> %tmp4
43 }
45 define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) {
46 ; CHECK-LABEL: cmeq2xi32:
47 ; CHECK: // %bb.0:
48 ; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s
49 ; CHECK-NEXT: ret
50 %tmp3 = icmp eq <2 x i32> %A, %B;
51 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
52 ret <2 x i32> %tmp4
53 }
55 define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) {
56 ; CHECK-LABEL: cmeq4xi32:
57 ; CHECK: // %bb.0:
58 ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
59 ; CHECK-NEXT: ret
60 %tmp3 = icmp eq <4 x i32> %A, %B;
61 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
62 ret <4 x i32> %tmp4
63 }
65 define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
66 ; CHECK-LABEL: cmeq2xi64:
67 ; CHECK: // %bb.0:
68 ; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d
69 ; CHECK-NEXT: ret
70 %tmp3 = icmp eq <2 x i64> %A, %B;
71 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
72 ret <2 x i64> %tmp4
73 }
75 define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
76 ; CHECK-LABEL: cmne8xi8:
77 ; CHECK: // %bb.0:
78 ; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
79 ; CHECK-NEXT: mvn v0.8b, v0.8b
80 ; CHECK-NEXT: ret
81 %tmp3 = icmp ne <8 x i8> %A, %B;
82 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
83 ret <8 x i8> %tmp4
84 }
86 define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
87 ; CHECK-LABEL: cmne16xi8:
88 ; CHECK: // %bb.0:
89 ; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
90 ; CHECK-NEXT: mvn v0.16b, v0.16b
91 ; CHECK-NEXT: ret
92 %tmp3 = icmp ne <16 x i8> %A, %B;
93 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
94 ret <16 x i8> %tmp4
95 }
97 define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
98 ; CHECK-LABEL: cmne4xi16:
99 ; CHECK: // %bb.0:
100 ; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h
101 ; CHECK-NEXT: mvn v0.8b, v0.8b
102 ; CHECK-NEXT: ret
103 %tmp3 = icmp ne <4 x i16> %A, %B;
104 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
105 ret <4 x i16> %tmp4
106 }
108 define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
109 ; CHECK-LABEL: cmne8xi16:
110 ; CHECK: // %bb.0:
111 ; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h
112 ; CHECK-NEXT: mvn v0.16b, v0.16b
113 ; CHECK-NEXT: ret
114 %tmp3 = icmp ne <8 x i16> %A, %B;
115 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
116 ret <8 x i16> %tmp4
117 }
119 define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
120 ; CHECK-LABEL: cmne2xi32:
121 ; CHECK: // %bb.0:
122 ; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s
123 ; CHECK-NEXT: mvn v0.8b, v0.8b
124 ; CHECK-NEXT: ret
125 %tmp3 = icmp ne <2 x i32> %A, %B;
126 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
127 ret <2 x i32> %tmp4
128 }
130 define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
131 ; CHECK-LABEL: cmne4xi32:
132 ; CHECK: // %bb.0:
133 ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
134 ; CHECK-NEXT: mvn v0.16b, v0.16b
135 ; CHECK-NEXT: ret
136 %tmp3 = icmp ne <4 x i32> %A, %B;
137 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
138 ret <4 x i32> %tmp4
139 }
141 define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
142 ; CHECK-LABEL: cmne2xi64:
143 ; CHECK: // %bb.0:
144 ; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d
145 ; CHECK-NEXT: mvn v0.16b, v0.16b
146 ; CHECK-NEXT: ret
147 %tmp3 = icmp ne <2 x i64> %A, %B;
148 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
149 ret <2 x i64> %tmp4
150 }
152 define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) {
153 ; CHECK-LABEL: cmgt8xi8:
154 ; CHECK: // %bb.0:
155 ; CHECK-NEXT: cmgt v0.8b, v0.8b, v1.8b
156 ; CHECK-NEXT: ret
157 %tmp3 = icmp sgt <8 x i8> %A, %B;
158 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
159 ret <8 x i8> %tmp4
160 }
162 define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) {
163 ; CHECK-LABEL: cmgt16xi8:
164 ; CHECK: // %bb.0:
165 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v1.16b
166 ; CHECK-NEXT: ret
167 %tmp3 = icmp sgt <16 x i8> %A, %B;
168 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
169 ret <16 x i8> %tmp4
170 }
172 define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) {
173 ; CHECK-LABEL: cmgt4xi16:
174 ; CHECK: // %bb.0:
175 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h
176 ; CHECK-NEXT: ret
177 %tmp3 = icmp sgt <4 x i16> %A, %B;
178 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
179 ret <4 x i16> %tmp4
180 }
182 define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) {
183 ; CHECK-LABEL: cmgt8xi16:
184 ; CHECK: // %bb.0:
185 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v1.8h
186 ; CHECK-NEXT: ret
187 %tmp3 = icmp sgt <8 x i16> %A, %B;
188 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
189 ret <8 x i16> %tmp4
190 }
192 define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) {
193 ; CHECK-LABEL: cmgt2xi32:
194 ; CHECK: // %bb.0:
195 ; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s
196 ; CHECK-NEXT: ret
197 %tmp3 = icmp sgt <2 x i32> %A, %B;
198 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
199 ret <2 x i32> %tmp4
200 }
202 define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) {
203 ; CHECK-LABEL: cmgt4xi32:
204 ; CHECK: // %bb.0:
205 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
206 ; CHECK-NEXT: ret
207 %tmp3 = icmp sgt <4 x i32> %A, %B;
208 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
209 ret <4 x i32> %tmp4
210 }
212 define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) {
213 ; CHECK-LABEL: cmgt2xi64:
214 ; CHECK: // %bb.0:
215 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v1.2d
216 ; CHECK-NEXT: ret
217 %tmp3 = icmp sgt <2 x i64> %A, %B;
218 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
219 ret <2 x i64> %tmp4
220 }
222 ; LT implemented as GT, so check reversed operands.
223 define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) {
224 ; CHECK-LABEL: cmlt8xi8:
225 ; CHECK: // %bb.0:
226 ; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b
227 ; CHECK-NEXT: ret
228 %tmp3 = icmp slt <8 x i8> %A, %B;
229 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
230 ret <8 x i8> %tmp4
231 }
233 ; LT implemented as GT, so check reversed operands.
234 define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) {
235 ; CHECK-LABEL: cmlt16xi8:
236 ; CHECK: // %bb.0:
237 ; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b
238 ; CHECK-NEXT: ret
239 %tmp3 = icmp slt <16 x i8> %A, %B;
240 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
241 ret <16 x i8> %tmp4
242 }
244 ; LT implemented as GT, so check reversed operands.
245 define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) {
246 ; CHECK-LABEL: cmlt4xi16:
247 ; CHECK: // %bb.0:
248 ; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h
249 ; CHECK-NEXT: ret
250 %tmp3 = icmp slt <4 x i16> %A, %B;
251 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
252 ret <4 x i16> %tmp4
253 }
255 ; LT implemented as GT, so check reversed operands.
256 define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) {
257 ; CHECK-LABEL: cmlt8xi16:
258 ; CHECK: // %bb.0:
259 ; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h
260 ; CHECK-NEXT: ret
261 %tmp3 = icmp slt <8 x i16> %A, %B;
262 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
263 ret <8 x i16> %tmp4
264 }
266 ; LT implemented as GT, so check reversed operands.
267 define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) {
268 ; CHECK-LABEL: cmlt2xi32:
269 ; CHECK: // %bb.0:
270 ; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s
271 ; CHECK-NEXT: ret
272 %tmp3 = icmp slt <2 x i32> %A, %B;
273 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
274 ret <2 x i32> %tmp4
275 }
277 ; LT implemented as GT, so check reversed operands.
278 define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) {
279 ; CHECK-LABEL: cmlt4xi32:
280 ; CHECK: // %bb.0:
281 ; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s
282 ; CHECK-NEXT: ret
283 %tmp3 = icmp slt <4 x i32> %A, %B;
284 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
285 ret <4 x i32> %tmp4
286 }
288 ; LT implemented as GT, so check reversed operands.
289 define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) {
290 ; CHECK-LABEL: cmlt2xi64:
291 ; CHECK: // %bb.0:
292 ; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d
293 ; CHECK-NEXT: ret
294 %tmp3 = icmp slt <2 x i64> %A, %B;
295 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
296 ret <2 x i64> %tmp4
297 }
299 define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) {
300 ; CHECK-LABEL: cmge8xi8:
301 ; CHECK: // %bb.0:
302 ; CHECK-NEXT: cmge v0.8b, v0.8b, v1.8b
303 ; CHECK-NEXT: ret
304 %tmp3 = icmp sge <8 x i8> %A, %B;
305 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
306 ret <8 x i8> %tmp4
307 }
309 define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) {
310 ; CHECK-LABEL: cmge16xi8:
311 ; CHECK: // %bb.0:
312 ; CHECK-NEXT: cmge v0.16b, v0.16b, v1.16b
313 ; CHECK-NEXT: ret
314 %tmp3 = icmp sge <16 x i8> %A, %B;
315 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
316 ret <16 x i8> %tmp4
317 }
319 define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) {
320 ; CHECK-LABEL: cmge4xi16:
321 ; CHECK: // %bb.0:
322 ; CHECK-NEXT: cmge v0.4h, v0.4h, v1.4h
323 ; CHECK-NEXT: ret
324 %tmp3 = icmp sge <4 x i16> %A, %B;
325 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
326 ret <4 x i16> %tmp4
327 }
329 define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) {
330 ; CHECK-LABEL: cmge8xi16:
331 ; CHECK: // %bb.0:
332 ; CHECK-NEXT: cmge v0.8h, v0.8h, v1.8h
333 ; CHECK-NEXT: ret
334 %tmp3 = icmp sge <8 x i16> %A, %B;
335 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
336 ret <8 x i16> %tmp4
337 }
339 define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) {
340 ; CHECK-LABEL: cmge2xi32:
341 ; CHECK: // %bb.0:
342 ; CHECK-NEXT: cmge v0.2s, v0.2s, v1.2s
343 ; CHECK-NEXT: ret
344 %tmp3 = icmp sge <2 x i32> %A, %B;
345 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
346 ret <2 x i32> %tmp4
347 }
349 define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) {
350 ; CHECK-LABEL: cmge4xi32:
351 ; CHECK: // %bb.0:
352 ; CHECK-NEXT: cmge v0.4s, v0.4s, v1.4s
353 ; CHECK-NEXT: ret
354 %tmp3 = icmp sge <4 x i32> %A, %B;
355 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
356 ret <4 x i32> %tmp4
357 }
359 define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) {
360 ; CHECK-LABEL: cmge2xi64:
361 ; CHECK: // %bb.0:
362 ; CHECK-NEXT: cmge v0.2d, v0.2d, v1.2d
363 ; CHECK-NEXT: ret
364 %tmp3 = icmp sge <2 x i64> %A, %B;
365 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
366 ret <2 x i64> %tmp4
367 }
369 ; LE implemented as GE, so check reversed operands.
370 define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) {
371 ; CHECK-LABEL: cmle8xi8:
372 ; CHECK: // %bb.0:
373 ; CHECK-NEXT: cmge v0.8b, v1.8b, v0.8b
374 ; CHECK-NEXT: ret
375 %tmp3 = icmp sle <8 x i8> %A, %B;
376 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
377 ret <8 x i8> %tmp4
378 }
380 ; LE implemented as GE, so check reversed operands.
381 define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) {
382 ; CHECK-LABEL: cmle16xi8:
383 ; CHECK: // %bb.0:
384 ; CHECK-NEXT: cmge v0.16b, v1.16b, v0.16b
385 ; CHECK-NEXT: ret
386 %tmp3 = icmp sle <16 x i8> %A, %B;
387 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
388 ret <16 x i8> %tmp4
389 }
391 ; LE implemented as GE, so check reversed operands.
392 define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) {
393 ; CHECK-LABEL: cmle4xi16:
394 ; CHECK: // %bb.0:
395 ; CHECK-NEXT: cmge v0.4h, v1.4h, v0.4h
396 ; CHECK-NEXT: ret
397 %tmp3 = icmp sle <4 x i16> %A, %B;
398 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
399 ret <4 x i16> %tmp4
400 }
402 ; LE implemented as GE, so check reversed operands.
403 define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) {
404 ; CHECK-LABEL: cmle8xi16:
405 ; CHECK: // %bb.0:
406 ; CHECK-NEXT: cmge v0.8h, v1.8h, v0.8h
407 ; CHECK-NEXT: ret
408 %tmp3 = icmp sle <8 x i16> %A, %B;
409 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
410 ret <8 x i16> %tmp4
411 }
413 ; LE implemented as GE, so check reversed operands.
414 define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) {
415 ; CHECK-LABEL: cmle2xi32:
416 ; CHECK: // %bb.0:
417 ; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s
418 ; CHECK-NEXT: ret
419 %tmp3 = icmp sle <2 x i32> %A, %B;
420 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
421 ret <2 x i32> %tmp4
422 }
424 ; LE implemented as GE, so check reversed operands.
425 define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) {
426 ; CHECK-LABEL: cmle4xi32:
427 ; CHECK: // %bb.0:
428 ; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s
429 ; CHECK-NEXT: ret
430 %tmp3 = icmp sle <4 x i32> %A, %B;
431 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
432 ret <4 x i32> %tmp4
433 }
435 ; LE implemented as GE, so check reversed operands.
436 define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) {
437 ; CHECK-LABEL: cmle2xi64:
438 ; CHECK: // %bb.0:
439 ; CHECK-NEXT: cmge v0.2d, v1.2d, v0.2d
440 ; CHECK-NEXT: ret
441 %tmp3 = icmp sle <2 x i64> %A, %B;
442 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
443 ret <2 x i64> %tmp4
444 }
446 define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) {
447 ; CHECK-LABEL: cmhi8xi8:
448 ; CHECK: // %bb.0:
449 ; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b
450 ; CHECK-NEXT: ret
451 %tmp3 = icmp ugt <8 x i8> %A, %B;
452 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
453 ret <8 x i8> %tmp4
454 }
456 define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) {
457 ; CHECK-LABEL: cmhi16xi8:
458 ; CHECK: // %bb.0:
459 ; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b
460 ; CHECK-NEXT: ret
461 %tmp3 = icmp ugt <16 x i8> %A, %B;
462 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
463 ret <16 x i8> %tmp4
464 }
466 define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) {
467 ; CHECK-LABEL: cmhi4xi16:
468 ; CHECK: // %bb.0:
469 ; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h
470 ; CHECK-NEXT: ret
471 %tmp3 = icmp ugt <4 x i16> %A, %B;
472 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
473 ret <4 x i16> %tmp4
474 }
476 define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) {
477 ; CHECK-LABEL: cmhi8xi16:
478 ; CHECK: // %bb.0:
479 ; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h
480 ; CHECK-NEXT: ret
481 %tmp3 = icmp ugt <8 x i16> %A, %B;
482 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
483 ret <8 x i16> %tmp4
484 }
486 define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) {
487 ; CHECK-LABEL: cmhi2xi32:
488 ; CHECK: // %bb.0:
489 ; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s
490 ; CHECK-NEXT: ret
491 %tmp3 = icmp ugt <2 x i32> %A, %B;
492 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
493 ret <2 x i32> %tmp4
494 }
496 define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) {
497 ; CHECK-LABEL: cmhi4xi32:
498 ; CHECK: // %bb.0:
499 ; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
500 ; CHECK-NEXT: ret
501 %tmp3 = icmp ugt <4 x i32> %A, %B;
502 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
503 ret <4 x i32> %tmp4
504 }
506 define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) {
507 ; CHECK-LABEL: cmhi2xi64:
508 ; CHECK: // %bb.0:
509 ; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
510 ; CHECK-NEXT: ret
511 %tmp3 = icmp ugt <2 x i64> %A, %B;
512 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
513 ret <2 x i64> %tmp4
514 }
516 ; LO implemented as HI, so check reversed operands.
517 define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) {
518 ; CHECK-LABEL: cmlo8xi8:
519 ; CHECK: // %bb.0:
520 ; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b
521 ; CHECK-NEXT: ret
522 %tmp3 = icmp ult <8 x i8> %A, %B;
523 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
524 ret <8 x i8> %tmp4
525 }
527 ; LO implemented as HI, so check reversed operands.
528 define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) {
529 ; CHECK-LABEL: cmlo16xi8:
530 ; CHECK: // %bb.0:
531 ; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b
532 ; CHECK-NEXT: ret
533 %tmp3 = icmp ult <16 x i8> %A, %B;
534 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
535 ret <16 x i8> %tmp4
536 }
538 ; LO implemented as HI, so check reversed operands.
539 define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) {
540 ; CHECK-LABEL: cmlo4xi16:
541 ; CHECK: // %bb.0:
542 ; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h
543 ; CHECK-NEXT: ret
544 %tmp3 = icmp ult <4 x i16> %A, %B;
545 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
546 ret <4 x i16> %tmp4
547 }
549 ; LO implemented as HI, so check reversed operands.
550 define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) {
551 ; CHECK-LABEL: cmlo8xi16:
552 ; CHECK: // %bb.0:
553 ; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h
554 ; CHECK-NEXT: ret
555 %tmp3 = icmp ult <8 x i16> %A, %B;
556 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
557 ret <8 x i16> %tmp4
558 }
560 ; LO implemented as HI, so check reversed operands.
561 define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) {
562 ; CHECK-LABEL: cmlo2xi32:
563 ; CHECK: // %bb.0:
564 ; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s
565 ; CHECK-NEXT: ret
566 %tmp3 = icmp ult <2 x i32> %A, %B;
567 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
568 ret <2 x i32> %tmp4
569 }
571 ; LO implemented as HI, so check reversed operands.
572 define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) {
573 ; CHECK-LABEL: cmlo4xi32:
574 ; CHECK: // %bb.0:
575 ; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
576 ; CHECK-NEXT: ret
577 %tmp3 = icmp ult <4 x i32> %A, %B;
578 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
579 ret <4 x i32> %tmp4
580 }
582 ; LO implemented as HI, so check reversed operands.
583 define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) {
584 ; CHECK-LABEL: cmlo2xi64:
585 ; CHECK: // %bb.0:
586 ; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
587 ; CHECK-NEXT: ret
588 %tmp3 = icmp ult <2 x i64> %A, %B;
589 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
590 ret <2 x i64> %tmp4
591 }
593 define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) {
594 ; CHECK-LABEL: cmhs8xi8:
595 ; CHECK: // %bb.0:
596 ; CHECK-NEXT: cmhs v0.8b, v0.8b, v1.8b
597 ; CHECK-NEXT: ret
598 %tmp3 = icmp uge <8 x i8> %A, %B;
599 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
600 ret <8 x i8> %tmp4
601 }
603 define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) {
604 ; CHECK-LABEL: cmhs16xi8:
605 ; CHECK: // %bb.0:
606 ; CHECK-NEXT: cmhs v0.16b, v0.16b, v1.16b
607 ; CHECK-NEXT: ret
608 %tmp3 = icmp uge <16 x i8> %A, %B;
609 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
610 ret <16 x i8> %tmp4
611 }
613 define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) {
614 ; CHECK-LABEL: cmhs4xi16:
615 ; CHECK: // %bb.0:
616 ; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h
617 ; CHECK-NEXT: ret
618 %tmp3 = icmp uge <4 x i16> %A, %B;
619 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
620 ret <4 x i16> %tmp4
621 }
623 define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) {
624 ; CHECK-LABEL: cmhs8xi16:
625 ; CHECK: // %bb.0:
626 ; CHECK-NEXT: cmhs v0.8h, v0.8h, v1.8h
627 ; CHECK-NEXT: ret
628 %tmp3 = icmp uge <8 x i16> %A, %B;
629 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
630 ret <8 x i16> %tmp4
631 }
633 define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) {
634 ; CHECK-LABEL: cmhs2xi32:
635 ; CHECK: // %bb.0:
636 ; CHECK-NEXT: cmhs v0.2s, v0.2s, v1.2s
637 ; CHECK-NEXT: ret
638 %tmp3 = icmp uge <2 x i32> %A, %B;
639 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
640 ret <2 x i32> %tmp4
641 }
643 define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) {
644 ; CHECK-LABEL: cmhs4xi32:
645 ; CHECK: // %bb.0:
646 ; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
647 ; CHECK-NEXT: ret
648 %tmp3 = icmp uge <4 x i32> %A, %B;
649 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
650 ret <4 x i32> %tmp4
651 }
653 define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) {
654 ; CHECK-LABEL: cmhs2xi64:
655 ; CHECK: // %bb.0:
656 ; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d
657 ; CHECK-NEXT: ret
658 %tmp3 = icmp uge <2 x i64> %A, %B;
659 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
660 ret <2 x i64> %tmp4
661 }
663 ; LS implemented as HS, so check reversed operands.
664 define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) {
665 ; CHECK-LABEL: cmls8xi8:
666 ; CHECK: // %bb.0:
667 ; CHECK-NEXT: cmhs v0.8b, v1.8b, v0.8b
668 ; CHECK-NEXT: ret
669 %tmp3 = icmp ule <8 x i8> %A, %B;
670 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
671 ret <8 x i8> %tmp4
672 }
674 ; LS implemented as HS, so check reversed operands.
675 define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) {
676 ; CHECK-LABEL: cmls16xi8:
677 ; CHECK: // %bb.0:
678 ; CHECK-NEXT: cmhs v0.16b, v1.16b, v0.16b
679 ; CHECK-NEXT: ret
680 %tmp3 = icmp ule <16 x i8> %A, %B;
681 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
682 ret <16 x i8> %tmp4
683 }
685 ; LS implemented as HS, so check reversed operands.
686 define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) {
687 ; CHECK-LABEL: cmls4xi16:
688 ; CHECK: // %bb.0:
689 ; CHECK-NEXT: cmhs v0.4h, v1.4h, v0.4h
690 ; CHECK-NEXT: ret
691 %tmp3 = icmp ule <4 x i16> %A, %B;
692 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
693 ret <4 x i16> %tmp4
694 }
696 ; LS implemented as HS, so check reversed operands.
697 define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) {
698 ; CHECK-LABEL: cmls8xi16:
699 ; CHECK: // %bb.0:
700 ; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h
701 ; CHECK-NEXT: ret
702 %tmp3 = icmp ule <8 x i16> %A, %B;
703 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
704 ret <8 x i16> %tmp4
705 }
707 ; LS implemented as HS, so check reversed operands.
708 define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) {
709 ; CHECK-LABEL: cmls2xi32:
710 ; CHECK: // %bb.0:
711 ; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s
712 ; CHECK-NEXT: ret
713 %tmp3 = icmp ule <2 x i32> %A, %B;
714 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
715 ret <2 x i32> %tmp4
716 }
718 ; LS implemented as HS, so check reversed operands.
719 define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) {
720 ; CHECK-LABEL: cmls4xi32:
721 ; CHECK: // %bb.0:
722 ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
723 ; CHECK-NEXT: ret
724 %tmp3 = icmp ule <4 x i32> %A, %B;
725 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
726 ret <4 x i32> %tmp4
727 }
729 ; LS implemented as HS, so check reversed operands.
730 define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) {
731 ; CHECK-LABEL: cmls2xi64:
732 ; CHECK: // %bb.0:
733 ; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d
734 ; CHECK-NEXT: ret
735 %tmp3 = icmp ule <2 x i64> %A, %B;
736 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
737 ret <2 x i64> %tmp4
738 }
740 define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
741 ; CHECK-SD-LABEL: cmtst8xi8:
742 ; CHECK-SD: // %bb.0:
743 ; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
744 ; CHECK-SD-NEXT: ret
745 ;
746 ; CHECK-GI-LABEL: cmtst8xi8:
747 ; CHECK-GI: // %bb.0:
748 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
749 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
750 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v2.8b
751 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
752 ; CHECK-GI-NEXT: ret
753 %tmp3 = and <8 x i8> %A, %B
754 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
755 %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
756 ret <8 x i8> %tmp5
757 }
759 define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
760 ; CHECK-SD-LABEL: cmtst16xi8:
761 ; CHECK-SD: // %bb.0:
762 ; CHECK-SD-NEXT: cmtst v0.16b, v0.16b, v1.16b
763 ; CHECK-SD-NEXT: ret
764 ;
765 ; CHECK-GI-LABEL: cmtst16xi8:
766 ; CHECK-GI: // %bb.0:
767 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
768 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
769 ; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v2.16b
770 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
771 ; CHECK-GI-NEXT: ret
772 %tmp3 = and <16 x i8> %A, %B
773 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
774 %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
775 ret <16 x i8> %tmp5
776 }
778 define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
779 ; CHECK-SD-LABEL: cmtst4xi16:
780 ; CHECK-SD: // %bb.0:
781 ; CHECK-SD-NEXT: cmtst v0.4h, v0.4h, v1.4h
782 ; CHECK-SD-NEXT: ret
783 ;
784 ; CHECK-GI-LABEL: cmtst4xi16:
785 ; CHECK-GI: // %bb.0:
786 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
787 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
788 ; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v2.4h
789 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
790 ; CHECK-GI-NEXT: ret
791 %tmp3 = and <4 x i16> %A, %B
792 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
793 %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
794 ret <4 x i16> %tmp5
795 }
797 define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
798 ; CHECK-SD-LABEL: cmtst8xi16:
799 ; CHECK-SD: // %bb.0:
800 ; CHECK-SD-NEXT: cmtst v0.8h, v0.8h, v1.8h
801 ; CHECK-SD-NEXT: ret
802 ;
803 ; CHECK-GI-LABEL: cmtst8xi16:
804 ; CHECK-GI: // %bb.0:
805 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
806 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
807 ; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v2.8h
808 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
809 ; CHECK-GI-NEXT: ret
810 %tmp3 = and <8 x i16> %A, %B
811 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
812 %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
813 ret <8 x i16> %tmp5
814 }
816 define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
817 ; CHECK-SD-LABEL: cmtst2xi32:
818 ; CHECK-SD: // %bb.0:
819 ; CHECK-SD-NEXT: cmtst v0.2s, v0.2s, v1.2s
820 ; CHECK-SD-NEXT: ret
821 ;
822 ; CHECK-GI-LABEL: cmtst2xi32:
823 ; CHECK-GI: // %bb.0:
824 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
825 ; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
826 ; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v2.2s
827 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
828 ; CHECK-GI-NEXT: ret
829 %tmp3 = and <2 x i32> %A, %B
830 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
831 %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
832 ret <2 x i32> %tmp5
833 }
835 define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
836 ; CHECK-SD-LABEL: cmtst4xi32:
837 ; CHECK-SD: // %bb.0:
838 ; CHECK-SD-NEXT: cmtst v0.4s, v0.4s, v1.4s
839 ; CHECK-SD-NEXT: ret
840 ;
841 ; CHECK-GI-LABEL: cmtst4xi32:
842 ; CHECK-GI: // %bb.0:
843 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
844 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
845 ; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v2.4s
846 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
847 ; CHECK-GI-NEXT: ret
848 %tmp3 = and <4 x i32> %A, %B
849 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
850 %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
851 ret <4 x i32> %tmp5
852 }
854 define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
855 ; CHECK-SD-LABEL: cmtst2xi64:
856 ; CHECK-SD: // %bb.0:
857 ; CHECK-SD-NEXT: cmtst v0.2d, v0.2d, v1.2d
858 ; CHECK-SD-NEXT: ret
859 ;
860 ; CHECK-GI-LABEL: cmtst2xi64:
861 ; CHECK-GI: // %bb.0:
862 ; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
863 ; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
864 ; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v2.2d
865 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
866 ; CHECK-GI-NEXT: ret
867 %tmp3 = and <2 x i64> %A, %B
868 %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer
869 %tmp5 = sext <2 x i1> %tmp4 to <2 x i64>
870 ret <2 x i64> %tmp5
871 }
875 define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
876 ; CHECK-SD-LABEL: cmeqz8xi8:
877 ; CHECK-SD: // %bb.0:
878 ; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
879 ; CHECK-SD-NEXT: ret
880 ;
881 ; CHECK-GI-LABEL: cmeqz8xi8:
882 ; CHECK-GI: // %bb.0:
883 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
884 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
885 ; CHECK-GI-NEXT: ret
886 %tmp3 = icmp eq <8 x i8> %A, zeroinitializer;
887 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
888 ret <8 x i8> %tmp4
889 }
891 define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
892 ; CHECK-SD-LABEL: cmeqz16xi8:
893 ; CHECK-SD: // %bb.0:
894 ; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
895 ; CHECK-SD-NEXT: ret
896 ;
897 ; CHECK-GI-LABEL: cmeqz16xi8:
898 ; CHECK-GI: // %bb.0:
899 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
900 ; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
901 ; CHECK-GI-NEXT: ret
902 %tmp3 = icmp eq <16 x i8> %A, zeroinitializer;
903 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
904 ret <16 x i8> %tmp4
905 }
907 define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
908 ; CHECK-SD-LABEL: cmeqz4xi16:
909 ; CHECK-SD: // %bb.0:
910 ; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
911 ; CHECK-SD-NEXT: ret
912 ;
913 ; CHECK-GI-LABEL: cmeqz4xi16:
914 ; CHECK-GI: // %bb.0:
915 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
916 ; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
917 ; CHECK-GI-NEXT: ret
918 %tmp3 = icmp eq <4 x i16> %A, zeroinitializer;
919 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
920 ret <4 x i16> %tmp4
921 }
923 define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
924 ; CHECK-SD-LABEL: cmeqz8xi16:
925 ; CHECK-SD: // %bb.0:
926 ; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
927 ; CHECK-SD-NEXT: ret
928 ;
929 ; CHECK-GI-LABEL: cmeqz8xi16:
930 ; CHECK-GI: // %bb.0:
931 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
932 ; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
933 ; CHECK-GI-NEXT: ret
934 %tmp3 = icmp eq <8 x i16> %A, zeroinitializer;
935 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
936 ret <8 x i16> %tmp4
937 }
939 define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
940 ; CHECK-SD-LABEL: cmeqz2xi32:
941 ; CHECK-SD: // %bb.0:
942 ; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
943 ; CHECK-SD-NEXT: ret
944 ;
945 ; CHECK-GI-LABEL: cmeqz2xi32:
946 ; CHECK-GI: // %bb.0:
947 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
948 ; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
949 ; CHECK-GI-NEXT: ret
950 %tmp3 = icmp eq <2 x i32> %A, zeroinitializer;
951 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
952 ret <2 x i32> %tmp4
953 }
955 define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
956 ; CHECK-SD-LABEL: cmeqz4xi32:
957 ; CHECK-SD: // %bb.0:
958 ; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
959 ; CHECK-SD-NEXT: ret
960 ;
961 ; CHECK-GI-LABEL: cmeqz4xi32:
962 ; CHECK-GI: // %bb.0:
963 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
964 ; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
965 ; CHECK-GI-NEXT: ret
966 %tmp3 = icmp eq <4 x i32> %A, zeroinitializer;
967 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
968 ret <4 x i32> %tmp4
969 }
971 define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
972 ; CHECK-SD-LABEL: cmeqz2xi64:
973 ; CHECK-SD: // %bb.0:
974 ; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
975 ; CHECK-SD-NEXT: ret
976 ;
977 ; CHECK-GI-LABEL: cmeqz2xi64:
978 ; CHECK-GI: // %bb.0:
979 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
980 ; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
981 ; CHECK-GI-NEXT: ret
982 %tmp3 = icmp eq <2 x i64> %A, zeroinitializer;
983 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
984 ret <2 x i64> %tmp4
985 }
988 define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
989 ; CHECK-SD-LABEL: cmgez8xi8:
990 ; CHECK-SD: // %bb.0:
991 ; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
992 ; CHECK-SD-NEXT: ret
993 ;
994 ; CHECK-GI-LABEL: cmgez8xi8:
995 ; CHECK-GI: // %bb.0:
996 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
997 ; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
998 ; CHECK-GI-NEXT: ret
999 %tmp3 = icmp sge <8 x i8> %A, zeroinitializer;
1000 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1001 ret <8 x i8> %tmp4
1002 }
1004 define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
1005 ; CHECK-SD-LABEL: cmgez16xi8:
1006 ; CHECK-SD: // %bb.0:
1007 ; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
1008 ; CHECK-SD-NEXT: ret
1009 ;
1010 ; CHECK-GI-LABEL: cmgez16xi8:
1011 ; CHECK-GI: // %bb.0:
1012 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1013 ; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
1014 ; CHECK-GI-NEXT: ret
1015 %tmp3 = icmp sge <16 x i8> %A, zeroinitializer;
1016 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1017 ret <16 x i8> %tmp4
1018 }
1020 define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
1021 ; CHECK-SD-LABEL: cmgez4xi16:
1022 ; CHECK-SD: // %bb.0:
1023 ; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
1024 ; CHECK-SD-NEXT: ret
1025 ;
1026 ; CHECK-GI-LABEL: cmgez4xi16:
1027 ; CHECK-GI: // %bb.0:
1028 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1029 ; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
1030 ; CHECK-GI-NEXT: ret
1031 %tmp3 = icmp sge <4 x i16> %A, zeroinitializer;
1032 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1033 ret <4 x i16> %tmp4
1034 }
1036 define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
1037 ; CHECK-SD-LABEL: cmgez8xi16:
1038 ; CHECK-SD: // %bb.0:
1039 ; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
1040 ; CHECK-SD-NEXT: ret
1041 ;
1042 ; CHECK-GI-LABEL: cmgez8xi16:
1043 ; CHECK-GI: // %bb.0:
1044 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1045 ; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
1046 ; CHECK-GI-NEXT: ret
1047 %tmp3 = icmp sge <8 x i16> %A, zeroinitializer;
1048 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1049 ret <8 x i16> %tmp4
1050 }
1052 define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
1053 ; CHECK-SD-LABEL: cmgez2xi32:
1054 ; CHECK-SD: // %bb.0:
1055 ; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
1056 ; CHECK-SD-NEXT: ret
1057 ;
1058 ; CHECK-GI-LABEL: cmgez2xi32:
1059 ; CHECK-GI: // %bb.0:
1060 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1061 ; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
1062 ; CHECK-GI-NEXT: ret
1063 %tmp3 = icmp sge <2 x i32> %A, zeroinitializer;
1064 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1065 ret <2 x i32> %tmp4
1066 }
1068 define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
1069 ; CHECK-SD-LABEL: cmgez4xi32:
1070 ; CHECK-SD: // %bb.0:
1071 ; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
1072 ; CHECK-SD-NEXT: ret
1073 ;
1074 ; CHECK-GI-LABEL: cmgez4xi32:
1075 ; CHECK-GI: // %bb.0:
1076 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1077 ; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
1078 ; CHECK-GI-NEXT: ret
1079 %tmp3 = icmp sge <4 x i32> %A, zeroinitializer;
1080 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1081 ret <4 x i32> %tmp4
1082 }
1084 define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
1085 ; CHECK-SD-LABEL: cmgez2xi64:
1086 ; CHECK-SD: // %bb.0:
1087 ; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
1088 ; CHECK-SD-NEXT: ret
1089 ;
1090 ; CHECK-GI-LABEL: cmgez2xi64:
1091 ; CHECK-GI: // %bb.0:
1092 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1093 ; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
1094 ; CHECK-GI-NEXT: ret
1095 %tmp3 = icmp sge <2 x i64> %A, zeroinitializer;
1096 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1097 ret <2 x i64> %tmp4
1098 }
1101 define <8 x i8> @cmgez8xi8_alt(<8 x i8> %A) {
1102 ; CHECK-SD-LABEL: cmgez8xi8_alt:
1103 ; CHECK-SD: // %bb.0:
1104 ; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
1105 ; CHECK-SD-NEXT: ret
1106 ;
1107 ; CHECK-GI-LABEL: cmgez8xi8_alt:
1108 ; CHECK-GI: // %bb.0:
1109 ; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7
1110 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1111 ; CHECK-GI-NEXT: ret
1112 %sign = ashr <8 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
1113 %not = xor <8 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1114 ret <8 x i8> %not
1115 }
1117 define <16 x i8> @cmgez16xi8_alt(<16 x i8> %A) {
1118 ; CHECK-SD-LABEL: cmgez16xi8_alt:
1119 ; CHECK-SD: // %bb.0:
1120 ; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
1121 ; CHECK-SD-NEXT: ret
1122 ;
1123 ; CHECK-GI-LABEL: cmgez16xi8_alt:
1124 ; CHECK-GI: // %bb.0:
1125 ; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
1126 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1127 ; CHECK-GI-NEXT: ret
1128 %sign = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
1129 %not = xor <16 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
1130 ret <16 x i8> %not
1131 }
1133 define <4 x i16> @cmgez4xi16_alt(<4 x i16> %A) {
1134 ; CHECK-SD-LABEL: cmgez4xi16_alt:
1135 ; CHECK-SD: // %bb.0:
1136 ; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
1137 ; CHECK-SD-NEXT: ret
1138 ;
1139 ; CHECK-GI-LABEL: cmgez4xi16_alt:
1140 ; CHECK-GI: // %bb.0:
1141 ; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #15
1142 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1143 ; CHECK-GI-NEXT: ret
1144 %sign = ashr <4 x i16> %A, <i16 15, i16 15, i16 15, i16 15>
1145 %not = xor <4 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1>
1146 ret <4 x i16> %not
1147 }
1149 define <8 x i16> @cmgez8xi16_alt(<8 x i16> %A) {
1150 ; CHECK-SD-LABEL: cmgez8xi16_alt:
1151 ; CHECK-SD: // %bb.0:
1152 ; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
1153 ; CHECK-SD-NEXT: ret
1154 ;
1155 ; CHECK-GI-LABEL: cmgez8xi16_alt:
1156 ; CHECK-GI: // %bb.0:
1157 ; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15
1158 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1159 ; CHECK-GI-NEXT: ret
1160 %sign = ashr <8 x i16> %A, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
1161 %not = xor <8 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
1162 ret <8 x i16> %not
1163 }
1165 define <2 x i32> @cmgez2xi32_alt(<2 x i32> %A) {
1166 ; CHECK-SD-LABEL: cmgez2xi32_alt:
1167 ; CHECK-SD: // %bb.0:
1168 ; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
1169 ; CHECK-SD-NEXT: ret
1170 ;
1171 ; CHECK-GI-LABEL: cmgez2xi32_alt:
1172 ; CHECK-GI: // %bb.0:
1173 ; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31
1174 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1175 ; CHECK-GI-NEXT: ret
1176 %sign = ashr <2 x i32> %A, <i32 31, i32 31>
1177 %not = xor <2 x i32> %sign, <i32 -1, i32 -1>
1178 ret <2 x i32> %not
1179 }
1181 define <4 x i32> @cmgez4xi32_alt(<4 x i32> %A) {
1182 ; CHECK-SD-LABEL: cmgez4xi32_alt:
1183 ; CHECK-SD: // %bb.0:
1184 ; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
1185 ; CHECK-SD-NEXT: ret
1186 ;
1187 ; CHECK-GI-LABEL: cmgez4xi32_alt:
1188 ; CHECK-GI: // %bb.0:
1189 ; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
1190 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1191 ; CHECK-GI-NEXT: ret
1192 %sign = ashr <4 x i32> %A, <i32 31, i32 31, i32 31, i32 31>
1193 %not = xor <4 x i32> %sign, <i32 -1, i32 -1, i32 -1, i32 -1>
1194 ret <4 x i32> %not
1195 }
1197 define <2 x i64> @cmgez2xi64_alt(<2 x i64> %A) {
1198 ; CHECK-SD-LABEL: cmgez2xi64_alt:
1199 ; CHECK-SD: // %bb.0:
1200 ; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
1201 ; CHECK-SD-NEXT: ret
1202 ;
1203 ; CHECK-GI-LABEL: cmgez2xi64_alt:
1204 ; CHECK-GI: // %bb.0:
1205 ; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63
1206 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1207 ; CHECK-GI-NEXT: ret
1208 %sign = ashr <2 x i64> %A, <i64 63, i64 63>
1209 %not = xor <2 x i64> %sign, <i64 -1, i64 -1>
1210 ret <2 x i64> %not
1211 }
1214 define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
1215 ; CHECK-SD-LABEL: cmgtz8xi8:
1216 ; CHECK-SD: // %bb.0:
1217 ; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
1218 ; CHECK-SD-NEXT: ret
1219 ;
1220 ; CHECK-GI-LABEL: cmgtz8xi8:
1221 ; CHECK-GI: // %bb.0:
1222 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1223 ; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
1224 ; CHECK-GI-NEXT: ret
1225 %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer;
1226 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1227 ret <8 x i8> %tmp4
1228 }
1230 define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
1231 ; CHECK-SD-LABEL: cmgtz16xi8:
1232 ; CHECK-SD: // %bb.0:
1233 ; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
1234 ; CHECK-SD-NEXT: ret
1235 ;
1236 ; CHECK-GI-LABEL: cmgtz16xi8:
1237 ; CHECK-GI: // %bb.0:
1238 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1239 ; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
1240 ; CHECK-GI-NEXT: ret
1241 %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer;
1242 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1243 ret <16 x i8> %tmp4
1244 }
1246 define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
1247 ; CHECK-SD-LABEL: cmgtz4xi16:
1248 ; CHECK-SD: // %bb.0:
1249 ; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
1250 ; CHECK-SD-NEXT: ret
1251 ;
1252 ; CHECK-GI-LABEL: cmgtz4xi16:
1253 ; CHECK-GI: // %bb.0:
1254 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1255 ; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
1256 ; CHECK-GI-NEXT: ret
1257 %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer;
1258 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1259 ret <4 x i16> %tmp4
1260 }
1262 define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
1263 ; CHECK-SD-LABEL: cmgtz8xi16:
1264 ; CHECK-SD: // %bb.0:
1265 ; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
1266 ; CHECK-SD-NEXT: ret
1267 ;
1268 ; CHECK-GI-LABEL: cmgtz8xi16:
1269 ; CHECK-GI: // %bb.0:
1270 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1271 ; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
1272 ; CHECK-GI-NEXT: ret
1273 %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer;
1274 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1275 ret <8 x i16> %tmp4
1276 }
1278 define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
1279 ; CHECK-SD-LABEL: cmgtz2xi32:
1280 ; CHECK-SD: // %bb.0:
1281 ; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
1282 ; CHECK-SD-NEXT: ret
1283 ;
1284 ; CHECK-GI-LABEL: cmgtz2xi32:
1285 ; CHECK-GI: // %bb.0:
1286 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1287 ; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
1288 ; CHECK-GI-NEXT: ret
1289 %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer;
1290 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1291 ret <2 x i32> %tmp4
1292 }
1294 define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
1295 ; CHECK-SD-LABEL: cmgtz4xi32:
1296 ; CHECK-SD: // %bb.0:
1297 ; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
1298 ; CHECK-SD-NEXT: ret
1299 ;
1300 ; CHECK-GI-LABEL: cmgtz4xi32:
1301 ; CHECK-GI: // %bb.0:
1302 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1303 ; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
1304 ; CHECK-GI-NEXT: ret
1305 %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer;
1306 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1307 ret <4 x i32> %tmp4
1308 }
1310 define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
1311 ; CHECK-SD-LABEL: cmgtz2xi64:
1312 ; CHECK-SD: // %bb.0:
1313 ; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
1314 ; CHECK-SD-NEXT: ret
1315 ;
1316 ; CHECK-GI-LABEL: cmgtz2xi64:
1317 ; CHECK-GI: // %bb.0:
1318 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1319 ; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
1320 ; CHECK-GI-NEXT: ret
1321 %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer;
1322 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1323 ret <2 x i64> %tmp4
1324 }
1326 define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
1327 ; CHECK-SD-LABEL: cmlez8xi8:
1328 ; CHECK-SD: // %bb.0:
1329 ; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
1330 ; CHECK-SD-NEXT: ret
1331 ;
1332 ; CHECK-GI-LABEL: cmlez8xi8:
1333 ; CHECK-GI: // %bb.0:
1334 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1335 ; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
1336 ; CHECK-GI-NEXT: ret
1337 %tmp3 = icmp sle <8 x i8> %A, zeroinitializer;
1338 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1339 ret <8 x i8> %tmp4
1340 }
1342 define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
1343 ; CHECK-SD-LABEL: cmlez16xi8:
1344 ; CHECK-SD: // %bb.0:
1345 ; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
1346 ; CHECK-SD-NEXT: ret
1347 ;
1348 ; CHECK-GI-LABEL: cmlez16xi8:
1349 ; CHECK-GI: // %bb.0:
1350 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1351 ; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
1352 ; CHECK-GI-NEXT: ret
1353 %tmp3 = icmp sle <16 x i8> %A, zeroinitializer;
1354 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1355 ret <16 x i8> %tmp4
1356 }
1358 define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
1359 ; CHECK-SD-LABEL: cmlez4xi16:
1360 ; CHECK-SD: // %bb.0:
1361 ; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
1362 ; CHECK-SD-NEXT: ret
1363 ;
1364 ; CHECK-GI-LABEL: cmlez4xi16:
1365 ; CHECK-GI: // %bb.0:
1366 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1367 ; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
1368 ; CHECK-GI-NEXT: ret
1369 %tmp3 = icmp sle <4 x i16> %A, zeroinitializer;
1370 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1371 ret <4 x i16> %tmp4
1372 }
1374 define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
1375 ; CHECK-SD-LABEL: cmlez8xi16:
1376 ; CHECK-SD: // %bb.0:
1377 ; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
1378 ; CHECK-SD-NEXT: ret
1379 ;
1380 ; CHECK-GI-LABEL: cmlez8xi16:
1381 ; CHECK-GI: // %bb.0:
1382 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1383 ; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
1384 ; CHECK-GI-NEXT: ret
1385 %tmp3 = icmp sle <8 x i16> %A, zeroinitializer;
1386 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1387 ret <8 x i16> %tmp4
1388 }
1390 define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
1391 ; CHECK-SD-LABEL: cmlez2xi32:
1392 ; CHECK-SD: // %bb.0:
1393 ; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
1394 ; CHECK-SD-NEXT: ret
1395 ;
1396 ; CHECK-GI-LABEL: cmlez2xi32:
1397 ; CHECK-GI: // %bb.0:
1398 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1399 ; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
1400 ; CHECK-GI-NEXT: ret
1401 %tmp3 = icmp sle <2 x i32> %A, zeroinitializer;
1402 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1403 ret <2 x i32> %tmp4
1404 }
1406 define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
1407 ; CHECK-SD-LABEL: cmlez4xi32:
1408 ; CHECK-SD: // %bb.0:
1409 ; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
1410 ; CHECK-SD-NEXT: ret
1411 ;
1412 ; CHECK-GI-LABEL: cmlez4xi32:
1413 ; CHECK-GI: // %bb.0:
1414 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1415 ; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
1416 ; CHECK-GI-NEXT: ret
1417 %tmp3 = icmp sle <4 x i32> %A, zeroinitializer;
1418 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1419 ret <4 x i32> %tmp4
1420 }
1422 define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
1423 ; CHECK-SD-LABEL: cmlez2xi64:
1424 ; CHECK-SD: // %bb.0:
1425 ; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
1426 ; CHECK-SD-NEXT: ret
1427 ;
1428 ; CHECK-GI-LABEL: cmlez2xi64:
1429 ; CHECK-GI: // %bb.0:
1430 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1431 ; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
1432 ; CHECK-GI-NEXT: ret
1433 %tmp3 = icmp sle <2 x i64> %A, zeroinitializer;
1434 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1435 ret <2 x i64> %tmp4
1436 }
1438 define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
1439 ; CHECK-SD-LABEL: cmltz8xi8:
1440 ; CHECK-SD: // %bb.0:
1441 ; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
1442 ; CHECK-SD-NEXT: ret
1443 ;
1444 ; CHECK-GI-LABEL: cmltz8xi8:
1445 ; CHECK-GI: // %bb.0:
1446 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1447 ; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
1448 ; CHECK-GI-NEXT: ret
1449 %tmp3 = icmp slt <8 x i8> %A, zeroinitializer;
1450 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1451 ret <8 x i8> %tmp4
1452 }
1454 define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
1455 ; CHECK-SD-LABEL: cmltz16xi8:
1456 ; CHECK-SD: // %bb.0:
1457 ; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
1458 ; CHECK-SD-NEXT: ret
1459 ;
1460 ; CHECK-GI-LABEL: cmltz16xi8:
1461 ; CHECK-GI: // %bb.0:
1462 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1463 ; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
1464 ; CHECK-GI-NEXT: ret
1465 %tmp3 = icmp slt <16 x i8> %A, zeroinitializer;
1466 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1467 ret <16 x i8> %tmp4
1468 }
1470 define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
1471 ; CHECK-SD-LABEL: cmltz4xi16:
1472 ; CHECK-SD: // %bb.0:
1473 ; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
1474 ; CHECK-SD-NEXT: ret
1475 ;
1476 ; CHECK-GI-LABEL: cmltz4xi16:
1477 ; CHECK-GI: // %bb.0:
1478 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1479 ; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
1480 ; CHECK-GI-NEXT: ret
1481 %tmp3 = icmp slt <4 x i16> %A, zeroinitializer;
1482 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1483 ret <4 x i16> %tmp4
1484 }
1486 define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
1487 ; CHECK-SD-LABEL: cmltz8xi16:
1488 ; CHECK-SD: // %bb.0:
1489 ; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
1490 ; CHECK-SD-NEXT: ret
1491 ;
1492 ; CHECK-GI-LABEL: cmltz8xi16:
1493 ; CHECK-GI: // %bb.0:
1494 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1495 ; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
1496 ; CHECK-GI-NEXT: ret
1497 %tmp3 = icmp slt <8 x i16> %A, zeroinitializer;
1498 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1499 ret <8 x i16> %tmp4
1500 }
1502 define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
1503 ; CHECK-SD-LABEL: cmltz2xi32:
1504 ; CHECK-SD: // %bb.0:
1505 ; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
1506 ; CHECK-SD-NEXT: ret
1507 ;
1508 ; CHECK-GI-LABEL: cmltz2xi32:
1509 ; CHECK-GI: // %bb.0:
1510 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1511 ; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
1512 ; CHECK-GI-NEXT: ret
1513 %tmp3 = icmp slt <2 x i32> %A, zeroinitializer;
1514 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1515 ret <2 x i32> %tmp4
1516 }
1518 define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
1519 ; CHECK-SD-LABEL: cmltz4xi32:
1520 ; CHECK-SD: // %bb.0:
1521 ; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
1522 ; CHECK-SD-NEXT: ret
1523 ;
1524 ; CHECK-GI-LABEL: cmltz4xi32:
1525 ; CHECK-GI: // %bb.0:
1526 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1527 ; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
1528 ; CHECK-GI-NEXT: ret
1529 %tmp3 = icmp slt <4 x i32> %A, zeroinitializer;
1530 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1531 ret <4 x i32> %tmp4
1532 }
1534 define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
1535 ; CHECK-SD-LABEL: cmltz2xi64:
1536 ; CHECK-SD: // %bb.0:
1537 ; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
1538 ; CHECK-SD-NEXT: ret
1539 ;
1540 ; CHECK-GI-LABEL: cmltz2xi64:
1541 ; CHECK-GI: // %bb.0:
1542 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1543 ; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
1544 ; CHECK-GI-NEXT: ret
1545 %tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
1546 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1547 ret <2 x i64> %tmp4
1548 }
1550 define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
1551 ; CHECK-SD-LABEL: cmneqz8xi8:
1552 ; CHECK-SD: // %bb.0:
1553 ; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v0.8b
1554 ; CHECK-SD-NEXT: ret
1555 ;
1556 ; CHECK-GI-LABEL: cmneqz8xi8:
1557 ; CHECK-GI: // %bb.0:
1558 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1559 ; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
1560 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1561 ; CHECK-GI-NEXT: ret
1562 %tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
1563 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1564 ret <8 x i8> %tmp4
1565 }
1567 define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
1568 ; CHECK-SD-LABEL: cmneqz16xi8:
1569 ; CHECK-SD: // %bb.0:
1570 ; CHECK-SD-NEXT: cmtst v0.16b, v0.16b, v0.16b
1571 ; CHECK-SD-NEXT: ret
1572 ;
1573 ; CHECK-GI-LABEL: cmneqz16xi8:
1574 ; CHECK-GI: // %bb.0:
1575 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1576 ; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
1577 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1578 ; CHECK-GI-NEXT: ret
1579 %tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
1580 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1581 ret <16 x i8> %tmp4
1582 }
1584 define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
1585 ; CHECK-SD-LABEL: cmneqz4xi16:
1586 ; CHECK-SD: // %bb.0:
1587 ; CHECK-SD-NEXT: cmtst v0.4h, v0.4h, v0.4h
1588 ; CHECK-SD-NEXT: ret
1589 ;
1590 ; CHECK-GI-LABEL: cmneqz4xi16:
1591 ; CHECK-GI: // %bb.0:
1592 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1593 ; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
1594 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1595 ; CHECK-GI-NEXT: ret
1596 %tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
1597 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1598 ret <4 x i16> %tmp4
1599 }
1601 define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
1602 ; CHECK-SD-LABEL: cmneqz8xi16:
1603 ; CHECK-SD: // %bb.0:
1604 ; CHECK-SD-NEXT: cmtst v0.8h, v0.8h, v0.8h
1605 ; CHECK-SD-NEXT: ret
1606 ;
1607 ; CHECK-GI-LABEL: cmneqz8xi16:
1608 ; CHECK-GI: // %bb.0:
1609 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1610 ; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
1611 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1612 ; CHECK-GI-NEXT: ret
1613 %tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
1614 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1615 ret <8 x i16> %tmp4
1616 }
1618 define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
1619 ; CHECK-SD-LABEL: cmneqz2xi32:
1620 ; CHECK-SD: // %bb.0:
1621 ; CHECK-SD-NEXT: cmtst v0.2s, v0.2s, v0.2s
1622 ; CHECK-SD-NEXT: ret
1623 ;
1624 ; CHECK-GI-LABEL: cmneqz2xi32:
1625 ; CHECK-GI: // %bb.0:
1626 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1627 ; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
1628 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1629 ; CHECK-GI-NEXT: ret
1630 %tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
1631 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1632 ret <2 x i32> %tmp4
1633 }
1635 define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
1636 ; CHECK-SD-LABEL: cmneqz4xi32:
1637 ; CHECK-SD: // %bb.0:
1638 ; CHECK-SD-NEXT: cmtst v0.4s, v0.4s, v0.4s
1639 ; CHECK-SD-NEXT: ret
1640 ;
1641 ; CHECK-GI-LABEL: cmneqz4xi32:
1642 ; CHECK-GI: // %bb.0:
1643 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1644 ; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
1645 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1646 ; CHECK-GI-NEXT: ret
1647 %tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
1648 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1649 ret <4 x i32> %tmp4
1650 }
1652 define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
1653 ; CHECK-SD-LABEL: cmneqz2xi64:
1654 ; CHECK-SD: // %bb.0:
1655 ; CHECK-SD-NEXT: cmtst v0.2d, v0.2d, v0.2d
1656 ; CHECK-SD-NEXT: ret
1657 ;
1658 ; CHECK-GI-LABEL: cmneqz2xi64:
1659 ; CHECK-GI: // %bb.0:
1660 ; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
1661 ; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
1662 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
1663 ; CHECK-GI-NEXT: ret
1664 %tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
1665 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1666 ret <2 x i64> %tmp4
1667 }
1669 define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
1670 ; CHECK-SD-LABEL: cmhsz8xi8:
1671 ; CHECK-SD: // %bb.0:
1672 ; CHECK-SD-NEXT: movi v1.8b, #2
1673 ; CHECK-SD-NEXT: cmhs v0.8b, v0.8b, v1.8b
1674 ; CHECK-SD-NEXT: ret
1675 ;
1676 ; CHECK-GI-LABEL: cmhsz8xi8:
1677 ; CHECK-GI: // %bb.0:
1678 ; CHECK-GI-NEXT: adrp x8, .LCPI126_0
1679 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI126_0]
1680 ; CHECK-GI-NEXT: cmhs v0.8b, v0.8b, v1.8b
1681 ; CHECK-GI-NEXT: ret
1682 %tmp3 = icmp uge <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
1683 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1684 ret <8 x i8> %tmp4
1685 }
1687 define <16 x i8> @cmhsz16xi8(<16 x i8> %A) {
1688 ; CHECK-SD-LABEL: cmhsz16xi8:
1689 ; CHECK-SD: // %bb.0:
1690 ; CHECK-SD-NEXT: movi v1.16b, #2
1691 ; CHECK-SD-NEXT: cmhs v0.16b, v0.16b, v1.16b
1692 ; CHECK-SD-NEXT: ret
1693 ;
1694 ; CHECK-GI-LABEL: cmhsz16xi8:
1695 ; CHECK-GI: // %bb.0:
1696 ; CHECK-GI-NEXT: adrp x8, .LCPI127_0
1697 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI127_0]
1698 ; CHECK-GI-NEXT: cmhs v0.16b, v0.16b, v1.16b
1699 ; CHECK-GI-NEXT: ret
1700 %tmp3 = icmp uge <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
1701 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1702 ret <16 x i8> %tmp4
1703 }
1705 define <4 x i16> @cmhsz4xi16(<4 x i16> %A) {
1706 ; CHECK-SD-LABEL: cmhsz4xi16:
1707 ; CHECK-SD: // %bb.0:
1708 ; CHECK-SD-NEXT: movi v1.4h, #2
1709 ; CHECK-SD-NEXT: cmhs v0.4h, v0.4h, v1.4h
1710 ; CHECK-SD-NEXT: ret
1711 ;
1712 ; CHECK-GI-LABEL: cmhsz4xi16:
1713 ; CHECK-GI: // %bb.0:
1714 ; CHECK-GI-NEXT: adrp x8, .LCPI128_0
1715 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI128_0]
1716 ; CHECK-GI-NEXT: cmhs v0.4h, v0.4h, v1.4h
1717 ; CHECK-GI-NEXT: ret
1718 %tmp3 = icmp uge <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2>
1719 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1720 ret <4 x i16> %tmp4
1721 }
1723 define <8 x i16> @cmhsz8xi16(<8 x i16> %A) {
1724 ; CHECK-SD-LABEL: cmhsz8xi16:
1725 ; CHECK-SD: // %bb.0:
1726 ; CHECK-SD-NEXT: movi v1.8h, #2
1727 ; CHECK-SD-NEXT: cmhs v0.8h, v0.8h, v1.8h
1728 ; CHECK-SD-NEXT: ret
1729 ;
1730 ; CHECK-GI-LABEL: cmhsz8xi16:
1731 ; CHECK-GI: // %bb.0:
1732 ; CHECK-GI-NEXT: adrp x8, .LCPI129_0
1733 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI129_0]
1734 ; CHECK-GI-NEXT: cmhs v0.8h, v0.8h, v1.8h
1735 ; CHECK-GI-NEXT: ret
1736 %tmp3 = icmp uge <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
1737 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1738 ret <8 x i16> %tmp4
1739 }
1741 define <2 x i32> @cmhsz2xi32(<2 x i32> %A) {
1742 ; CHECK-SD-LABEL: cmhsz2xi32:
1743 ; CHECK-SD: // %bb.0:
1744 ; CHECK-SD-NEXT: movi v1.2s, #2
1745 ; CHECK-SD-NEXT: cmhs v0.2s, v0.2s, v1.2s
1746 ; CHECK-SD-NEXT: ret
1747 ;
1748 ; CHECK-GI-LABEL: cmhsz2xi32:
1749 ; CHECK-GI: // %bb.0:
1750 ; CHECK-GI-NEXT: adrp x8, .LCPI130_0
1751 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI130_0]
1752 ; CHECK-GI-NEXT: cmhs v0.2s, v0.2s, v1.2s
1753 ; CHECK-GI-NEXT: ret
1754 %tmp3 = icmp uge <2 x i32> %A, <i32 2, i32 2>
1755 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1756 ret <2 x i32> %tmp4
1757 }
1759 define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
1760 ; CHECK-SD-LABEL: cmhsz4xi32:
1761 ; CHECK-SD: // %bb.0:
1762 ; CHECK-SD-NEXT: movi v1.4s, #2
1763 ; CHECK-SD-NEXT: cmhs v0.4s, v0.4s, v1.4s
1764 ; CHECK-SD-NEXT: ret
1765 ;
1766 ; CHECK-GI-LABEL: cmhsz4xi32:
1767 ; CHECK-GI: // %bb.0:
1768 ; CHECK-GI-NEXT: adrp x8, .LCPI131_0
1769 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI131_0]
1770 ; CHECK-GI-NEXT: cmhs v0.4s, v0.4s, v1.4s
1771 ; CHECK-GI-NEXT: ret
1772 %tmp3 = icmp uge <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2>
1773 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1774 ret <4 x i32> %tmp4
1775 }
1777 define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
1778 ; CHECK-SD-LABEL: cmhsz2xi64:
1779 ; CHECK-SD: // %bb.0:
1780 ; CHECK-SD-NEXT: mov w8, #2 // =0x2
1781 ; CHECK-SD-NEXT: dup v1.2d, x8
1782 ; CHECK-SD-NEXT: cmhs v0.2d, v0.2d, v1.2d
1783 ; CHECK-SD-NEXT: ret
1784 ;
1785 ; CHECK-GI-LABEL: cmhsz2xi64:
1786 ; CHECK-GI: // %bb.0:
1787 ; CHECK-GI-NEXT: adrp x8, .LCPI132_0
1788 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI132_0]
1789 ; CHECK-GI-NEXT: cmhs v0.2d, v0.2d, v1.2d
1790 ; CHECK-GI-NEXT: ret
1791 ; GISEL-LABEL: cmhsz2xi64:
1792 ; GISEL: // %bb.0:
1793 ; GISEL-NEXT: adrp x8, .LCPI132_0
1794 ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI132_0]
1795 ; GISEL-NEXT: cmhs v0.2d, v0.2d, v1.2d
1796 ; GISEL-NEXT: ret
1797 %tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2>
1798 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1799 ret <2 x i64> %tmp4
1800 }
1803 define <8 x i8> @cmhiz8xi8(<8 x i8> %A) {
1804 ; CHECK-SD-LABEL: cmhiz8xi8:
1805 ; CHECK-SD: // %bb.0:
1806 ; CHECK-SD-NEXT: movi v1.8b, #1
1807 ; CHECK-SD-NEXT: cmhi v0.8b, v0.8b, v1.8b
1808 ; CHECK-SD-NEXT: ret
1809 ;
1810 ; CHECK-GI-LABEL: cmhiz8xi8:
1811 ; CHECK-GI: // %bb.0:
1812 ; CHECK-GI-NEXT: adrp x8, .LCPI133_0
1813 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI133_0]
1814 ; CHECK-GI-NEXT: cmhi v0.8b, v0.8b, v1.8b
1815 ; CHECK-GI-NEXT: ret
1816 %tmp3 = icmp ugt <8 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1817 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1818 ret <8 x i8> %tmp4
1819 }
1821 define <16 x i8> @cmhiz16xi8(<16 x i8> %A) {
1822 ; CHECK-SD-LABEL: cmhiz16xi8:
1823 ; CHECK-SD: // %bb.0:
1824 ; CHECK-SD-NEXT: movi v1.16b, #1
1825 ; CHECK-SD-NEXT: cmhi v0.16b, v0.16b, v1.16b
1826 ; CHECK-SD-NEXT: ret
1827 ;
1828 ; CHECK-GI-LABEL: cmhiz16xi8:
1829 ; CHECK-GI: // %bb.0:
1830 ; CHECK-GI-NEXT: adrp x8, .LCPI134_0
1831 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI134_0]
1832 ; CHECK-GI-NEXT: cmhi v0.16b, v0.16b, v1.16b
1833 ; CHECK-GI-NEXT: ret
1834 %tmp3 = icmp ugt <16 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
1835 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1836 ret <16 x i8> %tmp4
1837 }
1839 define <4 x i16> @cmhiz4xi16(<4 x i16> %A) {
1840 ; CHECK-SD-LABEL: cmhiz4xi16:
1841 ; CHECK-SD: // %bb.0:
1842 ; CHECK-SD-NEXT: movi v1.4h, #1
1843 ; CHECK-SD-NEXT: cmhi v0.4h, v0.4h, v1.4h
1844 ; CHECK-SD-NEXT: ret
1845 ;
1846 ; CHECK-GI-LABEL: cmhiz4xi16:
1847 ; CHECK-GI: // %bb.0:
1848 ; CHECK-GI-NEXT: adrp x8, .LCPI135_0
1849 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI135_0]
1850 ; CHECK-GI-NEXT: cmhi v0.4h, v0.4h, v1.4h
1851 ; CHECK-GI-NEXT: ret
1852 %tmp3 = icmp ugt <4 x i16> %A, <i16 1, i16 1, i16 1, i16 1>
1853 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1854 ret <4 x i16> %tmp4
1855 }
1857 define <8 x i16> @cmhiz8xi16(<8 x i16> %A) {
1858 ; CHECK-SD-LABEL: cmhiz8xi16:
1859 ; CHECK-SD: // %bb.0:
1860 ; CHECK-SD-NEXT: movi v1.8h, #1
1861 ; CHECK-SD-NEXT: cmhi v0.8h, v0.8h, v1.8h
1862 ; CHECK-SD-NEXT: ret
1863 ;
1864 ; CHECK-GI-LABEL: cmhiz8xi16:
1865 ; CHECK-GI: // %bb.0:
1866 ; CHECK-GI-NEXT: adrp x8, .LCPI136_0
1867 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI136_0]
1868 ; CHECK-GI-NEXT: cmhi v0.8h, v0.8h, v1.8h
1869 ; CHECK-GI-NEXT: ret
1870 %tmp3 = icmp ugt <8 x i16> %A, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1871 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1872 ret <8 x i16> %tmp4
1873 }
1875 define <2 x i32> @cmhiz2xi32(<2 x i32> %A) {
1876 ; CHECK-SD-LABEL: cmhiz2xi32:
1877 ; CHECK-SD: // %bb.0:
1878 ; CHECK-SD-NEXT: movi v1.2s, #1
1879 ; CHECK-SD-NEXT: cmhi v0.2s, v0.2s, v1.2s
1880 ; CHECK-SD-NEXT: ret
1881 ;
1882 ; CHECK-GI-LABEL: cmhiz2xi32:
1883 ; CHECK-GI: // %bb.0:
1884 ; CHECK-GI-NEXT: adrp x8, .LCPI137_0
1885 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI137_0]
1886 ; CHECK-GI-NEXT: cmhi v0.2s, v0.2s, v1.2s
1887 ; CHECK-GI-NEXT: ret
1888 %tmp3 = icmp ugt <2 x i32> %A, <i32 1, i32 1>
1889 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1890 ret <2 x i32> %tmp4
1891 }
1893 define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
1894 ; CHECK-SD-LABEL: cmhiz4xi32:
1895 ; CHECK-SD: // %bb.0:
1896 ; CHECK-SD-NEXT: movi v1.4s, #1
1897 ; CHECK-SD-NEXT: cmhi v0.4s, v0.4s, v1.4s
1898 ; CHECK-SD-NEXT: ret
1899 ;
1900 ; CHECK-GI-LABEL: cmhiz4xi32:
1901 ; CHECK-GI: // %bb.0:
1902 ; CHECK-GI-NEXT: adrp x8, .LCPI138_0
1903 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI138_0]
1904 ; CHECK-GI-NEXT: cmhi v0.4s, v0.4s, v1.4s
1905 ; CHECK-GI-NEXT: ret
1906 %tmp3 = icmp ugt <4 x i32> %A, <i32 1, i32 1, i32 1, i32 1>
1907 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1908 ret <4 x i32> %tmp4
1909 }
1911 define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
1912 ; CHECK-SD-LABEL: cmhiz2xi64:
1913 ; CHECK-SD: // %bb.0:
1914 ; CHECK-SD-NEXT: mov w8, #1 // =0x1
1915 ; CHECK-SD-NEXT: dup v1.2d, x8
1916 ; CHECK-SD-NEXT: cmhi v0.2d, v0.2d, v1.2d
1917 ; CHECK-SD-NEXT: ret
1918 ;
1919 ; CHECK-GI-LABEL: cmhiz2xi64:
1920 ; CHECK-GI: // %bb.0:
1921 ; CHECK-GI-NEXT: adrp x8, .LCPI139_0
1922 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI139_0]
1923 ; CHECK-GI-NEXT: cmhi v0.2d, v0.2d, v1.2d
1924 ; CHECK-GI-NEXT: ret
1925 ; GISEL-LABEL: cmhiz2xi64:
1926 ; GISEL: // %bb.0:
1927 ; GISEL-NEXT: adrp x8, .LCPI139_0
1928 ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI139_0]
1929 ; GISEL-NEXT: cmhi v0.2d, v0.2d, v1.2d
1930 ; GISEL-NEXT: ret
1931 %tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1>
1932 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1933 ret <2 x i64> %tmp4
1934 }
1936 ; LS implemented as HS, so check reversed operands.
1937 define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
1938 ; CHECK-LABEL: cmlsz8xi8:
1939 ; CHECK: // %bb.0:
1940 ; CHECK-NEXT: movi v1.2d, #0000000000000000
1941 ; CHECK-NEXT: cmhs v0.8b, v1.8b, v0.8b
1942 ; CHECK-NEXT: ret
1943 %tmp3 = icmp ule <8 x i8> %A, zeroinitializer;
1944 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1945 ret <8 x i8> %tmp4
1946 }
1948 ; LS implemented as HS, so check reversed operands.
1949 define <16 x i8> @cmlsz16xi8(<16 x i8> %A) {
1950 ; CHECK-LABEL: cmlsz16xi8:
1951 ; CHECK: // %bb.0:
1952 ; CHECK-NEXT: movi v1.2d, #0000000000000000
1953 ; CHECK-NEXT: cmhs v0.16b, v1.16b, v0.16b
1954 ; CHECK-NEXT: ret
1955 %tmp3 = icmp ule <16 x i8> %A, zeroinitializer;
1956 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1957 ret <16 x i8> %tmp4
1958 }
1960 ; LS implemented as HS, so check reversed operands.
1961 define <4 x i16> @cmlsz4xi16(<4 x i16> %A) {
1962 ; CHECK-LABEL: cmlsz4xi16:
1963 ; CHECK: // %bb.0:
1964 ; CHECK-NEXT: movi v1.2d, #0000000000000000
1965 ; CHECK-NEXT: cmhs v0.4h, v1.4h, v0.4h
1966 ; CHECK-NEXT: ret
1967 %tmp3 = icmp ule <4 x i16> %A, zeroinitializer;
1968 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1969 ret <4 x i16> %tmp4
1970 }
1972 ; LS implemented as HS, so check reversed operands.
1973 define <8 x i16> @cmlsz8xi16(<8 x i16> %A) {
1974 ; CHECK-LABEL: cmlsz8xi16:
1975 ; CHECK: // %bb.0:
1976 ; CHECK-NEXT: movi v1.2d, #0000000000000000
1977 ; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h
1978 ; CHECK-NEXT: ret
1979 %tmp3 = icmp ule <8 x i16> %A, zeroinitializer;
1980 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1981 ret <8 x i16> %tmp4
1982 }
1984 ; LS implemented as HS, so check reversed operands.
1985 define <2 x i32> @cmlsz2xi32(<2 x i32> %A) {
1986 ; CHECK-LABEL: cmlsz2xi32:
1987 ; CHECK: // %bb.0:
1988 ; CHECK-NEXT: movi v1.2d, #0000000000000000
1989 ; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s
1990 ; CHECK-NEXT: ret
1991 %tmp3 = icmp ule <2 x i32> %A, zeroinitializer;
1992 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1993 ret <2 x i32> %tmp4
1994 }
1996 ; LS implemented as HS, so check reversed operands.
1997 define <4 x i32> @cmlsz4xi32(<4 x i32> %A) {
1998 ; CHECK-LABEL: cmlsz4xi32:
1999 ; CHECK: // %bb.0:
2000 ; CHECK-NEXT: movi v1.2d, #0000000000000000
2001 ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
2002 ; CHECK-NEXT: ret
2003 %tmp3 = icmp ule <4 x i32> %A, zeroinitializer;
2004 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2005 ret <4 x i32> %tmp4
2006 }
2008 ; LS implemented as HS, so check reversed operands.
2009 define <2 x i64> @cmlsz2xi64(<2 x i64> %A) {
2010 ; CHECK-LABEL: cmlsz2xi64:
2011 ; CHECK: // %bb.0:
2012 ; CHECK-NEXT: movi v1.2d, #0000000000000000
2013 ; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d
2014 ; CHECK-NEXT: ret
2015 %tmp3 = icmp ule <2 x i64> %A, zeroinitializer;
2016 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2017 ret <2 x i64> %tmp4
2018 }
2020 ; LO implemented as HI, so check reversed operands.
2021 define <8 x i8> @cmloz8xi8(<8 x i8> %A) {
2022 ; CHECK-SD-LABEL: cmloz8xi8:
2023 ; CHECK-SD: // %bb.0:
2024 ; CHECK-SD-NEXT: movi v1.8b, #2
2025 ; CHECK-SD-NEXT: cmhi v0.8b, v1.8b, v0.8b
2026 ; CHECK-SD-NEXT: ret
2027 ;
2028 ; CHECK-GI-LABEL: cmloz8xi8:
2029 ; CHECK-GI: // %bb.0:
2030 ; CHECK-GI-NEXT: adrp x8, .LCPI147_0
2031 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI147_0]
2032 ; CHECK-GI-NEXT: cmhi v0.8b, v1.8b, v0.8b
2033 ; CHECK-GI-NEXT: ret
2034 %tmp3 = icmp ult <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
2035 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
2036 ret <8 x i8> %tmp4
2037 }
2039 ; LO implemented as HI, so check reversed operands.
2040 define <16 x i8> @cmloz16xi8(<16 x i8> %A) {
2041 ; CHECK-SD-LABEL: cmloz16xi8:
2042 ; CHECK-SD: // %bb.0:
2043 ; CHECK-SD-NEXT: movi v1.16b, #2
2044 ; CHECK-SD-NEXT: cmhi v0.16b, v1.16b, v0.16b
2045 ; CHECK-SD-NEXT: ret
2046 ;
2047 ; CHECK-GI-LABEL: cmloz16xi8:
2048 ; CHECK-GI: // %bb.0:
2049 ; CHECK-GI-NEXT: adrp x8, .LCPI148_0
2050 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI148_0]
2051 ; CHECK-GI-NEXT: cmhi v0.16b, v1.16b, v0.16b
2052 ; CHECK-GI-NEXT: ret
2053 %tmp3 = icmp ult <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
2054 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
2055 ret <16 x i8> %tmp4
2056 }
2058 ; LO implemented as HI, so check reversed operands.
2059 define <4 x i16> @cmloz4xi16(<4 x i16> %A) {
2060 ; CHECK-SD-LABEL: cmloz4xi16:
2061 ; CHECK-SD: // %bb.0:
2062 ; CHECK-SD-NEXT: movi v1.4h, #2
2063 ; CHECK-SD-NEXT: cmhi v0.4h, v1.4h, v0.4h
2064 ; CHECK-SD-NEXT: ret
2065 ;
2066 ; CHECK-GI-LABEL: cmloz4xi16:
2067 ; CHECK-GI: // %bb.0:
2068 ; CHECK-GI-NEXT: adrp x8, .LCPI149_0
2069 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI149_0]
2070 ; CHECK-GI-NEXT: cmhi v0.4h, v1.4h, v0.4h
2071 ; CHECK-GI-NEXT: ret
2072 %tmp3 = icmp ult <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2>
2073 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
2074 ret <4 x i16> %tmp4
2075 }
2077 ; LO implemented as HI, so check reversed operands.
2078 define <8 x i16> @cmloz8xi16(<8 x i16> %A) {
2079 ; CHECK-SD-LABEL: cmloz8xi16:
2080 ; CHECK-SD: // %bb.0:
2081 ; CHECK-SD-NEXT: movi v1.8h, #2
2082 ; CHECK-SD-NEXT: cmhi v0.8h, v1.8h, v0.8h
2083 ; CHECK-SD-NEXT: ret
2084 ;
2085 ; CHECK-GI-LABEL: cmloz8xi16:
2086 ; CHECK-GI: // %bb.0:
2087 ; CHECK-GI-NEXT: adrp x8, .LCPI150_0
2088 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI150_0]
2089 ; CHECK-GI-NEXT: cmhi v0.8h, v1.8h, v0.8h
2090 ; CHECK-GI-NEXT: ret
2091 %tmp3 = icmp ult <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
2092 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
2093 ret <8 x i16> %tmp4
2094 }
2096 ; LO implemented as HI, so check reversed operands.
2097 define <2 x i32> @cmloz2xi32(<2 x i32> %A) {
2098 ; CHECK-SD-LABEL: cmloz2xi32:
2099 ; CHECK-SD: // %bb.0:
2100 ; CHECK-SD-NEXT: movi v1.2s, #2
2101 ; CHECK-SD-NEXT: cmhi v0.2s, v1.2s, v0.2s
2102 ; CHECK-SD-NEXT: ret
2103 ;
2104 ; CHECK-GI-LABEL: cmloz2xi32:
2105 ; CHECK-GI: // %bb.0:
2106 ; CHECK-GI-NEXT: adrp x8, .LCPI151_0
2107 ; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI151_0]
2108 ; CHECK-GI-NEXT: cmhi v0.2s, v1.2s, v0.2s
2109 ; CHECK-GI-NEXT: ret
2110 %tmp3 = icmp ult <2 x i32> %A, <i32 2, i32 2>
2111 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2112 ret <2 x i32> %tmp4
2113 }
2115 ; LO implemented as HI, so check reversed operands.
2116 define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
2117 ; CHECK-SD-LABEL: cmloz4xi32:
2118 ; CHECK-SD: // %bb.0:
2119 ; CHECK-SD-NEXT: movi v1.4s, #2
2120 ; CHECK-SD-NEXT: cmhi v0.4s, v1.4s, v0.4s
2121 ; CHECK-SD-NEXT: ret
2122 ;
2123 ; CHECK-GI-LABEL: cmloz4xi32:
2124 ; CHECK-GI: // %bb.0:
2125 ; CHECK-GI-NEXT: adrp x8, .LCPI152_0
2126 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI152_0]
2127 ; CHECK-GI-NEXT: cmhi v0.4s, v1.4s, v0.4s
2128 ; CHECK-GI-NEXT: ret
2129 %tmp3 = icmp ult <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2>
2130 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2131 ret <4 x i32> %tmp4
2132 }
2134 ; LO implemented as HI, so check reversed operands.
2135 define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
2136 ; CHECK-SD-LABEL: cmloz2xi64:
2137 ; CHECK-SD: // %bb.0:
2138 ; CHECK-SD-NEXT: mov w8, #2 // =0x2
2139 ; CHECK-SD-NEXT: dup v1.2d, x8
2140 ; CHECK-SD-NEXT: cmhi v0.2d, v1.2d, v0.2d
2141 ; CHECK-SD-NEXT: ret
2142 ;
2143 ; CHECK-GI-LABEL: cmloz2xi64:
2144 ; CHECK-GI: // %bb.0:
2145 ; CHECK-GI-NEXT: adrp x8, .LCPI153_0
2146 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI153_0]
2147 ; CHECK-GI-NEXT: cmhi v0.2d, v1.2d, v0.2d
2148 ; CHECK-GI-NEXT: ret
2149 ; GISEL-LABEL: cmloz2xi64:
2150 ; GISEL: // %bb.0:
2151 ; GISEL-NEXT: adrp x8, .LCPI153_0
2152 ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI153_0]
2153 ; GISEL-NEXT: cmhi v0.2d, v1.2d, v0.2d
2154 ; GISEL-NEXT: ret
2155 %tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2>
2156 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2157 ret <2 x i64> %tmp4
2158 }
2160 define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) {
2161 ; CHECK-LABEL: fcmoeq2xfloat:
2162 ; CHECK: // %bb.0:
2163 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
2164 ; CHECK-NEXT: ret
2165 %tmp3 = fcmp oeq <2 x float> %A, %B
2166 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2167 ret <2 x i32> %tmp4
2168 }
2170 define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) {
2171 ; CHECK-LABEL: fcmoeq4xfloat:
2172 ; CHECK: // %bb.0:
2173 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
2174 ; CHECK-NEXT: ret
2175 %tmp3 = fcmp oeq <4 x float> %A, %B
2176 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2177 ret <4 x i32> %tmp4
2178 }
2179 define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) {
2180 ; CHECK-LABEL: fcmoeq2xdouble:
2181 ; CHECK: // %bb.0:
2182 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d
2183 ; CHECK-NEXT: ret
2184 %tmp3 = fcmp oeq <2 x double> %A, %B
2185 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2186 ret <2 x i64> %tmp4
2187 }
2189 define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) {
2190 ; CHECK-LABEL: fcmoge2xfloat:
2191 ; CHECK: // %bb.0:
2192 ; CHECK-NEXT: fcmge v0.2s, v0.2s, v1.2s
2193 ; CHECK-NEXT: ret
2194 %tmp3 = fcmp oge <2 x float> %A, %B
2195 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2196 ret <2 x i32> %tmp4
2197 }
2199 define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) {
2200 ; CHECK-LABEL: fcmoge4xfloat:
2201 ; CHECK: // %bb.0:
2202 ; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s
2203 ; CHECK-NEXT: ret
2204 %tmp3 = fcmp oge <4 x float> %A, %B
2205 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2206 ret <4 x i32> %tmp4
2207 }
2208 define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) {
2209 ; CHECK-LABEL: fcmoge2xdouble:
2210 ; CHECK: // %bb.0:
2211 ; CHECK-NEXT: fcmge v0.2d, v0.2d, v1.2d
2212 ; CHECK-NEXT: ret
2213 %tmp3 = fcmp oge <2 x double> %A, %B
2214 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2215 ret <2 x i64> %tmp4
2216 }
2218 define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) {
2219 ; CHECK-LABEL: fcmogt2xfloat:
2220 ; CHECK: // %bb.0:
2221 ; CHECK-NEXT: fcmgt v0.2s, v0.2s, v1.2s
2222 ; CHECK-NEXT: ret
2223 %tmp3 = fcmp ogt <2 x float> %A, %B
2224 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2225 ret <2 x i32> %tmp4
2226 }
2228 define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) {
2229 ; CHECK-LABEL: fcmogt4xfloat:
2230 ; CHECK: // %bb.0:
2231 ; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s
2232 ; CHECK-NEXT: ret
2233 %tmp3 = fcmp ogt <4 x float> %A, %B
2234 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2235 ret <4 x i32> %tmp4
2236 }
2237 define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) {
2238 ; CHECK-LABEL: fcmogt2xdouble:
2239 ; CHECK: // %bb.0:
2240 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, v1.2d
2241 ; CHECK-NEXT: ret
2242 %tmp3 = fcmp ogt <2 x double> %A, %B
2243 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2244 ret <2 x i64> %tmp4
2245 }
2247 ; OLE implemented as OGE, so check reversed operands.
2248 define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) {
2249 ; CHECK-LABEL: fcmole2xfloat:
2250 ; CHECK: // %bb.0:
2251 ; CHECK-NEXT: fcmge v0.2s, v1.2s, v0.2s
2252 ; CHECK-NEXT: ret
2253 %tmp3 = fcmp ole <2 x float> %A, %B
2254 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2255 ret <2 x i32> %tmp4
2256 }
2258 ; OLE implemented as OGE, so check reversed operands.
2259 define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) {
2260 ; CHECK-LABEL: fcmole4xfloat:
2261 ; CHECK: // %bb.0:
2262 ; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s
2263 ; CHECK-NEXT: ret
2264 %tmp3 = fcmp ole <4 x float> %A, %B
2265 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2266 ret <4 x i32> %tmp4
2267 }
2269 ; OLE implemented as OGE, so check reversed operands.
2270 define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) {
2271 ; CHECK-LABEL: fcmole2xdouble:
2272 ; CHECK: // %bb.0:
2273 ; CHECK-NEXT: fcmge v0.2d, v1.2d, v0.2d
2274 ; CHECK-NEXT: ret
2275 %tmp3 = fcmp ole <2 x double> %A, %B
2276 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2277 ret <2 x i64> %tmp4
2278 }
2280 ; OLE implemented as OGE, so check reversed operands.
2281 define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) {
2282 ; CHECK-LABEL: fcmolt2xfloat:
2283 ; CHECK: // %bb.0:
2284 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
2285 ; CHECK-NEXT: ret
2286 %tmp3 = fcmp olt <2 x float> %A, %B
2287 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2288 ret <2 x i32> %tmp4
2289 }
2291 ; OLE implemented as OGE, so check reversed operands.
2292 define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) {
2293 ; CHECK-LABEL: fcmolt4xfloat:
2294 ; CHECK: // %bb.0:
2295 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
2296 ; CHECK-NEXT: ret
2297 %tmp3 = fcmp olt <4 x float> %A, %B
2298 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2299 ret <4 x i32> %tmp4
2300 }
2302 ; OLE implemented as OGE, so check reversed operands.
2303 define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) {
2304 ; CHECK-LABEL: fcmolt2xdouble:
2305 ; CHECK: // %bb.0:
2306 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
2307 ; CHECK-NEXT: ret
2308 %tmp3 = fcmp olt <2 x double> %A, %B
2309 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2310 ret <2 x i64> %tmp4
2311 }
2313 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
2314 define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) {
2315 ; CHECK-LABEL: fcmone2xfloat:
2316 ; CHECK: // %bb.0:
2317 ; CHECK-NEXT: fcmgt v2.2s, v0.2s, v1.2s
2318 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
2319 ; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
2320 ; CHECK-NEXT: ret
2321 %tmp3 = fcmp one <2 x float> %A, %B
2322 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2323 ret <2 x i32> %tmp4
2324 }
2326 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
2327 define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) {
2328 ; CHECK-LABEL: fcmone4xfloat:
2329 ; CHECK: // %bb.0:
2330 ; CHECK-NEXT: fcmgt v2.4s, v0.4s, v1.4s
2331 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
2332 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2333 ; CHECK-NEXT: ret
2334 %tmp3 = fcmp one <4 x float> %A, %B
2335 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2336 ret <4 x i32> %tmp4
2337 }
2339 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
2340 ; todo check reversed operands
2341 define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) {
2342 ; CHECK-LABEL: fcmone2xdouble:
2343 ; CHECK: // %bb.0:
2344 ; CHECK-NEXT: fcmgt v2.2d, v0.2d, v1.2d
2345 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
2346 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2347 ; CHECK-NEXT: ret
2348 %tmp3 = fcmp one <2 x double> %A, %B
2349 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2350 ret <2 x i64> %tmp4
2351 }
2353 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
2354 define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) {
2355 ; CHECK-LABEL: fcmord2xfloat:
2356 ; CHECK: // %bb.0:
2357 ; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s
2358 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
2359 ; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
2360 ; CHECK-NEXT: ret
2361 %tmp3 = fcmp ord <2 x float> %A, %B
2362 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2363 ret <2 x i32> %tmp4
2364 }
2366 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
2367 define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) {
2368 ; CHECK-LABEL: fcmord4xfloat:
2369 ; CHECK: // %bb.0:
2370 ; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s
2371 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
2372 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2373 ; CHECK-NEXT: ret
2374 %tmp3 = fcmp ord <4 x float> %A, %B
2375 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2376 ret <4 x i32> %tmp4
2377 }
2379 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
2380 define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) {
2381 ; CHECK-LABEL: fcmord2xdouble:
2382 ; CHECK: // %bb.0:
2383 ; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d
2384 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
2385 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2386 ; CHECK-NEXT: ret
2387 %tmp3 = fcmp ord <2 x double> %A, %B
2388 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2389 ret <2 x i64> %tmp4
2390 }
2393 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
2394 define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) {
2395 ; CHECK-LABEL: fcmuno2xfloat:
2396 ; CHECK: // %bb.0:
2397 ; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s
2398 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
2399 ; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
2400 ; CHECK-NEXT: mvn v0.8b, v0.8b
2401 ; CHECK-NEXT: ret
2402 %tmp3 = fcmp uno <2 x float> %A, %B
2403 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2404 ret <2 x i32> %tmp4
2405 }
2407 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
2408 define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) {
2409 ; CHECK-LABEL: fcmuno4xfloat:
2410 ; CHECK: // %bb.0:
2411 ; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s
2412 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
2413 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2414 ; CHECK-NEXT: mvn v0.16b, v0.16b
2415 ; CHECK-NEXT: ret
2416 %tmp3 = fcmp uno <4 x float> %A, %B
2417 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2418 ret <4 x i32> %tmp4
2419 }
2421 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
2422 define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) {
2423 ; CHECK-LABEL: fcmuno2xdouble:
2424 ; CHECK: // %bb.0:
2425 ; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d
2426 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
2427 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2428 ; CHECK-NEXT: mvn v0.16b, v0.16b
2429 ; CHECK-NEXT: ret
2430 %tmp3 = fcmp uno <2 x double> %A, %B
2431 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2432 ret <2 x i64> %tmp4
2433 }
2435 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
2436 define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) {
2437 ; CHECK-LABEL: fcmueq2xfloat:
2438 ; CHECK: // %bb.0:
2439 ; CHECK-NEXT: fcmgt v2.2s, v0.2s, v1.2s
2440 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
2441 ; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
2442 ; CHECK-NEXT: mvn v0.8b, v0.8b
2443 ; CHECK-NEXT: ret
2444 %tmp3 = fcmp ueq <2 x float> %A, %B
2445 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2446 ret <2 x i32> %tmp4
2447 }
2449 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
2450 define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) {
2451 ; CHECK-LABEL: fcmueq4xfloat:
2452 ; CHECK: // %bb.0:
2453 ; CHECK-NEXT: fcmgt v2.4s, v0.4s, v1.4s
2454 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
2455 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2456 ; CHECK-NEXT: mvn v0.16b, v0.16b
2457 ; CHECK-NEXT: ret
2458 %tmp3 = fcmp ueq <4 x float> %A, %B
2459 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2460 ret <4 x i32> %tmp4
2461 }
2463 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
2464 define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) {
2465 ; CHECK-LABEL: fcmueq2xdouble:
2466 ; CHECK: // %bb.0:
2467 ; CHECK-NEXT: fcmgt v2.2d, v0.2d, v1.2d
2468 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
2469 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
2470 ; CHECK-NEXT: mvn v0.16b, v0.16b
2471 ; CHECK-NEXT: ret
2472 %tmp3 = fcmp ueq <2 x double> %A, %B
2473 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2474 ret <2 x i64> %tmp4
2475 }
2477 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
2478 define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) {
2479 ; CHECK-LABEL: fcmuge2xfloat:
2480 ; CHECK: // %bb.0:
2481 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
2482 ; CHECK-NEXT: mvn v0.8b, v0.8b
2483 ; CHECK-NEXT: ret
2484 %tmp3 = fcmp uge <2 x float> %A, %B
2485 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2486 ret <2 x i32> %tmp4
2487 }
2489 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
2490 define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) {
2491 ; CHECK-LABEL: fcmuge4xfloat:
2492 ; CHECK: // %bb.0:
2493 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
2494 ; CHECK-NEXT: mvn v0.16b, v0.16b
2495 ; CHECK-NEXT: ret
2496 %tmp3 = fcmp uge <4 x float> %A, %B
2497 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2498 ret <4 x i32> %tmp4
2499 }
2501 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
2502 define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) {
2503 ; CHECK-LABEL: fcmuge2xdouble:
2504 ; CHECK: // %bb.0:
2505 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
2506 ; CHECK-NEXT: mvn v0.16b, v0.16b
2507 ; CHECK-NEXT: ret
2508 %tmp3 = fcmp uge <2 x double> %A, %B
2509 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2510 ret <2 x i64> %tmp4
2511 }
2513 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
2514 define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) {
2515 ; CHECK-LABEL: fcmugt2xfloat:
2516 ; CHECK: // %bb.0:
2517 ; CHECK-NEXT: fcmge v0.2s, v1.2s, v0.2s
2518 ; CHECK-NEXT: mvn v0.8b, v0.8b
2519 ; CHECK-NEXT: ret
2520 %tmp3 = fcmp ugt <2 x float> %A, %B
2521 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2522 ret <2 x i32> %tmp4
2523 }
2525 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
2526 define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) {
2527 ; CHECK-LABEL: fcmugt4xfloat:
2528 ; CHECK: // %bb.0:
2529 ; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s
2530 ; CHECK-NEXT: mvn v0.16b, v0.16b
2531 ; CHECK-NEXT: ret
2532 %tmp3 = fcmp ugt <4 x float> %A, %B
2533 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2534 ret <4 x i32> %tmp4
2535 }
2537 define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) {
2538 ; CHECK-LABEL: fcmugt2xdouble:
2539 ; CHECK: // %bb.0:
2540 ; CHECK-NEXT: fcmge v0.2d, v1.2d, v0.2d
2541 ; CHECK-NEXT: mvn v0.16b, v0.16b
2542 ; CHECK-NEXT: ret
2543 %tmp3 = fcmp ugt <2 x double> %A, %B
2544 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2545 ret <2 x i64> %tmp4
2546 }
2548 ; ULE implemented as !OGT.
2549 define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) {
2550 ; CHECK-LABEL: fcmule2xfloat:
2551 ; CHECK: // %bb.0:
2552 ; CHECK-NEXT: fcmgt v0.2s, v0.2s, v1.2s
2553 ; CHECK-NEXT: mvn v0.8b, v0.8b
2554 ; CHECK-NEXT: ret
2555 %tmp3 = fcmp ule <2 x float> %A, %B
2556 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2557 ret <2 x i32> %tmp4
2558 }
2560 ; ULE implemented as !OGT.
2561 define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) {
2562 ; CHECK-LABEL: fcmule4xfloat:
2563 ; CHECK: // %bb.0:
2564 ; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s
2565 ; CHECK-NEXT: mvn v0.16b, v0.16b
2566 ; CHECK-NEXT: ret
2567 %tmp3 = fcmp ule <4 x float> %A, %B
2568 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2569 ret <4 x i32> %tmp4
2570 }
2572 ; ULE implemented as !OGT.
2573 define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) {
2574 ; CHECK-LABEL: fcmule2xdouble:
2575 ; CHECK: // %bb.0:
2576 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, v1.2d
2577 ; CHECK-NEXT: mvn v0.16b, v0.16b
2578 ; CHECK-NEXT: ret
2579 %tmp3 = fcmp ule <2 x double> %A, %B
2580 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2581 ret <2 x i64> %tmp4
2582 }
2584 ; ULT implemented as !OGE.
2585 define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) {
2586 ; CHECK-LABEL: fcmult2xfloat:
2587 ; CHECK: // %bb.0:
2588 ; CHECK-NEXT: fcmge v0.2s, v0.2s, v1.2s
2589 ; CHECK-NEXT: mvn v0.8b, v0.8b
2590 ; CHECK-NEXT: ret
2591 %tmp3 = fcmp ult <2 x float> %A, %B
2592 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2593 ret <2 x i32> %tmp4
2594 }
2596 ; ULT implemented as !OGE.
2597 define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) {
2598 ; CHECK-LABEL: fcmult4xfloat:
2599 ; CHECK: // %bb.0:
2600 ; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s
2601 ; CHECK-NEXT: mvn v0.16b, v0.16b
2602 ; CHECK-NEXT: ret
2603 %tmp3 = fcmp ult <4 x float> %A, %B
2604 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2605 ret <4 x i32> %tmp4
2606 }
2608 ; ULT implemented as !OGE.
2609 define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) {
2610 ; CHECK-LABEL: fcmult2xdouble:
2611 ; CHECK: // %bb.0:
2612 ; CHECK-NEXT: fcmge v0.2d, v0.2d, v1.2d
2613 ; CHECK-NEXT: mvn v0.16b, v0.16b
2614 ; CHECK-NEXT: ret
2615 %tmp3 = fcmp ult <2 x double> %A, %B
2616 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2617 ret <2 x i64> %tmp4
2618 }
2620 ; UNE = !OEQ.
2621 define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) {
2622 ; CHECK-LABEL: fcmune2xfloat:
2623 ; CHECK: // %bb.0:
2624 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
2625 ; CHECK-NEXT: mvn v0.8b, v0.8b
2626 ; CHECK-NEXT: ret
2627 %tmp3 = fcmp une <2 x float> %A, %B
2628 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2629 ret <2 x i32> %tmp4
2630 }
2632 ; UNE = !OEQ.
2633 define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) {
2634 ; CHECK-LABEL: fcmune4xfloat:
2635 ; CHECK: // %bb.0:
2636 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
2637 ; CHECK-NEXT: mvn v0.16b, v0.16b
2638 ; CHECK-NEXT: ret
2639 %tmp3 = fcmp une <4 x float> %A, %B
2640 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2641 ret <4 x i32> %tmp4
2642 }
2644 ; UNE = !OEQ.
2645 define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
2646 ; CHECK-LABEL: fcmune2xdouble:
2647 ; CHECK: // %bb.0:
2648 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d
2649 ; CHECK-NEXT: mvn v0.16b, v0.16b
2650 ; CHECK-NEXT: ret
2651 %tmp3 = fcmp une <2 x double> %A, %B
2652 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2653 ret <2 x i64> %tmp4
2654 }
2656 define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) {
2657 ; CHECK-LABEL: fcmoeqz2xfloat:
2658 ; CHECK: // %bb.0:
2659 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0
2660 ; CHECK-NEXT: ret
2661 %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer
2662 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2663 ret <2 x i32> %tmp4
2664 }
2666 define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) {
2667 ; CHECK-LABEL: fcmoeqz4xfloat:
2668 ; CHECK: // %bb.0:
2669 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0
2670 ; CHECK-NEXT: ret
2671 %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer
2672 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2673 ret <4 x i32> %tmp4
2674 }
2675 define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) {
2676 ; CHECK-LABEL: fcmoeqz2xdouble:
2677 ; CHECK: // %bb.0:
2678 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0
2679 ; CHECK-NEXT: ret
2680 %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer
2681 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2682 ret <2 x i64> %tmp4
2683 }
2686 define <2 x i32> @fcmogez2xfloat(<2 x float> %A) {
2687 ; CHECK-LABEL: fcmogez2xfloat:
2688 ; CHECK: // %bb.0:
2689 ; CHECK-NEXT: fcmge v0.2s, v0.2s, #0.0
2690 ; CHECK-NEXT: ret
2691 %tmp3 = fcmp oge <2 x float> %A, zeroinitializer
2692 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2693 ret <2 x i32> %tmp4
2694 }
2696 define <4 x i32> @fcmogez4xfloat(<4 x float> %A) {
2697 ; CHECK-LABEL: fcmogez4xfloat:
2698 ; CHECK: // %bb.0:
2699 ; CHECK-NEXT: fcmge v0.4s, v0.4s, #0.0
2700 ; CHECK-NEXT: ret
2701 %tmp3 = fcmp oge <4 x float> %A, zeroinitializer
2702 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2703 ret <4 x i32> %tmp4
2704 }
2705 define <2 x i64> @fcmogez2xdouble(<2 x double> %A) {
2706 ; CHECK-LABEL: fcmogez2xdouble:
2707 ; CHECK: // %bb.0:
2708 ; CHECK-NEXT: fcmge v0.2d, v0.2d, #0.0
2709 ; CHECK-NEXT: ret
2710 %tmp3 = fcmp oge <2 x double> %A, zeroinitializer
2711 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2712 ret <2 x i64> %tmp4
2713 }
2715 define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) {
2716 ; CHECK-LABEL: fcmogtz2xfloat:
2717 ; CHECK: // %bb.0:
2718 ; CHECK-NEXT: fcmgt v0.2s, v0.2s, #0.0
2719 ; CHECK-NEXT: ret
2720 %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer
2721 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2722 ret <2 x i32> %tmp4
2723 }
2725 define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) {
2726 ; CHECK-LABEL: fcmogtz4xfloat:
2727 ; CHECK: // %bb.0:
2728 ; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0
2729 ; CHECK-NEXT: ret
2730 %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer
2731 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2732 ret <4 x i32> %tmp4
2733 }
2734 define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) {
2735 ; CHECK-LABEL: fcmogtz2xdouble:
2736 ; CHECK: // %bb.0:
2737 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0
2738 ; CHECK-NEXT: ret
2739 %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer
2740 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2741 ret <2 x i64> %tmp4
2742 }
2744 define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) {
2745 ; CHECK-LABEL: fcmoltz2xfloat:
2746 ; CHECK: // %bb.0:
2747 ; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
2748 ; CHECK-NEXT: ret
2749 %tmp3 = fcmp olt <2 x float> %A, zeroinitializer
2750 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2751 ret <2 x i32> %tmp4
2752 }
2754 define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) {
2755 ; CHECK-LABEL: fcmoltz4xfloat:
2756 ; CHECK: // %bb.0:
2757 ; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
2758 ; CHECK-NEXT: ret
2759 %tmp3 = fcmp olt <4 x float> %A, zeroinitializer
2760 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2761 ret <4 x i32> %tmp4
2762 }
2764 define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) {
2765 ; CHECK-LABEL: fcmoltz2xdouble:
2766 ; CHECK: // %bb.0:
2767 ; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
2768 ; CHECK-NEXT: ret
2769 %tmp3 = fcmp olt <2 x double> %A, zeroinitializer
2770 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2771 ret <2 x i64> %tmp4
2772 }
2774 define <2 x i32> @fcmolez2xfloat(<2 x float> %A) {
2775 ; CHECK-LABEL: fcmolez2xfloat:
2776 ; CHECK: // %bb.0:
2777 ; CHECK-NEXT: fcmle v0.2s, v0.2s, #0.0
2778 ; CHECK-NEXT: ret
2779 %tmp3 = fcmp ole <2 x float> %A, zeroinitializer
2780 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2781 ret <2 x i32> %tmp4
2782 }
2784 define <4 x i32> @fcmolez4xfloat(<4 x float> %A) {
2785 ; CHECK-LABEL: fcmolez4xfloat:
2786 ; CHECK: // %bb.0:
2787 ; CHECK-NEXT: fcmle v0.4s, v0.4s, #0.0
2788 ; CHECK-NEXT: ret
2789 %tmp3 = fcmp ole <4 x float> %A, zeroinitializer
2790 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2791 ret <4 x i32> %tmp4
2792 }
2794 define <2 x i64> @fcmolez2xdouble(<2 x double> %A) {
2795 ; CHECK-LABEL: fcmolez2xdouble:
2796 ; CHECK: // %bb.0:
2797 ; CHECK-NEXT: fcmle v0.2d, v0.2d, #0.0
2798 ; CHECK-NEXT: ret
2799 %tmp3 = fcmp ole <2 x double> %A, zeroinitializer
2800 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2801 ret <2 x i64> %tmp4
2802 }
2804 ; ONE with zero = OLT | OGT
2805 define <2 x i32> @fcmonez2xfloat(<2 x float> %A) {
2806 ; CHECK-LABEL: fcmonez2xfloat:
2807 ; CHECK: // %bb.0:
2808 ; CHECK-NEXT: fcmgt v1.2s, v0.2s, #0.0
2809 ; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
2810 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
2811 ; CHECK-NEXT: ret
2812 %tmp3 = fcmp one <2 x float> %A, zeroinitializer
2813 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2814 ret <2 x i32> %tmp4
2815 }
2817 ; ONE with zero = OLT | OGT
2818 define <4 x i32> @fcmonez4xfloat(<4 x float> %A) {
2819 ; CHECK-LABEL: fcmonez4xfloat:
2820 ; CHECK: // %bb.0:
2821 ; CHECK-NEXT: fcmgt v1.4s, v0.4s, #0.0
2822 ; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
2823 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
2824 ; CHECK-NEXT: ret
2825 %tmp3 = fcmp one <4 x float> %A, zeroinitializer
2826 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2827 ret <4 x i32> %tmp4
2828 }
2830 ; ONE with zero = OLT | OGT
2831 define <2 x i64> @fcmonez2xdouble(<2 x double> %A) {
2832 ; CHECK-LABEL: fcmonez2xdouble:
2833 ; CHECK: // %bb.0:
2834 ; CHECK-NEXT: fcmgt v1.2d, v0.2d, #0.0
2835 ; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
2836 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
2837 ; CHECK-NEXT: ret
2838 %tmp3 = fcmp one <2 x double> %A, zeroinitializer
2839 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2840 ret <2 x i64> %tmp4
2841 }
2843 ; ORD with zero = OLT | OGE
2844 define <2 x i32> @fcmordz2xfloat(<2 x float> %A) {
2845 ; CHECK-SD-LABEL: fcmordz2xfloat:
2846 ; CHECK-SD: // %bb.0:
2847 ; CHECK-SD-NEXT: fcmge v1.2s, v0.2s, #0.0
2848 ; CHECK-SD-NEXT: fcmlt v0.2s, v0.2s, #0.0
2849 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
2850 ; CHECK-SD-NEXT: ret
2851 ;
2852 ; CHECK-GI-LABEL: fcmordz2xfloat:
2853 ; CHECK-GI: // %bb.0:
2854 ; CHECK-GI-NEXT: fcmeq v0.2s, v0.2s, v0.2s
2855 ; CHECK-GI-NEXT: ret
2856 %tmp3 = fcmp ord <2 x float> %A, zeroinitializer
2857 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2858 ret <2 x i32> %tmp4
2859 }
2861 ; ORD with zero = OLT | OGE
2862 define <4 x i32> @fcmordz4xfloat(<4 x float> %A) {
2863 ; CHECK-SD-LABEL: fcmordz4xfloat:
2864 ; CHECK-SD: // %bb.0:
2865 ; CHECK-SD-NEXT: fcmge v1.4s, v0.4s, #0.0
2866 ; CHECK-SD-NEXT: fcmlt v0.4s, v0.4s, #0.0
2867 ; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
2868 ; CHECK-SD-NEXT: ret
2869 ;
2870 ; CHECK-GI-LABEL: fcmordz4xfloat:
2871 ; CHECK-GI: // %bb.0:
2872 ; CHECK-GI-NEXT: fcmeq v0.4s, v0.4s, v0.4s
2873 ; CHECK-GI-NEXT: ret
2874 %tmp3 = fcmp ord <4 x float> %A, zeroinitializer
2875 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2876 ret <4 x i32> %tmp4
2877 }
2879 ; ORD with zero = OLT | OGE
2880 define <2 x i64> @fcmordz2xdouble(<2 x double> %A) {
2881 ; CHECK-SD-LABEL: fcmordz2xdouble:
2882 ; CHECK-SD: // %bb.0:
2883 ; CHECK-SD-NEXT: fcmge v1.2d, v0.2d, #0.0
2884 ; CHECK-SD-NEXT: fcmlt v0.2d, v0.2d, #0.0
2885 ; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
2886 ; CHECK-SD-NEXT: ret
2887 ;
2888 ; CHECK-GI-LABEL: fcmordz2xdouble:
2889 ; CHECK-GI: // %bb.0:
2890 ; CHECK-GI-NEXT: fcmeq v0.2d, v0.2d, v0.2d
2891 ; CHECK-GI-NEXT: ret
2892 %tmp3 = fcmp ord <2 x double> %A, zeroinitializer
2893 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2894 ret <2 x i64> %tmp4
2895 }
2897 ; UEQ with zero = !ONE = !(OLT |OGT)
2898 define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) {
2899 ; CHECK-LABEL: fcmueqz2xfloat:
2900 ; CHECK: // %bb.0:
2901 ; CHECK-NEXT: fcmgt v1.2s, v0.2s, #0.0
2902 ; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
2903 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
2904 ; CHECK-NEXT: mvn v0.8b, v0.8b
2905 ; CHECK-NEXT: ret
2906 %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer
2907 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2908 ret <2 x i32> %tmp4
2909 }
2911 ; UEQ with zero = !ONE = !(OLT |OGT)
2912 define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) {
2913 ; CHECK-LABEL: fcmueqz4xfloat:
2914 ; CHECK: // %bb.0:
2915 ; CHECK-NEXT: fcmgt v1.4s, v0.4s, #0.0
2916 ; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
2917 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
2918 ; CHECK-NEXT: mvn v0.16b, v0.16b
2919 ; CHECK-NEXT: ret
2920 %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer
2921 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2922 ret <4 x i32> %tmp4
2923 }
2925 ; UEQ with zero = !ONE = !(OLT |OGT)
2926 define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
2927 ; CHECK-LABEL: fcmueqz2xdouble:
2928 ; CHECK: // %bb.0:
2929 ; CHECK-NEXT: fcmgt v1.2d, v0.2d, #0.0
2930 ; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
2931 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
2932 ; CHECK-NEXT: mvn v0.16b, v0.16b
2933 ; CHECK-NEXT: ret
2934 %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer
2935 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2936 ret <2 x i64> %tmp4
2937 }
2939 ; UGE with zero = !OLT
2940 define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
2941 ; CHECK-LABEL: fcmugez2xfloat:
2942 ; CHECK: // %bb.0:
2943 ; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
2944 ; CHECK-NEXT: mvn v0.8b, v0.8b
2945 ; CHECK-NEXT: ret
2946 %tmp3 = fcmp uge <2 x float> %A, zeroinitializer
2947 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2948 ret <2 x i32> %tmp4
2949 }
2951 ; UGE with zero = !OLT
2952 define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
2953 ; CHECK-LABEL: fcmugez4xfloat:
2954 ; CHECK: // %bb.0:
2955 ; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
2956 ; CHECK-NEXT: mvn v0.16b, v0.16b
2957 ; CHECK-NEXT: ret
2958 %tmp3 = fcmp uge <4 x float> %A, zeroinitializer
2959 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2960 ret <4 x i32> %tmp4
2961 }
2963 ; UGE with zero = !OLT
2964 define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
2965 ; CHECK-LABEL: fcmugez2xdouble:
2966 ; CHECK: // %bb.0:
2967 ; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
2968 ; CHECK-NEXT: mvn v0.16b, v0.16b
2969 ; CHECK-NEXT: ret
2970 %tmp3 = fcmp uge <2 x double> %A, zeroinitializer
2971 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2972 ret <2 x i64> %tmp4
2973 }
2975 ; UGT with zero = !OLE
2976 define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
2977 ; CHECK-LABEL: fcmugtz2xfloat:
2978 ; CHECK: // %bb.0:
2979 ; CHECK-NEXT: fcmle v0.2s, v0.2s, #0.0
2980 ; CHECK-NEXT: mvn v0.8b, v0.8b
2981 ; CHECK-NEXT: ret
2982 %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer
2983 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2984 ret <2 x i32> %tmp4
2985 }
2987 ; UGT with zero = !OLE
2988 define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
2989 ; CHECK-LABEL: fcmugtz4xfloat:
2990 ; CHECK: // %bb.0:
2991 ; CHECK-NEXT: fcmle v0.4s, v0.4s, #0.0
2992 ; CHECK-NEXT: mvn v0.16b, v0.16b
2993 ; CHECK-NEXT: ret
2994 %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer
2995 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2996 ret <4 x i32> %tmp4
2997 }
2999 ; UGT with zero = !OLE
3000 define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
3001 ; CHECK-LABEL: fcmugtz2xdouble:
3002 ; CHECK: // %bb.0:
3003 ; CHECK-NEXT: fcmle v0.2d, v0.2d, #0.0
3004 ; CHECK-NEXT: mvn v0.16b, v0.16b
3005 ; CHECK-NEXT: ret
3006 %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer
3007 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3008 ret <2 x i64> %tmp4
3009 }
3011 ; ULT with zero = !OGE
3012 define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
3013 ; CHECK-LABEL: fcmultz2xfloat:
3014 ; CHECK: // %bb.0:
3015 ; CHECK-NEXT: fcmge v0.2s, v0.2s, #0.0
3016 ; CHECK-NEXT: mvn v0.8b, v0.8b
3017 ; CHECK-NEXT: ret
3018 %tmp3 = fcmp ult <2 x float> %A, zeroinitializer
3019 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3020 ret <2 x i32> %tmp4
3021 }
3023 define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
3024 ; CHECK-LABEL: fcmultz4xfloat:
3025 ; CHECK: // %bb.0:
3026 ; CHECK-NEXT: fcmge v0.4s, v0.4s, #0.0
3027 ; CHECK-NEXT: mvn v0.16b, v0.16b
3028 ; CHECK-NEXT: ret
3029 %tmp3 = fcmp ult <4 x float> %A, zeroinitializer
3030 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3031 ret <4 x i32> %tmp4
3032 }
3034 define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
3035 ; CHECK-LABEL: fcmultz2xdouble:
3036 ; CHECK: // %bb.0:
3037 ; CHECK-NEXT: fcmge v0.2d, v0.2d, #0.0
3038 ; CHECK-NEXT: mvn v0.16b, v0.16b
3039 ; CHECK-NEXT: ret
3040 %tmp3 = fcmp ult <2 x double> %A, zeroinitializer
3041 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3042 ret <2 x i64> %tmp4
3043 }
3045 ; ULE with zero = !OGT
3046 define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
3047 ; CHECK-LABEL: fcmulez2xfloat:
3048 ; CHECK: // %bb.0:
3049 ; CHECK-NEXT: fcmgt v0.2s, v0.2s, #0.0
3050 ; CHECK-NEXT: mvn v0.8b, v0.8b
3051 ; CHECK-NEXT: ret
3052 %tmp3 = fcmp ule <2 x float> %A, zeroinitializer
3053 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3054 ret <2 x i32> %tmp4
3055 }
3057 ; ULE with zero = !OGT
3058 define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
3059 ; CHECK-LABEL: fcmulez4xfloat:
3060 ; CHECK: // %bb.0:
3061 ; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0
3062 ; CHECK-NEXT: mvn v0.16b, v0.16b
3063 ; CHECK-NEXT: ret
3064 %tmp3 = fcmp ule <4 x float> %A, zeroinitializer
3065 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3066 ret <4 x i32> %tmp4
3067 }
3069 ; ULE with zero = !OGT
3070 define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
3071 ; CHECK-LABEL: fcmulez2xdouble:
3072 ; CHECK: // %bb.0:
3073 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0
3074 ; CHECK-NEXT: mvn v0.16b, v0.16b
3075 ; CHECK-NEXT: ret
3076 %tmp3 = fcmp ule <2 x double> %A, zeroinitializer
3077 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3078 ret <2 x i64> %tmp4
3079 }
3081 ; UNE with zero = !OEQ with zero
3082 define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
3083 ; CHECK-LABEL: fcmunez2xfloat:
3084 ; CHECK: // %bb.0:
3085 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0
3086 ; CHECK-NEXT: mvn v0.8b, v0.8b
3087 ; CHECK-NEXT: ret
3088 %tmp3 = fcmp une <2 x float> %A, zeroinitializer
3089 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3090 ret <2 x i32> %tmp4
3091 }
3093 ; UNE with zero = !OEQ with zero
3094 define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
3095 ; CHECK-LABEL: fcmunez4xfloat:
3096 ; CHECK: // %bb.0:
3097 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0
3098 ; CHECK-NEXT: mvn v0.16b, v0.16b
3099 ; CHECK-NEXT: ret
3100 %tmp3 = fcmp une <4 x float> %A, zeroinitializer
3101 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3102 ret <4 x i32> %tmp4
3103 }
3105 ; UNE with zero = !OEQ with zero
3106 define <2 x i64> @fcmunez2xdouble(<2 x double> %A) {
3107 ; CHECK-LABEL: fcmunez2xdouble:
3108 ; CHECK: // %bb.0:
3109 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0
3110 ; CHECK-NEXT: mvn v0.16b, v0.16b
3111 ; CHECK-NEXT: ret
3112 %tmp3 = fcmp une <2 x double> %A, zeroinitializer
3113 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3114 ret <2 x i64> %tmp4
3115 }
3117 ; UNO with zero = !ORD = !(OLT | OGE)
3118 define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) {
3119 ; CHECK-LABEL: fcmunoz2xfloat:
3120 ; CHECK: // %bb.0:
3121 ; CHECK-NEXT: fcmge v1.2s, v0.2s, #0.0
3122 ; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
3123 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
3124 ; CHECK-NEXT: mvn v0.8b, v0.8b
3125 ; CHECK-NEXT: ret
3126 %tmp3 = fcmp uno <2 x float> %A, zeroinitializer
3127 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3128 ret <2 x i32> %tmp4
3129 }
3131 ; UNO with zero = !ORD = !(OLT | OGE)
3132 define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) {
3133 ; CHECK-LABEL: fcmunoz4xfloat:
3134 ; CHECK: // %bb.0:
3135 ; CHECK-NEXT: fcmge v1.4s, v0.4s, #0.0
3136 ; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
3137 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
3138 ; CHECK-NEXT: mvn v0.16b, v0.16b
3139 ; CHECK-NEXT: ret
3140 %tmp3 = fcmp uno <4 x float> %A, zeroinitializer
3141 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3142 ret <4 x i32> %tmp4
3143 }
3145 ; UNO with zero = !ORD = !(OLT | OGE)
3146 define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) {
3147 ; CHECK-LABEL: fcmunoz2xdouble:
3148 ; CHECK: // %bb.0:
3149 ; CHECK-NEXT: fcmge v1.2d, v0.2d, #0.0
3150 ; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
3151 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
3152 ; CHECK-NEXT: mvn v0.16b, v0.16b
3153 ; CHECK-NEXT: ret
3154 %tmp3 = fcmp uno <2 x double> %A, zeroinitializer
3155 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3156 ret <2 x i64> %tmp4
3158 }
3160 define <2 x i32> @fcmoeq2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3161 ; CHECK-LABEL: fcmoeq2xfloat_fast:
3162 ; CHECK: // %bb.0:
3163 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
3164 ; CHECK-NEXT: ret
3165 %tmp3 = fcmp fast oeq <2 x float> %A, %B
3166 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3167 ret <2 x i32> %tmp4
3168 }
3170 define <4 x i32> @fcmoeq4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3171 ; CHECK-LABEL: fcmoeq4xfloat_fast:
3172 ; CHECK: // %bb.0:
3173 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
3174 ; CHECK-NEXT: ret
3175 %tmp3 = fcmp fast oeq <4 x float> %A, %B
3176 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3177 ret <4 x i32> %tmp4
3178 }
3179 define <2 x i64> @fcmoeq2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3180 ; CHECK-LABEL: fcmoeq2xdouble_fast:
3181 ; CHECK: // %bb.0:
3182 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d
3183 ; CHECK-NEXT: ret
3184 %tmp3 = fcmp fast oeq <2 x double> %A, %B
3185 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3186 ret <2 x i64> %tmp4
3187 }
3189 define <2 x i32> @fcmoge2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3190 ; CHECK-LABEL: fcmoge2xfloat_fast:
3191 ; CHECK: // %bb.0:
3192 ; CHECK-NEXT: fcmge v0.2s, v0.2s, v1.2s
3193 ; CHECK-NEXT: ret
3194 %tmp3 = fcmp fast oge <2 x float> %A, %B
3195 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3196 ret <2 x i32> %tmp4
3197 }
3199 define <4 x i32> @fcmoge4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3200 ; CHECK-LABEL: fcmoge4xfloat_fast:
3201 ; CHECK: // %bb.0:
3202 ; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s
3203 ; CHECK-NEXT: ret
3204 %tmp3 = fcmp fast oge <4 x float> %A, %B
3205 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3206 ret <4 x i32> %tmp4
3207 }
3208 define <2 x i64> @fcmoge2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3209 ; CHECK-LABEL: fcmoge2xdouble_fast:
3210 ; CHECK: // %bb.0:
3211 ; CHECK-NEXT: fcmge v0.2d, v0.2d, v1.2d
3212 ; CHECK-NEXT: ret
3213 %tmp3 = fcmp fast oge <2 x double> %A, %B
3214 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3215 ret <2 x i64> %tmp4
3216 }
3218 define <2 x i32> @fcmogt2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3219 ; CHECK-LABEL: fcmogt2xfloat_fast:
3220 ; CHECK: // %bb.0:
3221 ; CHECK-NEXT: fcmgt v0.2s, v0.2s, v1.2s
3222 ; CHECK-NEXT: ret
3223 %tmp3 = fcmp fast ogt <2 x float> %A, %B
3224 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3225 ret <2 x i32> %tmp4
3226 }
3228 define <4 x i32> @fcmogt4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3229 ; CHECK-LABEL: fcmogt4xfloat_fast:
3230 ; CHECK: // %bb.0:
3231 ; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s
3232 ; CHECK-NEXT: ret
3233 %tmp3 = fcmp fast ogt <4 x float> %A, %B
3234 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3235 ret <4 x i32> %tmp4
3236 }
3237 define <2 x i64> @fcmogt2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3238 ; CHECK-LABEL: fcmogt2xdouble_fast:
3239 ; CHECK: // %bb.0:
3240 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, v1.2d
3241 ; CHECK-NEXT: ret
3242 %tmp3 = fcmp fast ogt <2 x double> %A, %B
3243 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3244 ret <2 x i64> %tmp4
3245 }
3247 define <2 x i32> @fcmole2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3248 ; CHECK-LABEL: fcmole2xfloat_fast:
3249 ; CHECK: // %bb.0:
3250 ; CHECK-NEXT: fcmge v0.2s, v1.2s, v0.2s
3251 ; CHECK-NEXT: ret
3252 %tmp3 = fcmp fast ole <2 x float> %A, %B
3253 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3254 ret <2 x i32> %tmp4
3255 }
3257 define <4 x i32> @fcmole4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3258 ; CHECK-LABEL: fcmole4xfloat_fast:
3259 ; CHECK: // %bb.0:
3260 ; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s
3261 ; CHECK-NEXT: ret
3262 %tmp3 = fcmp fast ole <4 x float> %A, %B
3263 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3264 ret <4 x i32> %tmp4
3265 }
3267 define <2 x i64> @fcmole2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3268 ; CHECK-LABEL: fcmole2xdouble_fast:
3269 ; CHECK: // %bb.0:
3270 ; CHECK-NEXT: fcmge v0.2d, v1.2d, v0.2d
3271 ; CHECK-NEXT: ret
3272 %tmp3 = fcmp fast ole <2 x double> %A, %B
3273 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3274 ret <2 x i64> %tmp4
3275 }
3277 define <2 x i32> @fcmolt2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3278 ; CHECK-LABEL: fcmolt2xfloat_fast:
3279 ; CHECK: // %bb.0:
3280 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
3281 ; CHECK-NEXT: ret
3282 %tmp3 = fcmp fast olt <2 x float> %A, %B
3283 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3284 ret <2 x i32> %tmp4
3285 }
3287 define <4 x i32> @fcmolt4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3288 ; CHECK-LABEL: fcmolt4xfloat_fast:
3289 ; CHECK: // %bb.0:
3290 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
3291 ; CHECK-NEXT: ret
3292 %tmp3 = fcmp fast olt <4 x float> %A, %B
3293 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3294 ret <4 x i32> %tmp4
3295 }
3297 define <2 x i64> @fcmolt2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3298 ; CHECK-LABEL: fcmolt2xdouble_fast:
3299 ; CHECK: // %bb.0:
3300 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
3301 ; CHECK-NEXT: ret
3302 %tmp3 = fcmp fast olt <2 x double> %A, %B
3303 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3304 ret <2 x i64> %tmp4
3305 }
3307 define <2 x i32> @fcmone2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3308 ; CHECK-SD-LABEL: fcmone2xfloat_fast:
3309 ; CHECK-SD: // %bb.0:
3310 ; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, v1.2s
3311 ; CHECK-SD-NEXT: mvn v0.8b, v0.8b
3312 ; CHECK-SD-NEXT: ret
3313 ;
3314 ; CHECK-GI-LABEL: fcmone2xfloat_fast:
3315 ; CHECK-GI: // %bb.0:
3316 ; CHECK-GI-NEXT: fcmgt v2.2s, v0.2s, v1.2s
3317 ; CHECK-GI-NEXT: fcmgt v0.2s, v1.2s, v0.2s
3318 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v2.8b
3319 ; CHECK-GI-NEXT: ret
3320 %tmp3 = fcmp fast one <2 x float> %A, %B
3321 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3322 ret <2 x i32> %tmp4
3323 }
3325 define <4 x i32> @fcmone4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3326 ; CHECK-SD-LABEL: fcmone4xfloat_fast:
3327 ; CHECK-SD: // %bb.0:
3328 ; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s
3329 ; CHECK-SD-NEXT: mvn v0.16b, v0.16b
3330 ; CHECK-SD-NEXT: ret
3331 ;
3332 ; CHECK-GI-LABEL: fcmone4xfloat_fast:
3333 ; CHECK-GI: // %bb.0:
3334 ; CHECK-GI-NEXT: fcmgt v2.4s, v0.4s, v1.4s
3335 ; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
3336 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b
3337 ; CHECK-GI-NEXT: ret
3338 %tmp3 = fcmp fast one <4 x float> %A, %B
3339 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3340 ret <4 x i32> %tmp4
3341 }
3343 define <2 x i64> @fcmone2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3344 ; CHECK-SD-LABEL: fcmone2xdouble_fast:
3345 ; CHECK-SD: // %bb.0:
3346 ; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, v1.2d
3347 ; CHECK-SD-NEXT: mvn v0.16b, v0.16b
3348 ; CHECK-SD-NEXT: ret
3349 ;
3350 ; CHECK-GI-LABEL: fcmone2xdouble_fast:
3351 ; CHECK-GI: // %bb.0:
3352 ; CHECK-GI-NEXT: fcmgt v2.2d, v0.2d, v1.2d
3353 ; CHECK-GI-NEXT: fcmgt v0.2d, v1.2d, v0.2d
3354 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b
3355 ; CHECK-GI-NEXT: ret
3356 %tmp3 = fcmp fast one <2 x double> %A, %B
3357 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3358 ret <2 x i64> %tmp4
3359 }
3361 define <2 x i32> @fcmord2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3362 ; CHECK-LABEL: fcmord2xfloat_fast:
3363 ; CHECK: // %bb.0:
3364 ; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s
3365 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
3366 ; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
3367 ; CHECK-NEXT: ret
3368 %tmp3 = fcmp fast ord <2 x float> %A, %B
3369 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3370 ret <2 x i32> %tmp4
3371 }
3373 define <4 x i32> @fcmord4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3374 ; CHECK-LABEL: fcmord4xfloat_fast:
3375 ; CHECK: // %bb.0:
3376 ; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s
3377 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
3378 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
3379 ; CHECK-NEXT: ret
3380 %tmp3 = fcmp fast ord <4 x float> %A, %B
3381 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3382 ret <4 x i32> %tmp4
3383 }
3385 define <2 x i64> @fcmord2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3386 ; CHECK-LABEL: fcmord2xdouble_fast:
3387 ; CHECK: // %bb.0:
3388 ; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d
3389 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
3390 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
3391 ; CHECK-NEXT: ret
3392 %tmp3 = fcmp fast ord <2 x double> %A, %B
3393 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3394 ret <2 x i64> %tmp4
3395 }
3398 define <2 x i32> @fcmuno2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3399 ; CHECK-LABEL: fcmuno2xfloat_fast:
3400 ; CHECK: // %bb.0:
3401 ; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s
3402 ; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s
3403 ; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
3404 ; CHECK-NEXT: mvn v0.8b, v0.8b
3405 ; CHECK-NEXT: ret
3406 %tmp3 = fcmp fast uno <2 x float> %A, %B
3407 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3408 ret <2 x i32> %tmp4
3409 }
3411 define <4 x i32> @fcmuno4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3412 ; CHECK-LABEL: fcmuno4xfloat_fast:
3413 ; CHECK: // %bb.0:
3414 ; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s
3415 ; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s
3416 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
3417 ; CHECK-NEXT: mvn v0.16b, v0.16b
3418 ; CHECK-NEXT: ret
3419 %tmp3 = fcmp fast uno <4 x float> %A, %B
3420 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3421 ret <4 x i32> %tmp4
3422 }
3424 define <2 x i64> @fcmuno2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3425 ; CHECK-LABEL: fcmuno2xdouble_fast:
3426 ; CHECK: // %bb.0:
3427 ; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d
3428 ; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d
3429 ; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
3430 ; CHECK-NEXT: mvn v0.16b, v0.16b
3431 ; CHECK-NEXT: ret
3432 %tmp3 = fcmp fast uno <2 x double> %A, %B
3433 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3434 ret <2 x i64> %tmp4
3435 }
3437 define <2 x i32> @fcmueq2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3438 ; CHECK-SD-LABEL: fcmueq2xfloat_fast:
3439 ; CHECK-SD: // %bb.0:
3440 ; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, v1.2s
3441 ; CHECK-SD-NEXT: ret
3442 ;
3443 ; CHECK-GI-LABEL: fcmueq2xfloat_fast:
3444 ; CHECK-GI: // %bb.0:
3445 ; CHECK-GI-NEXT: fcmgt v2.2s, v0.2s, v1.2s
3446 ; CHECK-GI-NEXT: fcmgt v0.2s, v1.2s, v0.2s
3447 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v2.8b
3448 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
3449 ; CHECK-GI-NEXT: ret
3450 %tmp3 = fcmp fast ueq <2 x float> %A, %B
3451 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3452 ret <2 x i32> %tmp4
3453 }
3455 define <4 x i32> @fcmueq4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3456 ; CHECK-SD-LABEL: fcmueq4xfloat_fast:
3457 ; CHECK-SD: // %bb.0:
3458 ; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s
3459 ; CHECK-SD-NEXT: ret
3460 ;
3461 ; CHECK-GI-LABEL: fcmueq4xfloat_fast:
3462 ; CHECK-GI: // %bb.0:
3463 ; CHECK-GI-NEXT: fcmgt v2.4s, v0.4s, v1.4s
3464 ; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
3465 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b
3466 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3467 ; CHECK-GI-NEXT: ret
3468 %tmp3 = fcmp fast ueq <4 x float> %A, %B
3469 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3470 ret <4 x i32> %tmp4
3471 }
3473 define <2 x i64> @fcmueq2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3474 ; CHECK-SD-LABEL: fcmueq2xdouble_fast:
3475 ; CHECK-SD: // %bb.0:
3476 ; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, v1.2d
3477 ; CHECK-SD-NEXT: ret
3478 ;
3479 ; CHECK-GI-LABEL: fcmueq2xdouble_fast:
3480 ; CHECK-GI: // %bb.0:
3481 ; CHECK-GI-NEXT: fcmgt v2.2d, v0.2d, v1.2d
3482 ; CHECK-GI-NEXT: fcmgt v0.2d, v1.2d, v0.2d
3483 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b
3484 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3485 ; CHECK-GI-NEXT: ret
3486 %tmp3 = fcmp fast ueq <2 x double> %A, %B
3487 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3488 ret <2 x i64> %tmp4
3489 }
3491 define <2 x i32> @fcmuge2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3492 ; CHECK-SD-LABEL: fcmuge2xfloat_fast:
3493 ; CHECK-SD: // %bb.0:
3494 ; CHECK-SD-NEXT: fcmge v0.2s, v0.2s, v1.2s
3495 ; CHECK-SD-NEXT: ret
3496 ;
3497 ; CHECK-GI-LABEL: fcmuge2xfloat_fast:
3498 ; CHECK-GI: // %bb.0:
3499 ; CHECK-GI-NEXT: fcmgt v0.2s, v1.2s, v0.2s
3500 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
3501 ; CHECK-GI-NEXT: ret
3502 %tmp3 = fcmp fast uge <2 x float> %A, %B
3503 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3504 ret <2 x i32> %tmp4
3505 }
3507 define <4 x i32> @fcmuge4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3508 ; CHECK-SD-LABEL: fcmuge4xfloat_fast:
3509 ; CHECK-SD: // %bb.0:
3510 ; CHECK-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s
3511 ; CHECK-SD-NEXT: ret
3512 ;
3513 ; CHECK-GI-LABEL: fcmuge4xfloat_fast:
3514 ; CHECK-GI: // %bb.0:
3515 ; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s
3516 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3517 ; CHECK-GI-NEXT: ret
3518 %tmp3 = fcmp fast uge <4 x float> %A, %B
3519 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3520 ret <4 x i32> %tmp4
3521 }
3523 define <2 x i64> @fcmuge2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3524 ; CHECK-SD-LABEL: fcmuge2xdouble_fast:
3525 ; CHECK-SD: // %bb.0:
3526 ; CHECK-SD-NEXT: fcmge v0.2d, v0.2d, v1.2d
3527 ; CHECK-SD-NEXT: ret
3528 ;
3529 ; CHECK-GI-LABEL: fcmuge2xdouble_fast:
3530 ; CHECK-GI: // %bb.0:
3531 ; CHECK-GI-NEXT: fcmgt v0.2d, v1.2d, v0.2d
3532 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3533 ; CHECK-GI-NEXT: ret
3534 %tmp3 = fcmp fast uge <2 x double> %A, %B
3535 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3536 ret <2 x i64> %tmp4
3537 }
3539 define <2 x i32> @fcmugt2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3540 ; CHECK-SD-LABEL: fcmugt2xfloat_fast:
3541 ; CHECK-SD: // %bb.0:
3542 ; CHECK-SD-NEXT: fcmgt v0.2s, v0.2s, v1.2s
3543 ; CHECK-SD-NEXT: ret
3544 ;
3545 ; CHECK-GI-LABEL: fcmugt2xfloat_fast:
3546 ; CHECK-GI: // %bb.0:
3547 ; CHECK-GI-NEXT: fcmge v0.2s, v1.2s, v0.2s
3548 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
3549 ; CHECK-GI-NEXT: ret
3550 %tmp3 = fcmp fast ugt <2 x float> %A, %B
3551 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3552 ret <2 x i32> %tmp4
3553 }
3555 define <4 x i32> @fcmugt4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3556 ; CHECK-SD-LABEL: fcmugt4xfloat_fast:
3557 ; CHECK-SD: // %bb.0:
3558 ; CHECK-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s
3559 ; CHECK-SD-NEXT: ret
3560 ;
3561 ; CHECK-GI-LABEL: fcmugt4xfloat_fast:
3562 ; CHECK-GI: // %bb.0:
3563 ; CHECK-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s
3564 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3565 ; CHECK-GI-NEXT: ret
3566 %tmp3 = fcmp fast ugt <4 x float> %A, %B
3567 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3568 ret <4 x i32> %tmp4
3569 }
3571 define <2 x i64> @fcmugt2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3572 ; CHECK-SD-LABEL: fcmugt2xdouble_fast:
3573 ; CHECK-SD: // %bb.0:
3574 ; CHECK-SD-NEXT: fcmgt v0.2d, v0.2d, v1.2d
3575 ; CHECK-SD-NEXT: ret
3576 ;
3577 ; CHECK-GI-LABEL: fcmugt2xdouble_fast:
3578 ; CHECK-GI: // %bb.0:
3579 ; CHECK-GI-NEXT: fcmge v0.2d, v1.2d, v0.2d
3580 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3581 ; CHECK-GI-NEXT: ret
3582 %tmp3 = fcmp fast ugt <2 x double> %A, %B
3583 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3584 ret <2 x i64> %tmp4
3585 }
3587 define <2 x i32> @fcmule2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3588 ; CHECK-SD-LABEL: fcmule2xfloat_fast:
3589 ; CHECK-SD: // %bb.0:
3590 ; CHECK-SD-NEXT: fcmge v0.2s, v1.2s, v0.2s
3591 ; CHECK-SD-NEXT: ret
3592 ;
3593 ; CHECK-GI-LABEL: fcmule2xfloat_fast:
3594 ; CHECK-GI: // %bb.0:
3595 ; CHECK-GI-NEXT: fcmgt v0.2s, v0.2s, v1.2s
3596 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
3597 ; CHECK-GI-NEXT: ret
3598 %tmp3 = fcmp fast ule <2 x float> %A, %B
3599 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3600 ret <2 x i32> %tmp4
3601 }
3603 define <4 x i32> @fcmule4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3604 ; CHECK-SD-LABEL: fcmule4xfloat_fast:
3605 ; CHECK-SD: // %bb.0:
3606 ; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s
3607 ; CHECK-SD-NEXT: ret
3608 ;
3609 ; CHECK-GI-LABEL: fcmule4xfloat_fast:
3610 ; CHECK-GI: // %bb.0:
3611 ; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s
3612 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3613 ; CHECK-GI-NEXT: ret
3614 %tmp3 = fcmp fast ule <4 x float> %A, %B
3615 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3616 ret <4 x i32> %tmp4
3617 }
3619 define <2 x i64> @fcmule2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3620 ; CHECK-SD-LABEL: fcmule2xdouble_fast:
3621 ; CHECK-SD: // %bb.0:
3622 ; CHECK-SD-NEXT: fcmge v0.2d, v1.2d, v0.2d
3623 ; CHECK-SD-NEXT: ret
3624 ;
3625 ; CHECK-GI-LABEL: fcmule2xdouble_fast:
3626 ; CHECK-GI: // %bb.0:
3627 ; CHECK-GI-NEXT: fcmgt v0.2d, v0.2d, v1.2d
3628 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3629 ; CHECK-GI-NEXT: ret
3630 %tmp3 = fcmp fast ule <2 x double> %A, %B
3631 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3632 ret <2 x i64> %tmp4
3633 }
3635 define <2 x i32> @fcmult2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3636 ; CHECK-SD-LABEL: fcmult2xfloat_fast:
3637 ; CHECK-SD: // %bb.0:
3638 ; CHECK-SD-NEXT: fcmgt v0.2s, v1.2s, v0.2s
3639 ; CHECK-SD-NEXT: ret
3640 ;
3641 ; CHECK-GI-LABEL: fcmult2xfloat_fast:
3642 ; CHECK-GI: // %bb.0:
3643 ; CHECK-GI-NEXT: fcmge v0.2s, v0.2s, v1.2s
3644 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
3645 ; CHECK-GI-NEXT: ret
3646 %tmp3 = fcmp fast ult <2 x float> %A, %B
3647 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3648 ret <2 x i32> %tmp4
3649 }
3651 define <4 x i32> @fcmult4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3652 ; CHECK-SD-LABEL: fcmult4xfloat_fast:
3653 ; CHECK-SD: // %bb.0:
3654 ; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s
3655 ; CHECK-SD-NEXT: ret
3656 ;
3657 ; CHECK-GI-LABEL: fcmult4xfloat_fast:
3658 ; CHECK-GI: // %bb.0:
3659 ; CHECK-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s
3660 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3661 ; CHECK-GI-NEXT: ret
3662 %tmp3 = fcmp fast ult <4 x float> %A, %B
3663 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3664 ret <4 x i32> %tmp4
3665 }
3667 define <2 x i64> @fcmult2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3668 ; CHECK-SD-LABEL: fcmult2xdouble_fast:
3669 ; CHECK-SD: // %bb.0:
3670 ; CHECK-SD-NEXT: fcmgt v0.2d, v1.2d, v0.2d
3671 ; CHECK-SD-NEXT: ret
3672 ;
3673 ; CHECK-GI-LABEL: fcmult2xdouble_fast:
3674 ; CHECK-GI: // %bb.0:
3675 ; CHECK-GI-NEXT: fcmge v0.2d, v0.2d, v1.2d
3676 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3677 ; CHECK-GI-NEXT: ret
3678 %tmp3 = fcmp fast ult <2 x double> %A, %B
3679 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3680 ret <2 x i64> %tmp4
3681 }
3683 define <2 x i32> @fcmune2xfloat_fast(<2 x float> %A, <2 x float> %B) {
3684 ; CHECK-LABEL: fcmune2xfloat_fast:
3685 ; CHECK: // %bb.0:
3686 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
3687 ; CHECK-NEXT: mvn v0.8b, v0.8b
3688 ; CHECK-NEXT: ret
3689 %tmp3 = fcmp fast une <2 x float> %A, %B
3690 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3691 ret <2 x i32> %tmp4
3692 }
3694 define <4 x i32> @fcmune4xfloat_fast(<4 x float> %A, <4 x float> %B) {
3695 ; CHECK-LABEL: fcmune4xfloat_fast:
3696 ; CHECK: // %bb.0:
3697 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
3698 ; CHECK-NEXT: mvn v0.16b, v0.16b
3699 ; CHECK-NEXT: ret
3700 %tmp3 = fcmp fast une <4 x float> %A, %B
3701 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3702 ret <4 x i32> %tmp4
3703 }
3705 define <2 x i64> @fcmune2xdouble_fast(<2 x double> %A, <2 x double> %B) {
3706 ; CHECK-LABEL: fcmune2xdouble_fast:
3707 ; CHECK: // %bb.0:
3708 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d
3709 ; CHECK-NEXT: mvn v0.16b, v0.16b
3710 ; CHECK-NEXT: ret
3711 %tmp3 = fcmp fast une <2 x double> %A, %B
3712 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3713 ret <2 x i64> %tmp4
3714 }
3716 define <2 x i32> @fcmoeqz2xfloat_fast(<2 x float> %A) {
3717 ; CHECK-LABEL: fcmoeqz2xfloat_fast:
3718 ; CHECK: // %bb.0:
3719 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0
3720 ; CHECK-NEXT: ret
3721 %tmp3 = fcmp fast oeq <2 x float> %A, zeroinitializer
3722 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3723 ret <2 x i32> %tmp4
3724 }
3726 define <4 x i32> @fcmoeqz4xfloat_fast(<4 x float> %A) {
3727 ; CHECK-LABEL: fcmoeqz4xfloat_fast:
3728 ; CHECK: // %bb.0:
3729 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0
3730 ; CHECK-NEXT: ret
3731 %tmp3 = fcmp fast oeq <4 x float> %A, zeroinitializer
3732 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3733 ret <4 x i32> %tmp4
3734 }
3735 define <2 x i64> @fcmoeqz2xdouble_fast(<2 x double> %A) {
3736 ; CHECK-LABEL: fcmoeqz2xdouble_fast:
3737 ; CHECK: // %bb.0:
3738 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0
3739 ; CHECK-NEXT: ret
3740 %tmp3 = fcmp fast oeq <2 x double> %A, zeroinitializer
3741 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3742 ret <2 x i64> %tmp4
3743 }
3746 define <2 x i32> @fcmogez2xfloat_fast(<2 x float> %A) {
3747 ; CHECK-LABEL: fcmogez2xfloat_fast:
3748 ; CHECK: // %bb.0:
3749 ; CHECK-NEXT: fcmge v0.2s, v0.2s, #0.0
3750 ; CHECK-NEXT: ret
3751 %tmp3 = fcmp fast oge <2 x float> %A, zeroinitializer
3752 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3753 ret <2 x i32> %tmp4
3754 }
3756 define <4 x i32> @fcmogez4xfloat_fast(<4 x float> %A) {
3757 ; CHECK-LABEL: fcmogez4xfloat_fast:
3758 ; CHECK: // %bb.0:
3759 ; CHECK-NEXT: fcmge v0.4s, v0.4s, #0.0
3760 ; CHECK-NEXT: ret
3761 %tmp3 = fcmp fast oge <4 x float> %A, zeroinitializer
3762 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3763 ret <4 x i32> %tmp4
3764 }
3765 define <2 x i64> @fcmogez2xdouble_fast(<2 x double> %A) {
3766 ; CHECK-LABEL: fcmogez2xdouble_fast:
3767 ; CHECK: // %bb.0:
3768 ; CHECK-NEXT: fcmge v0.2d, v0.2d, #0.0
3769 ; CHECK-NEXT: ret
3770 %tmp3 = fcmp fast oge <2 x double> %A, zeroinitializer
3771 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3772 ret <2 x i64> %tmp4
3773 }
3775 define <2 x i32> @fcmogtz2xfloat_fast(<2 x float> %A) {
3776 ; CHECK-LABEL: fcmogtz2xfloat_fast:
3777 ; CHECK: // %bb.0:
3778 ; CHECK-NEXT: fcmgt v0.2s, v0.2s, #0.0
3779 ; CHECK-NEXT: ret
3780 %tmp3 = fcmp fast ogt <2 x float> %A, zeroinitializer
3781 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3782 ret <2 x i32> %tmp4
3783 }
3785 define <4 x i32> @fcmogtz4xfloat_fast(<4 x float> %A) {
3786 ; CHECK-LABEL: fcmogtz4xfloat_fast:
3787 ; CHECK: // %bb.0:
3788 ; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0
3789 ; CHECK-NEXT: ret
3790 %tmp3 = fcmp fast ogt <4 x float> %A, zeroinitializer
3791 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3792 ret <4 x i32> %tmp4
3793 }
3794 define <2 x i64> @fcmogtz2xdouble_fast(<2 x double> %A) {
3795 ; CHECK-LABEL: fcmogtz2xdouble_fast:
3796 ; CHECK: // %bb.0:
3797 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0
3798 ; CHECK-NEXT: ret
3799 %tmp3 = fcmp fast ogt <2 x double> %A, zeroinitializer
3800 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3801 ret <2 x i64> %tmp4
3802 }
3804 define <2 x i32> @fcmoltz2xfloat_fast(<2 x float> %A) {
3805 ; CHECK-LABEL: fcmoltz2xfloat_fast:
3806 ; CHECK: // %bb.0:
3807 ; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
3808 ; CHECK-NEXT: ret
3809 %tmp3 = fcmp fast olt <2 x float> %A, zeroinitializer
3810 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3811 ret <2 x i32> %tmp4
3812 }
3814 define <4 x i32> @fcmoltz4xfloat_fast(<4 x float> %A) {
3815 ; CHECK-LABEL: fcmoltz4xfloat_fast:
3816 ; CHECK: // %bb.0:
3817 ; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
3818 ; CHECK-NEXT: ret
3819 %tmp3 = fcmp fast olt <4 x float> %A, zeroinitializer
3820 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3821 ret <4 x i32> %tmp4
3822 }
3824 define <2 x i64> @fcmoltz2xdouble_fast(<2 x double> %A) {
3825 ; CHECK-LABEL: fcmoltz2xdouble_fast:
3826 ; CHECK: // %bb.0:
3827 ; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
3828 ; CHECK-NEXT: ret
3829 %tmp3 = fcmp fast olt <2 x double> %A, zeroinitializer
3830 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3831 ret <2 x i64> %tmp4
3832 }
3834 define <2 x i32> @fcmolez2xfloat_fast(<2 x float> %A) {
3835 ; CHECK-LABEL: fcmolez2xfloat_fast:
3836 ; CHECK: // %bb.0:
3837 ; CHECK-NEXT: fcmle v0.2s, v0.2s, #0.0
3838 ; CHECK-NEXT: ret
3839 %tmp3 = fcmp fast ole <2 x float> %A, zeroinitializer
3840 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3841 ret <2 x i32> %tmp4
3842 }
3844 define <4 x i32> @fcmolez4xfloat_fast(<4 x float> %A) {
3845 ; CHECK-LABEL: fcmolez4xfloat_fast:
3846 ; CHECK: // %bb.0:
3847 ; CHECK-NEXT: fcmle v0.4s, v0.4s, #0.0
3848 ; CHECK-NEXT: ret
3849 %tmp3 = fcmp fast ole <4 x float> %A, zeroinitializer
3850 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3851 ret <4 x i32> %tmp4
3852 }
3854 define <2 x i64> @fcmolez2xdouble_fast(<2 x double> %A) {
3855 ; CHECK-LABEL: fcmolez2xdouble_fast:
3856 ; CHECK: // %bb.0:
3857 ; CHECK-NEXT: fcmle v0.2d, v0.2d, #0.0
3858 ; CHECK-NEXT: ret
3859 %tmp3 = fcmp fast ole <2 x double> %A, zeroinitializer
3860 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3861 ret <2 x i64> %tmp4
3862 }
3864 define <2 x i32> @fcmonez2xfloat_fast(<2 x float> %A) {
3865 ; CHECK-SD-LABEL: fcmonez2xfloat_fast:
3866 ; CHECK-SD: // %bb.0:
3867 ; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, #0.0
3868 ; CHECK-SD-NEXT: mvn v0.8b, v0.8b
3869 ; CHECK-SD-NEXT: ret
3870 ;
3871 ; CHECK-GI-LABEL: fcmonez2xfloat_fast:
3872 ; CHECK-GI: // %bb.0:
3873 ; CHECK-GI-NEXT: fcmgt v1.2s, v0.2s, #0.0
3874 ; CHECK-GI-NEXT: fcmlt v0.2s, v0.2s, #0.0
3875 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
3876 ; CHECK-GI-NEXT: ret
3877 %tmp3 = fcmp fast one <2 x float> %A, zeroinitializer
3878 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3879 ret <2 x i32> %tmp4
3880 }
3882 define <4 x i32> @fcmonez4xfloat_fast(<4 x float> %A) {
3883 ; CHECK-SD-LABEL: fcmonez4xfloat_fast:
3884 ; CHECK-SD: // %bb.0:
3885 ; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, #0.0
3886 ; CHECK-SD-NEXT: mvn v0.16b, v0.16b
3887 ; CHECK-SD-NEXT: ret
3888 ;
3889 ; CHECK-GI-LABEL: fcmonez4xfloat_fast:
3890 ; CHECK-GI: // %bb.0:
3891 ; CHECK-GI-NEXT: fcmgt v1.4s, v0.4s, #0.0
3892 ; CHECK-GI-NEXT: fcmlt v0.4s, v0.4s, #0.0
3893 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
3894 ; CHECK-GI-NEXT: ret
3895 %tmp3 = fcmp fast one <4 x float> %A, zeroinitializer
3896 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3897 ret <4 x i32> %tmp4
3898 }
3900 define <2 x i64> @fcmonez2xdouble_fast(<2 x double> %A) {
3901 ; CHECK-SD-LABEL: fcmonez2xdouble_fast:
3902 ; CHECK-SD: // %bb.0:
3903 ; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, #0.0
3904 ; CHECK-SD-NEXT: mvn v0.16b, v0.16b
3905 ; CHECK-SD-NEXT: ret
3906 ;
3907 ; CHECK-GI-LABEL: fcmonez2xdouble_fast:
3908 ; CHECK-GI: // %bb.0:
3909 ; CHECK-GI-NEXT: fcmgt v1.2d, v0.2d, #0.0
3910 ; CHECK-GI-NEXT: fcmlt v0.2d, v0.2d, #0.0
3911 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
3912 ; CHECK-GI-NEXT: ret
3913 %tmp3 = fcmp fast one <2 x double> %A, zeroinitializer
3914 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3915 ret <2 x i64> %tmp4
3916 }
3918 define <2 x i32> @fcmordz2xfloat_fast(<2 x float> %A) {
3919 ; CHECK-SD-LABEL: fcmordz2xfloat_fast:
3920 ; CHECK-SD: // %bb.0:
3921 ; CHECK-SD-NEXT: fcmge v1.2s, v0.2s, #0.0
3922 ; CHECK-SD-NEXT: fcmlt v0.2s, v0.2s, #0.0
3923 ; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
3924 ; CHECK-SD-NEXT: ret
3925 ;
3926 ; CHECK-GI-LABEL: fcmordz2xfloat_fast:
3927 ; CHECK-GI: // %bb.0:
3928 ; CHECK-GI-NEXT: fcmeq v0.2s, v0.2s, v0.2s
3929 ; CHECK-GI-NEXT: ret
3930 %tmp3 = fcmp fast ord <2 x float> %A, zeroinitializer
3931 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3932 ret <2 x i32> %tmp4
3933 }
3935 define <4 x i32> @fcmordz4xfloat_fast(<4 x float> %A) {
3936 ; CHECK-SD-LABEL: fcmordz4xfloat_fast:
3937 ; CHECK-SD: // %bb.0:
3938 ; CHECK-SD-NEXT: fcmge v1.4s, v0.4s, #0.0
3939 ; CHECK-SD-NEXT: fcmlt v0.4s, v0.4s, #0.0
3940 ; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
3941 ; CHECK-SD-NEXT: ret
3942 ;
3943 ; CHECK-GI-LABEL: fcmordz4xfloat_fast:
3944 ; CHECK-GI: // %bb.0:
3945 ; CHECK-GI-NEXT: fcmeq v0.4s, v0.4s, v0.4s
3946 ; CHECK-GI-NEXT: ret
3947 %tmp3 = fcmp fast ord <4 x float> %A, zeroinitializer
3948 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
3949 ret <4 x i32> %tmp4
3950 }
3952 define <2 x i64> @fcmordz2xdouble_fast(<2 x double> %A) {
3953 ; CHECK-SD-LABEL: fcmordz2xdouble_fast:
3954 ; CHECK-SD: // %bb.0:
3955 ; CHECK-SD-NEXT: fcmge v1.2d, v0.2d, #0.0
3956 ; CHECK-SD-NEXT: fcmlt v0.2d, v0.2d, #0.0
3957 ; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
3958 ; CHECK-SD-NEXT: ret
3959 ;
3960 ; CHECK-GI-LABEL: fcmordz2xdouble_fast:
3961 ; CHECK-GI: // %bb.0:
3962 ; CHECK-GI-NEXT: fcmeq v0.2d, v0.2d, v0.2d
3963 ; CHECK-GI-NEXT: ret
3964 %tmp3 = fcmp fast ord <2 x double> %A, zeroinitializer
3965 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
3966 ret <2 x i64> %tmp4
3967 }
3969 define <2 x i32> @fcmueqz2xfloat_fast(<2 x float> %A) {
3970 ; CHECK-SD-LABEL: fcmueqz2xfloat_fast:
3971 ; CHECK-SD: // %bb.0:
3972 ; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, #0.0
3973 ; CHECK-SD-NEXT: ret
3974 ;
3975 ; CHECK-GI-LABEL: fcmueqz2xfloat_fast:
3976 ; CHECK-GI: // %bb.0:
3977 ; CHECK-GI-NEXT: fcmgt v1.2s, v0.2s, #0.0
3978 ; CHECK-GI-NEXT: fcmlt v0.2s, v0.2s, #0.0
3979 ; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
3980 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
3981 ; CHECK-GI-NEXT: ret
3982 %tmp3 = fcmp fast ueq <2 x float> %A, zeroinitializer
3983 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
3984 ret <2 x i32> %tmp4
3985 }
3987 define <4 x i32> @fcmueqz4xfloat_fast(<4 x float> %A) {
3988 ; CHECK-SD-LABEL: fcmueqz4xfloat_fast:
3989 ; CHECK-SD: // %bb.0:
3990 ; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, #0.0
3991 ; CHECK-SD-NEXT: ret
3992 ;
3993 ; CHECK-GI-LABEL: fcmueqz4xfloat_fast:
3994 ; CHECK-GI: // %bb.0:
3995 ; CHECK-GI-NEXT: fcmgt v1.4s, v0.4s, #0.0
3996 ; CHECK-GI-NEXT: fcmlt v0.4s, v0.4s, #0.0
3997 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
3998 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
3999 ; CHECK-GI-NEXT: ret
4000 %tmp3 = fcmp fast ueq <4 x float> %A, zeroinitializer
4001 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
4002 ret <4 x i32> %tmp4
4003 }
4005 define <2 x i64> @fcmueqz2xdouble_fast(<2 x double> %A) {
4006 ; CHECK-SD-LABEL: fcmueqz2xdouble_fast:
4007 ; CHECK-SD: // %bb.0:
4008 ; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, #0.0
4009 ; CHECK-SD-NEXT: ret
4010 ;
4011 ; CHECK-GI-LABEL: fcmueqz2xdouble_fast:
4012 ; CHECK-GI: // %bb.0:
4013 ; CHECK-GI-NEXT: fcmgt v1.2d, v0.2d, #0.0
4014 ; CHECK-GI-NEXT: fcmlt v0.2d, v0.2d, #0.0
4015 ; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
4016 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4017 ; CHECK-GI-NEXT: ret
4018 %tmp3 = fcmp fast ueq <2 x double> %A, zeroinitializer
4019 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
4020 ret <2 x i64> %tmp4
4021 }
4023 define <2 x i32> @fcmugez2xfloat_fast(<2 x float> %A) {
4024 ; CHECK-SD-LABEL: fcmugez2xfloat_fast:
4025 ; CHECK-SD: // %bb.0:
4026 ; CHECK-SD-NEXT: fcmge v0.2s, v0.2s, #0.0
4027 ; CHECK-SD-NEXT: ret
4028 ;
4029 ; CHECK-GI-LABEL: fcmugez2xfloat_fast:
4030 ; CHECK-GI: // %bb.0:
4031 ; CHECK-GI-NEXT: fcmlt v0.2s, v0.2s, #0.0
4032 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
4033 ; CHECK-GI-NEXT: ret
4034 %tmp3 = fcmp fast uge <2 x float> %A, zeroinitializer
4035 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
4036 ret <2 x i32> %tmp4
4037 }
4039 define <4 x i32> @fcmugez4xfloat_fast(<4 x float> %A) {
4040 ; CHECK-SD-LABEL: fcmugez4xfloat_fast:
4041 ; CHECK-SD: // %bb.0:
4042 ; CHECK-SD-NEXT: fcmge v0.4s, v0.4s, #0.0
4043 ; CHECK-SD-NEXT: ret
4044 ;
4045 ; CHECK-GI-LABEL: fcmugez4xfloat_fast:
4046 ; CHECK-GI: // %bb.0:
4047 ; CHECK-GI-NEXT: fcmlt v0.4s, v0.4s, #0.0
4048 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4049 ; CHECK-GI-NEXT: ret
4050 %tmp3 = fcmp fast uge <4 x float> %A, zeroinitializer
4051 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
4052 ret <4 x i32> %tmp4
4053 }
4055 define <2 x i64> @fcmugez2xdouble_fast(<2 x double> %A) {
4056 ; CHECK-SD-LABEL: fcmugez2xdouble_fast:
4057 ; CHECK-SD: // %bb.0:
4058 ; CHECK-SD-NEXT: fcmge v0.2d, v0.2d, #0.0
4059 ; CHECK-SD-NEXT: ret
4060 ;
4061 ; CHECK-GI-LABEL: fcmugez2xdouble_fast:
4062 ; CHECK-GI: // %bb.0:
4063 ; CHECK-GI-NEXT: fcmlt v0.2d, v0.2d, #0.0
4064 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4065 ; CHECK-GI-NEXT: ret
4066 %tmp3 = fcmp fast uge <2 x double> %A, zeroinitializer
4067 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
4068 ret <2 x i64> %tmp4
4069 }
4071 define <2 x i32> @fcmugtz2xfloat_fast(<2 x float> %A) {
4072 ; CHECK-SD-LABEL: fcmugtz2xfloat_fast:
4073 ; CHECK-SD: // %bb.0:
4074 ; CHECK-SD-NEXT: fcmgt v0.2s, v0.2s, #0.0
4075 ; CHECK-SD-NEXT: ret
4076 ;
4077 ; CHECK-GI-LABEL: fcmugtz2xfloat_fast:
4078 ; CHECK-GI: // %bb.0:
4079 ; CHECK-GI-NEXT: fcmle v0.2s, v0.2s, #0.0
4080 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
4081 ; CHECK-GI-NEXT: ret
4082 %tmp3 = fcmp fast ugt <2 x float> %A, zeroinitializer
4083 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
4084 ret <2 x i32> %tmp4
4085 }
4087 define <4 x i32> @fcmugtz4xfloat_fast(<4 x float> %A) {
4088 ; CHECK-SD-LABEL: fcmugtz4xfloat_fast:
4089 ; CHECK-SD: // %bb.0:
4090 ; CHECK-SD-NEXT: fcmgt v0.4s, v0.4s, #0.0
4091 ; CHECK-SD-NEXT: ret
4092 ;
4093 ; CHECK-GI-LABEL: fcmugtz4xfloat_fast:
4094 ; CHECK-GI: // %bb.0:
4095 ; CHECK-GI-NEXT: fcmle v0.4s, v0.4s, #0.0
4096 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4097 ; CHECK-GI-NEXT: ret
4098 %tmp3 = fcmp fast ugt <4 x float> %A, zeroinitializer
4099 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
4100 ret <4 x i32> %tmp4
4101 }
4103 define <2 x i64> @fcmugtz2xdouble_fast(<2 x double> %A) {
4104 ; CHECK-SD-LABEL: fcmugtz2xdouble_fast:
4105 ; CHECK-SD: // %bb.0:
4106 ; CHECK-SD-NEXT: fcmgt v0.2d, v0.2d, #0.0
4107 ; CHECK-SD-NEXT: ret
4108 ;
4109 ; CHECK-GI-LABEL: fcmugtz2xdouble_fast:
4110 ; CHECK-GI: // %bb.0:
4111 ; CHECK-GI-NEXT: fcmle v0.2d, v0.2d, #0.0
4112 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4113 ; CHECK-GI-NEXT: ret
4114 %tmp3 = fcmp fast ugt <2 x double> %A, zeroinitializer
4115 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
4116 ret <2 x i64> %tmp4
4117 }
4119 define <2 x i32> @fcmultz2xfloat_fast(<2 x float> %A) {
4120 ; CHECK-SD-LABEL: fcmultz2xfloat_fast:
4121 ; CHECK-SD: // %bb.0:
4122 ; CHECK-SD-NEXT: fcmlt v0.2s, v0.2s, #0.0
4123 ; CHECK-SD-NEXT: ret
4124 ;
4125 ; CHECK-GI-LABEL: fcmultz2xfloat_fast:
4126 ; CHECK-GI: // %bb.0:
4127 ; CHECK-GI-NEXT: fcmge v0.2s, v0.2s, #0.0
4128 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
4129 ; CHECK-GI-NEXT: ret
4130 %tmp3 = fcmp fast ult <2 x float> %A, zeroinitializer
4131 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
4132 ret <2 x i32> %tmp4
4133 }
4135 define <4 x i32> @fcmultz4xfloat_fast(<4 x float> %A) {
4136 ; CHECK-SD-LABEL: fcmultz4xfloat_fast:
4137 ; CHECK-SD: // %bb.0:
4138 ; CHECK-SD-NEXT: fcmlt v0.4s, v0.4s, #0.0
4139 ; CHECK-SD-NEXT: ret
4140 ;
4141 ; CHECK-GI-LABEL: fcmultz4xfloat_fast:
4142 ; CHECK-GI: // %bb.0:
4143 ; CHECK-GI-NEXT: fcmge v0.4s, v0.4s, #0.0
4144 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4145 ; CHECK-GI-NEXT: ret
4146 %tmp3 = fcmp fast ult <4 x float> %A, zeroinitializer
4147 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
4148 ret <4 x i32> %tmp4
4149 }
4151 define <2 x i64> @fcmultz2xdouble_fast(<2 x double> %A) {
4152 ; CHECK-SD-LABEL: fcmultz2xdouble_fast:
4153 ; CHECK-SD: // %bb.0:
4154 ; CHECK-SD-NEXT: fcmlt v0.2d, v0.2d, #0.0
4155 ; CHECK-SD-NEXT: ret
4156 ;
4157 ; CHECK-GI-LABEL: fcmultz2xdouble_fast:
4158 ; CHECK-GI: // %bb.0:
4159 ; CHECK-GI-NEXT: fcmge v0.2d, v0.2d, #0.0
4160 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4161 ; CHECK-GI-NEXT: ret
4162 %tmp3 = fcmp fast ult <2 x double> %A, zeroinitializer
4163 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
4164 ret <2 x i64> %tmp4
4165 }
4167 ; ULE with zero = !OGT
4168 define <2 x i32> @fcmulez2xfloat_fast(<2 x float> %A) {
4169 ; CHECK-SD-LABEL: fcmulez2xfloat_fast:
4170 ; CHECK-SD: // %bb.0:
4171 ; CHECK-SD-NEXT: fcmle v0.2s, v0.2s, #0.0
4172 ; CHECK-SD-NEXT: ret
4173 ;
4174 ; CHECK-GI-LABEL: fcmulez2xfloat_fast:
4175 ; CHECK-GI: // %bb.0:
4176 ; CHECK-GI-NEXT: fcmgt v0.2s, v0.2s, #0.0
4177 ; CHECK-GI-NEXT: mvn v0.8b, v0.8b
4178 ; CHECK-GI-NEXT: ret
4179 %tmp3 = fcmp fast ule <2 x float> %A, zeroinitializer
4180 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
4181 ret <2 x i32> %tmp4
4182 }
4184 define <4 x i32> @fcmulez4xfloat_fast(<4 x float> %A) {
4185 ; CHECK-SD-LABEL: fcmulez4xfloat_fast:
4186 ; CHECK-SD: // %bb.0:
4187 ; CHECK-SD-NEXT: fcmle v0.4s, v0.4s, #0.0
4188 ; CHECK-SD-NEXT: ret
4189 ;
4190 ; CHECK-GI-LABEL: fcmulez4xfloat_fast:
4191 ; CHECK-GI: // %bb.0:
4192 ; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, #0.0
4193 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4194 ; CHECK-GI-NEXT: ret
4195 %tmp3 = fcmp fast ule <4 x float> %A, zeroinitializer
4196 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
4197 ret <4 x i32> %tmp4
4198 }
4200 define <2 x i64> @fcmulez2xdouble_fast(<2 x double> %A) {
4201 ; CHECK-SD-LABEL: fcmulez2xdouble_fast:
4202 ; CHECK-SD: // %bb.0:
4203 ; CHECK-SD-NEXT: fcmle v0.2d, v0.2d, #0.0
4204 ; CHECK-SD-NEXT: ret
4205 ;
4206 ; CHECK-GI-LABEL: fcmulez2xdouble_fast:
4207 ; CHECK-GI: // %bb.0:
4208 ; CHECK-GI-NEXT: fcmgt v0.2d, v0.2d, #0.0
4209 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4210 ; CHECK-GI-NEXT: ret
4211 %tmp3 = fcmp fast ule <2 x double> %A, zeroinitializer
4212 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
4213 ret <2 x i64> %tmp4
4214 }
4216 define <2 x i32> @fcmunez2xfloat_fast(<2 x float> %A) {
4217 ; CHECK-LABEL: fcmunez2xfloat_fast:
4218 ; CHECK: // %bb.0:
4219 ; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0
4220 ; CHECK-NEXT: mvn v0.8b, v0.8b
4221 ; CHECK-NEXT: ret
4222 %tmp3 = fcmp fast une <2 x float> %A, zeroinitializer
4223 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
4224 ret <2 x i32> %tmp4
4225 }
4227 define <4 x i32> @fcmunez4xfloat_fast(<4 x float> %A) {
4228 ; CHECK-LABEL: fcmunez4xfloat_fast:
4229 ; CHECK: // %bb.0:
4230 ; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0
4231 ; CHECK-NEXT: mvn v0.16b, v0.16b
4232 ; CHECK-NEXT: ret
4233 %tmp3 = fcmp fast une <4 x float> %A, zeroinitializer
4234 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
4235 ret <4 x i32> %tmp4
4236 }
4238 define <2 x i64> @fcmunez2xdouble_fast(<2 x double> %A) {
4239 ; CHECK-LABEL: fcmunez2xdouble_fast:
4240 ; CHECK: // %bb.0:
4241 ; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0
4242 ; CHECK-NEXT: mvn v0.16b, v0.16b
4243 ; CHECK-NEXT: ret
4244 %tmp3 = fcmp fast une <2 x double> %A, zeroinitializer
4245 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
4246 ret <2 x i64> %tmp4
4247 }
4249 define <2 x i32> @fcmunoz2xfloat_fast(<2 x float> %A) {
4250 ; CHECK-LABEL: fcmunoz2xfloat_fast:
4251 ; CHECK: // %bb.0:
4252 ; CHECK-NEXT: fcmge v1.2s, v0.2s, #0.0
4253 ; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0
4254 ; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
4255 ; CHECK-NEXT: mvn v0.8b, v0.8b
4256 ; CHECK-NEXT: ret
4257 %tmp3 = fcmp fast uno <2 x float> %A, zeroinitializer
4258 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
4259 ret <2 x i32> %tmp4
4260 }
4262 define <4 x i32> @fcmunoz4xfloat_fast(<4 x float> %A) {
4263 ; CHECK-LABEL: fcmunoz4xfloat_fast:
4264 ; CHECK: // %bb.0:
4265 ; CHECK-NEXT: fcmge v1.4s, v0.4s, #0.0
4266 ; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0
4267 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
4268 ; CHECK-NEXT: mvn v0.16b, v0.16b
4269 ; CHECK-NEXT: ret
4270 %tmp3 = fcmp fast uno <4 x float> %A, zeroinitializer
4271 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
4272 ret <4 x i32> %tmp4
4273 }
4275 define <2 x i64> @fcmunoz2xdouble_fast(<2 x double> %A) {
4276 ; CHECK-LABEL: fcmunoz2xdouble_fast:
4277 ; CHECK: // %bb.0:
4278 ; CHECK-NEXT: fcmge v1.2d, v0.2d, #0.0
4279 ; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0
4280 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
4281 ; CHECK-NEXT: mvn v0.16b, v0.16b
4282 ; CHECK-NEXT: ret
4283 %tmp3 = fcmp fast uno <2 x double> %A, zeroinitializer
4284 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
4285 ret <2 x i64> %tmp4
4287 }
4289 ; Test SETCC fast-math flags are propagated when combining zext(setcc).
4290 define <4 x i32> @fcmule4xfloat_fast_zext(<4 x float> %A, <4 x float> %B) {
4291 ; CHECK-SD-LABEL: fcmule4xfloat_fast_zext:
4292 ; CHECK-SD: // %bb.0:
4293 ; CHECK-SD-NEXT: movi v2.4s, #1
4294 ; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s
4295 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
4296 ; CHECK-SD-NEXT: ret
4297 ;
4298 ; CHECK-GI-LABEL: fcmule4xfloat_fast_zext:
4299 ; CHECK-GI: // %bb.0:
4300 ; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s
4301 ; CHECK-GI-NEXT: adrp x8, .LCPI322_0
4302 ; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI322_0]
4303 ; CHECK-GI-NEXT: bic v0.16b, v1.16b, v0.16b
4304 ; CHECK-GI-NEXT: ret
4305 ; GISEL-LABEL: fcmule4xfloat_fast_zext:
4306 ; GISEL: // %bb.0:
4307 ; GISEL-NEXT: fcmgt v0.4s, v0.4s, v1.4s
4308 ; GISEL-NEXT: adrp x8, .LCPI322_0
4309 ; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI322_0]
4310 ; GISEL-NEXT: bic v0.16b, v1.16b, v0.16b
4311 ; GISEL-NEXT: ret
4312 %tmp3 = fcmp fast ule <4 x float> %A, %B
4313 %tmp4 = zext <4 x i1> %tmp3 to <4 x i32>
4314 ret <4 x i32> %tmp4
4315 }
4317 ; Test SETCC fast-math flags are propagated when combining aext(setcc).
4318 define <4 x i1> @fcmule4xfloat_fast_aext(<4 x float> %A, <4 x float> %B) {
4319 ; CHECK-SD-LABEL: fcmule4xfloat_fast_aext:
4320 ; CHECK-SD: // %bb.0:
4321 ; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s
4322 ; CHECK-SD-NEXT: xtn v0.4h, v0.4s
4323 ; CHECK-SD-NEXT: ret
4324 ;
4325 ; CHECK-GI-LABEL: fcmule4xfloat_fast_aext:
4326 ; CHECK-GI: // %bb.0:
4327 ; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s
4328 ; CHECK-GI-NEXT: mvn v0.16b, v0.16b
4329 ; CHECK-GI-NEXT: xtn v0.4h, v0.4s
4330 ; CHECK-GI-NEXT: ret
4331 %tmp3 = fcmp fast ule <4 x float> %A, %B
4332 ret <4 x i1> %tmp3
4333 }
4335 define <4 x i64> @fcmoeq4xdouble(<4 x double> %A, <4 x double> %B) {
4336 ; CHECK-SD-LABEL: fcmoeq4xdouble:
4337 ; CHECK-SD: // %bb.0:
4338 ; CHECK-SD-NEXT: fcmeq v1.2d, v1.2d, v3.2d
4339 ; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, v2.2d
4340 ; CHECK-SD-NEXT: ret
4341 ;
4342 ; CHECK-GI-LABEL: fcmoeq4xdouble:
4343 ; CHECK-GI: // %bb.0:
4344 ; CHECK-GI-NEXT: fcmeq v0.2d, v0.2d, v2.2d
4345 ; CHECK-GI-NEXT: fcmeq v1.2d, v1.2d, v3.2d
4346 ; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63
4347 ; CHECK-GI-NEXT: shl v1.2d, v1.2d, #63
4348 ; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63
4349 ; CHECK-GI-NEXT: sshr v1.2d, v1.2d, #63
4350 ; CHECK-GI-NEXT: ret
4351 %tmp3 = fcmp oeq <4 x double> %A, %B
4352 %tmp4 = sext <4 x i1> %tmp3 to <4 x i64>
4353 ret <4 x i64> %tmp4
4354 }
4356 define <8 x i32> @fcmoeq8xfloat(<8 x float> %A, <8 x float> %B) {
4357 ; CHECK-SD-LABEL: fcmoeq8xfloat:
4358 ; CHECK-SD: // %bb.0:
4359 ; CHECK-SD-NEXT: fcmeq v1.4s, v1.4s, v3.4s
4360 ; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v2.4s
4361 ; CHECK-SD-NEXT: ret
4362 ;
4363 ; CHECK-GI-LABEL: fcmoeq8xfloat:
4364 ; CHECK-GI: // %bb.0:
4365 ; CHECK-GI-NEXT: fcmeq v0.4s, v0.4s, v2.4s
4366 ; CHECK-GI-NEXT: fcmeq v1.4s, v1.4s, v3.4s
4367 ; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
4368 ; CHECK-GI-NEXT: shl v1.4s, v1.4s, #31
4369 ; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
4370 ; CHECK-GI-NEXT: sshr v1.4s, v1.4s, #31
4371 ; CHECK-GI-NEXT: ret
4372 %tmp3 = fcmp oeq <8 x float> %A, %B
4373 %tmp4 = sext <8 x i1> %tmp3 to <8 x i32>
4374 ret <8 x i32> %tmp4
4375 }