| blob | a20a76c00418d11637052de8fd93df7a02fd3be6 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+neon | FileCheck %s
3 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
6 define i1 @test_redand_v1i1(<1 x i1> %a) {
7 ; CHECK-LABEL: test_redand_v1i1:
8 ; CHECK: // %bb.0:
9 ; CHECK-NEXT: and w0, w0, #0x1
10 ; CHECK-NEXT: ret
11 ;
12 ; GISEL-LABEL: test_redand_v1i1:
13 ; GISEL: // %bb.0:
14 ; GISEL-NEXT: and w0, w0, #0x1
15 ; GISEL-NEXT: ret
16 %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
17 ret i1 %or_result
18 }
20 define i1 @test_redand_v2i1(<2 x i1> %a) {
21 ; CHECK-LABEL: test_redand_v2i1:
22 ; CHECK: // %bb.0:
23 ; CHECK-NEXT: shl v0.2s, v0.2s, #31
24 ; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
25 ; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s
26 ; CHECK-NEXT: fmov w8, s0
27 ; CHECK-NEXT: and w0, w8, #0x1
28 ; CHECK-NEXT: ret
29 ;
30 ; GISEL-LABEL: test_redand_v2i1:
31 ; GISEL: // %bb.0:
32 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
33 ; GISEL-NEXT: mov s1, v0.s[1]
34 ; GISEL-NEXT: fmov w8, s0
35 ; GISEL-NEXT: fmov w9, s1
36 ; GISEL-NEXT: and w8, w8, w9
37 ; GISEL-NEXT: and w0, w8, #0x1
38 ; GISEL-NEXT: ret
39 %or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
40 ret i1 %or_result
41 }
43 define i1 @test_redand_v4i1(<4 x i1> %a) {
44 ; CHECK-LABEL: test_redand_v4i1:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: shl v0.4h, v0.4h, #15
47 ; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
48 ; CHECK-NEXT: uminv h0, v0.4h
49 ; CHECK-NEXT: fmov w8, s0
50 ; CHECK-NEXT: and w0, w8, #0x1
51 ; CHECK-NEXT: ret
52 ;
53 ; GISEL-LABEL: test_redand_v4i1:
54 ; GISEL: // %bb.0:
55 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
56 ; GISEL-NEXT: mov h1, v0.h[1]
57 ; GISEL-NEXT: mov h2, v0.h[2]
58 ; GISEL-NEXT: mov h3, v0.h[3]
59 ; GISEL-NEXT: fmov w8, s0
60 ; GISEL-NEXT: fmov w9, s1
61 ; GISEL-NEXT: fmov w10, s2
62 ; GISEL-NEXT: fmov w11, s3
63 ; GISEL-NEXT: and w8, w8, w9
64 ; GISEL-NEXT: and w9, w10, w11
65 ; GISEL-NEXT: and w8, w8, w9
66 ; GISEL-NEXT: and w0, w8, #0x1
67 ; GISEL-NEXT: ret
68 %or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
69 ret i1 %or_result
70 }
72 define i1 @test_redand_v8i1(<8 x i1> %a) {
73 ; CHECK-LABEL: test_redand_v8i1:
74 ; CHECK: // %bb.0:
75 ; CHECK-NEXT: shl v0.8b, v0.8b, #7
76 ; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
77 ; CHECK-NEXT: uminv b0, v0.8b
78 ; CHECK-NEXT: fmov w8, s0
79 ; CHECK-NEXT: and w0, w8, #0x1
80 ; CHECK-NEXT: ret
81 ;
82 ; GISEL-LABEL: test_redand_v8i1:
83 ; GISEL: // %bb.0:
84 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
85 ; GISEL-NEXT: mov b1, v0.b[1]
86 ; GISEL-NEXT: mov b2, v0.b[2]
87 ; GISEL-NEXT: mov b3, v0.b[3]
88 ; GISEL-NEXT: mov b4, v0.b[4]
89 ; GISEL-NEXT: mov b5, v0.b[5]
90 ; GISEL-NEXT: mov b6, v0.b[6]
91 ; GISEL-NEXT: mov b7, v0.b[7]
92 ; GISEL-NEXT: fmov w8, s0
93 ; GISEL-NEXT: fmov w9, s1
94 ; GISEL-NEXT: fmov w10, s2
95 ; GISEL-NEXT: fmov w11, s3
96 ; GISEL-NEXT: fmov w12, s4
97 ; GISEL-NEXT: fmov w13, s5
98 ; GISEL-NEXT: fmov w14, s6
99 ; GISEL-NEXT: and w8, w8, w9
100 ; GISEL-NEXT: fmov w9, s7
101 ; GISEL-NEXT: and w10, w10, w11
102 ; GISEL-NEXT: and w11, w12, w13
103 ; GISEL-NEXT: and w8, w8, w10
104 ; GISEL-NEXT: and w9, w14, w9
105 ; GISEL-NEXT: and w9, w11, w9
106 ; GISEL-NEXT: and w8, w8, w9
107 ; GISEL-NEXT: and w0, w8, #0x1
108 ; GISEL-NEXT: ret
109 %or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
110 ret i1 %or_result
111 }
113 define i1 @test_redand_v16i1(<16 x i1> %a) {
114 ; CHECK-LABEL: test_redand_v16i1:
115 ; CHECK: // %bb.0:
116 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
117 ; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
118 ; CHECK-NEXT: uminv b0, v0.16b
119 ; CHECK-NEXT: fmov w8, s0
120 ; CHECK-NEXT: and w0, w8, #0x1
121 ; CHECK-NEXT: ret
122 ;
123 ; GISEL-LABEL: test_redand_v16i1:
124 ; GISEL: // %bb.0:
125 ; GISEL-NEXT: mov b1, v0.b[1]
126 ; GISEL-NEXT: mov b2, v0.b[2]
127 ; GISEL-NEXT: mov b3, v0.b[3]
128 ; GISEL-NEXT: mov b4, v0.b[4]
129 ; GISEL-NEXT: mov b5, v0.b[5]
130 ; GISEL-NEXT: mov b6, v0.b[6]
131 ; GISEL-NEXT: mov b7, v0.b[7]
132 ; GISEL-NEXT: fmov w8, s0
133 ; GISEL-NEXT: mov b16, v0.b[8]
134 ; GISEL-NEXT: mov b17, v0.b[9]
135 ; GISEL-NEXT: mov b18, v0.b[10]
136 ; GISEL-NEXT: mov b19, v0.b[11]
137 ; GISEL-NEXT: fmov w9, s1
138 ; GISEL-NEXT: fmov w10, s2
139 ; GISEL-NEXT: fmov w11, s3
140 ; GISEL-NEXT: fmov w12, s6
141 ; GISEL-NEXT: mov b20, v0.b[12]
142 ; GISEL-NEXT: mov b21, v0.b[13]
143 ; GISEL-NEXT: fmov w13, s7
144 ; GISEL-NEXT: mov b22, v0.b[14]
145 ; GISEL-NEXT: mov b23, v0.b[15]
146 ; GISEL-NEXT: and w8, w8, w9
147 ; GISEL-NEXT: and w9, w10, w11
148 ; GISEL-NEXT: fmov w10, s4
149 ; GISEL-NEXT: and w8, w8, w9
150 ; GISEL-NEXT: fmov w11, s5
151 ; GISEL-NEXT: fmov w14, s18
152 ; GISEL-NEXT: fmov w15, s19
153 ; GISEL-NEXT: fmov w16, s22
154 ; GISEL-NEXT: fmov w17, s23
155 ; GISEL-NEXT: and w10, w10, w11
156 ; GISEL-NEXT: and w11, w12, w13
157 ; GISEL-NEXT: fmov w12, s16
158 ; GISEL-NEXT: and w9, w10, w11
159 ; GISEL-NEXT: fmov w13, s17
160 ; GISEL-NEXT: and w8, w8, w9
161 ; GISEL-NEXT: and w12, w12, w13
162 ; GISEL-NEXT: and w13, w14, w15
163 ; GISEL-NEXT: fmov w14, s20
164 ; GISEL-NEXT: fmov w15, s21
165 ; GISEL-NEXT: and w10, w12, w13
166 ; GISEL-NEXT: and w14, w14, w15
167 ; GISEL-NEXT: and w15, w16, w17
168 ; GISEL-NEXT: and w11, w14, w15
169 ; GISEL-NEXT: and w9, w10, w11
170 ; GISEL-NEXT: and w8, w8, w9
171 ; GISEL-NEXT: and w0, w8, #0x1
172 ; GISEL-NEXT: ret
173 %or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
174 ret i1 %or_result
175 }
177 define <16 x i1> @test_redand_ins_v16i1(<16 x i1> %a) {
178 ; CHECK-LABEL: test_redand_ins_v16i1:
179 ; CHECK: // %bb.0:
180 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
181 ; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
182 ; CHECK-NEXT: uminv b0, v0.16b
183 ; CHECK-NEXT: ret
184 ;
185 ; GISEL-LABEL: test_redand_ins_v16i1:
186 ; GISEL: // %bb.0:
187 ; GISEL-NEXT: mov b1, v0.b[1]
188 ; GISEL-NEXT: mov b2, v0.b[2]
189 ; GISEL-NEXT: mov b3, v0.b[3]
190 ; GISEL-NEXT: mov b4, v0.b[4]
191 ; GISEL-NEXT: mov b5, v0.b[5]
192 ; GISEL-NEXT: mov b6, v0.b[6]
193 ; GISEL-NEXT: mov b7, v0.b[7]
194 ; GISEL-NEXT: fmov w8, s0
195 ; GISEL-NEXT: mov b16, v0.b[8]
196 ; GISEL-NEXT: mov b17, v0.b[9]
197 ; GISEL-NEXT: mov b18, v0.b[10]
198 ; GISEL-NEXT: mov b19, v0.b[11]
199 ; GISEL-NEXT: fmov w9, s1
200 ; GISEL-NEXT: fmov w10, s2
201 ; GISEL-NEXT: fmov w11, s3
202 ; GISEL-NEXT: fmov w12, s6
203 ; GISEL-NEXT: mov b20, v0.b[12]
204 ; GISEL-NEXT: mov b21, v0.b[13]
205 ; GISEL-NEXT: fmov w13, s7
206 ; GISEL-NEXT: mov b22, v0.b[14]
207 ; GISEL-NEXT: mov b23, v0.b[15]
208 ; GISEL-NEXT: and w8, w8, w9
209 ; GISEL-NEXT: and w9, w10, w11
210 ; GISEL-NEXT: fmov w10, s4
211 ; GISEL-NEXT: and w8, w8, w9
212 ; GISEL-NEXT: fmov w11, s5
213 ; GISEL-NEXT: fmov w14, s18
214 ; GISEL-NEXT: fmov w15, s19
215 ; GISEL-NEXT: fmov w16, s22
216 ; GISEL-NEXT: fmov w17, s23
217 ; GISEL-NEXT: and w10, w10, w11
218 ; GISEL-NEXT: and w11, w12, w13
219 ; GISEL-NEXT: fmov w12, s16
220 ; GISEL-NEXT: and w9, w10, w11
221 ; GISEL-NEXT: fmov w13, s17
222 ; GISEL-NEXT: and w8, w8, w9
223 ; GISEL-NEXT: and w12, w12, w13
224 ; GISEL-NEXT: and w13, w14, w15
225 ; GISEL-NEXT: fmov w14, s20
226 ; GISEL-NEXT: fmov w15, s21
227 ; GISEL-NEXT: and w10, w12, w13
228 ; GISEL-NEXT: and w14, w14, w15
229 ; GISEL-NEXT: and w15, w16, w17
230 ; GISEL-NEXT: and w11, w14, w15
231 ; GISEL-NEXT: and w9, w10, w11
232 ; GISEL-NEXT: and w8, w8, w9
233 ; GISEL-NEXT: fmov s0, w8
234 ; GISEL-NEXT: ret
235 %and_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
236 %ins = insertelement <16 x i1> poison, i1 %and_result, i64 0
237 ret <16 x i1> %ins
238 }
240 define i8 @test_redand_v1i8(<1 x i8> %a) {
241 ; CHECK-LABEL: test_redand_v1i8:
242 ; CHECK: // %bb.0:
243 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
244 ; CHECK-NEXT: umov w0, v0.b[0]
245 ; CHECK-NEXT: ret
246 ;
247 ; GISEL-LABEL: test_redand_v1i8:
248 ; GISEL: // %bb.0:
249 ; GISEL-NEXT: fmov x0, d0
250 ; GISEL-NEXT: // kill: def $w0 killed $w0 killed $x0
251 ; GISEL-NEXT: ret
252 %and_result = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
253 ret i8 %and_result
254 }
256 define i8 @test_redand_v3i8(<3 x i8> %a) {
257 ; CHECK-LABEL: test_redand_v3i8:
258 ; CHECK: // %bb.0:
259 ; CHECK-NEXT: movi d0, #0xff00ff00ff00ff
260 ; CHECK-NEXT: mov v0.h[0], w0
261 ; CHECK-NEXT: mov v0.h[1], w1
262 ; CHECK-NEXT: mov v0.h[2], w2
263 ; CHECK-NEXT: fmov x8, d0
264 ; CHECK-NEXT: and x8, x8, x8, lsr #32
265 ; CHECK-NEXT: lsr x9, x8, #16
266 ; CHECK-NEXT: and w0, w8, w9
267 ; CHECK-NEXT: ret
268 ;
269 ; GISEL-LABEL: test_redand_v3i8:
270 ; GISEL: // %bb.0:
271 ; GISEL-NEXT: and w8, w0, w1
272 ; GISEL-NEXT: and w0, w8, w2
273 ; GISEL-NEXT: ret
274 %and_result = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
275 ret i8 %and_result
276 }
278 define i8 @test_redand_v4i8(<4 x i8> %a) {
279 ; CHECK-LABEL: test_redand_v4i8:
280 ; CHECK: // %bb.0:
281 ; CHECK-NEXT: fmov x8, d0
282 ; CHECK-NEXT: and x8, x8, x8, lsr #32
283 ; CHECK-NEXT: lsr x9, x8, #16
284 ; CHECK-NEXT: and w0, w8, w9
285 ; CHECK-NEXT: ret
286 ;
287 ; GISEL-LABEL: test_redand_v4i8:
288 ; GISEL: // %bb.0:
289 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
290 ; GISEL-NEXT: mov h1, v0.h[1]
291 ; GISEL-NEXT: mov h2, v0.h[2]
292 ; GISEL-NEXT: mov h3, v0.h[3]
293 ; GISEL-NEXT: fmov w8, s0
294 ; GISEL-NEXT: fmov w9, s1
295 ; GISEL-NEXT: fmov w10, s2
296 ; GISEL-NEXT: fmov w11, s3
297 ; GISEL-NEXT: and w8, w8, w9
298 ; GISEL-NEXT: and w9, w10, w11
299 ; GISEL-NEXT: and w0, w8, w9
300 ; GISEL-NEXT: ret
301 %and_result = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %a)
302 ret i8 %and_result
303 }
305 define i8 @test_redand_v8i8(<8 x i8> %a) {
306 ; CHECK-LABEL: test_redand_v8i8:
307 ; CHECK: // %bb.0:
308 ; CHECK-NEXT: fmov x8, d0
309 ; CHECK-NEXT: and x8, x8, x8, lsr #32
310 ; CHECK-NEXT: and x8, x8, x8, lsr #16
311 ; CHECK-NEXT: lsr x9, x8, #8
312 ; CHECK-NEXT: and w0, w8, w9
313 ; CHECK-NEXT: ret
314 ;
315 ; GISEL-LABEL: test_redand_v8i8:
316 ; GISEL: // %bb.0:
317 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
318 ; GISEL-NEXT: mov b1, v0.b[1]
319 ; GISEL-NEXT: mov b2, v0.b[2]
320 ; GISEL-NEXT: mov b3, v0.b[3]
321 ; GISEL-NEXT: mov b4, v0.b[4]
322 ; GISEL-NEXT: mov b5, v0.b[5]
323 ; GISEL-NEXT: mov b6, v0.b[6]
324 ; GISEL-NEXT: mov b7, v0.b[7]
325 ; GISEL-NEXT: fmov w8, s0
326 ; GISEL-NEXT: fmov w9, s1
327 ; GISEL-NEXT: fmov w10, s2
328 ; GISEL-NEXT: fmov w11, s3
329 ; GISEL-NEXT: fmov w12, s4
330 ; GISEL-NEXT: fmov w13, s5
331 ; GISEL-NEXT: fmov w14, s6
332 ; GISEL-NEXT: and w8, w8, w9
333 ; GISEL-NEXT: fmov w9, s7
334 ; GISEL-NEXT: and w10, w10, w11
335 ; GISEL-NEXT: and w11, w12, w13
336 ; GISEL-NEXT: and w8, w8, w10
337 ; GISEL-NEXT: and w9, w14, w9
338 ; GISEL-NEXT: and w9, w11, w9
339 ; GISEL-NEXT: and w0, w8, w9
340 ; GISEL-NEXT: ret
341 %and_result = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a)
342 ret i8 %and_result
343 }
345 define i8 @test_redand_v16i8(<16 x i8> %a) {
346 ; CHECK-LABEL: test_redand_v16i8:
347 ; CHECK: // %bb.0:
348 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
349 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
350 ; CHECK-NEXT: fmov x8, d0
351 ; CHECK-NEXT: and x8, x8, x8, lsr #32
352 ; CHECK-NEXT: and x8, x8, x8, lsr #16
353 ; CHECK-NEXT: lsr x9, x8, #8
354 ; CHECK-NEXT: and w0, w8, w9
355 ; CHECK-NEXT: ret
356 ;
357 ; GISEL-LABEL: test_redand_v16i8:
358 ; GISEL: // %bb.0:
359 ; GISEL-NEXT: mov d1, v0.d[1]
360 ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
361 ; GISEL-NEXT: mov b1, v0.b[1]
362 ; GISEL-NEXT: mov b2, v0.b[2]
363 ; GISEL-NEXT: mov b3, v0.b[3]
364 ; GISEL-NEXT: mov b4, v0.b[4]
365 ; GISEL-NEXT: mov b5, v0.b[5]
366 ; GISEL-NEXT: mov b6, v0.b[6]
367 ; GISEL-NEXT: mov b7, v0.b[7]
368 ; GISEL-NEXT: fmov w8, s0
369 ; GISEL-NEXT: fmov w9, s1
370 ; GISEL-NEXT: fmov w10, s2
371 ; GISEL-NEXT: fmov w11, s3
372 ; GISEL-NEXT: fmov w12, s4
373 ; GISEL-NEXT: fmov w13, s5
374 ; GISEL-NEXT: fmov w14, s6
375 ; GISEL-NEXT: and w8, w8, w9
376 ; GISEL-NEXT: fmov w9, s7
377 ; GISEL-NEXT: and w10, w10, w11
378 ; GISEL-NEXT: and w11, w12, w13
379 ; GISEL-NEXT: and w8, w8, w10
380 ; GISEL-NEXT: and w9, w14, w9
381 ; GISEL-NEXT: and w9, w11, w9
382 ; GISEL-NEXT: and w0, w8, w9
383 ; GISEL-NEXT: ret
384 %and_result = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a)
385 ret i8 %and_result
386 }
388 define i8 @test_redand_v32i8(<32 x i8> %a) {
389 ; CHECK-LABEL: test_redand_v32i8:
390 ; CHECK: // %bb.0:
391 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
392 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
393 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
394 ; CHECK-NEXT: fmov x8, d0
395 ; CHECK-NEXT: and x8, x8, x8, lsr #32
396 ; CHECK-NEXT: and x8, x8, x8, lsr #16
397 ; CHECK-NEXT: lsr x9, x8, #8
398 ; CHECK-NEXT: and w0, w8, w9
399 ; CHECK-NEXT: ret
400 ;
401 ; GISEL-LABEL: test_redand_v32i8:
402 ; GISEL: // %bb.0:
403 ; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
404 ; GISEL-NEXT: mov d1, v0.d[1]
405 ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
406 ; GISEL-NEXT: mov b1, v0.b[1]
407 ; GISEL-NEXT: mov b2, v0.b[2]
408 ; GISEL-NEXT: mov b3, v0.b[3]
409 ; GISEL-NEXT: mov b4, v0.b[4]
410 ; GISEL-NEXT: mov b5, v0.b[5]
411 ; GISEL-NEXT: mov b6, v0.b[6]
412 ; GISEL-NEXT: mov b7, v0.b[7]
413 ; GISEL-NEXT: fmov w8, s0
414 ; GISEL-NEXT: fmov w9, s1
415 ; GISEL-NEXT: fmov w10, s2
416 ; GISEL-NEXT: fmov w11, s3
417 ; GISEL-NEXT: fmov w12, s4
418 ; GISEL-NEXT: fmov w13, s5
419 ; GISEL-NEXT: fmov w14, s6
420 ; GISEL-NEXT: and w8, w8, w9
421 ; GISEL-NEXT: fmov w9, s7
422 ; GISEL-NEXT: and w10, w10, w11
423 ; GISEL-NEXT: and w11, w12, w13
424 ; GISEL-NEXT: and w8, w8, w10
425 ; GISEL-NEXT: and w9, w14, w9
426 ; GISEL-NEXT: and w9, w11, w9
427 ; GISEL-NEXT: and w0, w8, w9
428 ; GISEL-NEXT: ret
429 %and_result = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %a)
430 ret i8 %and_result
431 }
433 define i16 @test_redand_v4i16(<4 x i16> %a) {
434 ; CHECK-LABEL: test_redand_v4i16:
435 ; CHECK: // %bb.0:
436 ; CHECK-NEXT: fmov x8, d0
437 ; CHECK-NEXT: and x8, x8, x8, lsr #32
438 ; CHECK-NEXT: lsr x9, x8, #16
439 ; CHECK-NEXT: and w0, w8, w9
440 ; CHECK-NEXT: ret
441 ;
442 ; GISEL-LABEL: test_redand_v4i16:
443 ; GISEL: // %bb.0:
444 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
445 ; GISEL-NEXT: mov h1, v0.h[1]
446 ; GISEL-NEXT: mov h2, v0.h[2]
447 ; GISEL-NEXT: mov h3, v0.h[3]
448 ; GISEL-NEXT: fmov w8, s0
449 ; GISEL-NEXT: fmov w9, s1
450 ; GISEL-NEXT: fmov w10, s2
451 ; GISEL-NEXT: fmov w11, s3
452 ; GISEL-NEXT: and w8, w8, w9
453 ; GISEL-NEXT: and w9, w10, w11
454 ; GISEL-NEXT: and w0, w8, w9
455 ; GISEL-NEXT: ret
456 %and_result = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a)
457 ret i16 %and_result
458 }
460 define i16 @test_redand_v8i16(<8 x i16> %a) {
461 ; CHECK-LABEL: test_redand_v8i16:
462 ; CHECK: // %bb.0:
463 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
464 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
465 ; CHECK-NEXT: fmov x8, d0
466 ; CHECK-NEXT: and x8, x8, x8, lsr #32
467 ; CHECK-NEXT: lsr x9, x8, #16
468 ; CHECK-NEXT: and w0, w8, w9
469 ; CHECK-NEXT: ret
470 ;
471 ; GISEL-LABEL: test_redand_v8i16:
472 ; GISEL: // %bb.0:
473 ; GISEL-NEXT: mov d1, v0.d[1]
474 ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
475 ; GISEL-NEXT: mov h1, v0.h[1]
476 ; GISEL-NEXT: mov h2, v0.h[2]
477 ; GISEL-NEXT: mov h3, v0.h[3]
478 ; GISEL-NEXT: fmov w8, s0
479 ; GISEL-NEXT: fmov w9, s1
480 ; GISEL-NEXT: fmov w10, s2
481 ; GISEL-NEXT: fmov w11, s3
482 ; GISEL-NEXT: and w8, w8, w9
483 ; GISEL-NEXT: and w9, w10, w11
484 ; GISEL-NEXT: and w0, w8, w9
485 ; GISEL-NEXT: ret
486 %and_result = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a)
487 ret i16 %and_result
488 }
490 define i16 @test_redand_v16i16(<16 x i16> %a) {
491 ; CHECK-LABEL: test_redand_v16i16:
492 ; CHECK: // %bb.0:
493 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
494 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
495 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
496 ; CHECK-NEXT: fmov x8, d0
497 ; CHECK-NEXT: and x8, x8, x8, lsr #32
498 ; CHECK-NEXT: lsr x9, x8, #16
499 ; CHECK-NEXT: and w0, w8, w9
500 ; CHECK-NEXT: ret
501 ;
502 ; GISEL-LABEL: test_redand_v16i16:
503 ; GISEL: // %bb.0:
504 ; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
505 ; GISEL-NEXT: mov d1, v0.d[1]
506 ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
507 ; GISEL-NEXT: mov h1, v0.h[1]
508 ; GISEL-NEXT: mov h2, v0.h[2]
509 ; GISEL-NEXT: mov h3, v0.h[3]
510 ; GISEL-NEXT: fmov w8, s0
511 ; GISEL-NEXT: fmov w9, s1
512 ; GISEL-NEXT: fmov w10, s2
513 ; GISEL-NEXT: fmov w11, s3
514 ; GISEL-NEXT: and w8, w8, w9
515 ; GISEL-NEXT: and w9, w10, w11
516 ; GISEL-NEXT: and w0, w8, w9
517 ; GISEL-NEXT: ret
518 %and_result = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %a)
519 ret i16 %and_result
520 }
522 define i32 @test_redand_v2i32(<2 x i32> %a) {
523 ; CHECK-LABEL: test_redand_v2i32:
524 ; CHECK: // %bb.0:
525 ; CHECK-NEXT: fmov x8, d0
526 ; CHECK-NEXT: lsr x9, x8, #32
527 ; CHECK-NEXT: and w0, w8, w9
528 ; CHECK-NEXT: ret
529 ;
530 ; GISEL-LABEL: test_redand_v2i32:
531 ; GISEL: // %bb.0:
532 ; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
533 ; GISEL-NEXT: mov s1, v0.s[1]
534 ; GISEL-NEXT: fmov w8, s0
535 ; GISEL-NEXT: fmov w9, s1
536 ; GISEL-NEXT: and w0, w8, w9
537 ; GISEL-NEXT: ret
538 %and_result = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)
539 ret i32 %and_result
540 }
542 define i32 @test_redand_v4i32(<4 x i32> %a) {
543 ; CHECK-LABEL: test_redand_v4i32:
544 ; CHECK: // %bb.0:
545 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
546 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
547 ; CHECK-NEXT: fmov x8, d0
548 ; CHECK-NEXT: lsr x9, x8, #32
549 ; CHECK-NEXT: and w0, w8, w9
550 ; CHECK-NEXT: ret
551 ;
552 ; GISEL-LABEL: test_redand_v4i32:
553 ; GISEL: // %bb.0:
554 ; GISEL-NEXT: mov d1, v0.d[1]
555 ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
556 ; GISEL-NEXT: mov s1, v0.s[1]
557 ; GISEL-NEXT: fmov w8, s0
558 ; GISEL-NEXT: fmov w9, s1
559 ; GISEL-NEXT: and w0, w8, w9
560 ; GISEL-NEXT: ret
561 %and_result = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
562 ret i32 %and_result
563 }
565 define i32 @test_redand_v8i32(<8 x i32> %a) {
566 ; CHECK-LABEL: test_redand_v8i32:
567 ; CHECK: // %bb.0:
568 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
569 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
570 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
571 ; CHECK-NEXT: fmov x8, d0
572 ; CHECK-NEXT: lsr x9, x8, #32
573 ; CHECK-NEXT: and w0, w8, w9
574 ; CHECK-NEXT: ret
575 ;
576 ; GISEL-LABEL: test_redand_v8i32:
577 ; GISEL: // %bb.0:
578 ; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
579 ; GISEL-NEXT: mov d1, v0.d[1]
580 ; GISEL-NEXT: and v0.8b, v0.8b, v1.8b
581 ; GISEL-NEXT: mov s1, v0.s[1]
582 ; GISEL-NEXT: fmov w8, s0
583 ; GISEL-NEXT: fmov w9, s1
584 ; GISEL-NEXT: and w0, w8, w9
585 ; GISEL-NEXT: ret
586 %and_result = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %a)
587 ret i32 %and_result
588 }
590 define i64 @test_redand_v2i64(<2 x i64> %a) {
591 ; CHECK-LABEL: test_redand_v2i64:
592 ; CHECK: // %bb.0:
593 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
594 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
595 ; CHECK-NEXT: fmov x0, d0
596 ; CHECK-NEXT: ret
597 ;
598 ; GISEL-LABEL: test_redand_v2i64:
599 ; GISEL: // %bb.0:
600 ; GISEL-NEXT: mov d1, v0.d[1]
601 ; GISEL-NEXT: fmov x8, d0
602 ; GISEL-NEXT: fmov x9, d1
603 ; GISEL-NEXT: and x0, x8, x9
604 ; GISEL-NEXT: ret
605 %and_result = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a)
606 ret i64 %and_result
607 }
609 define i64 @test_redand_v4i64(<4 x i64> %a) {
610 ; CHECK-LABEL: test_redand_v4i64:
611 ; CHECK: // %bb.0:
612 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
613 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
614 ; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
615 ; CHECK-NEXT: fmov x0, d0
616 ; CHECK-NEXT: ret
617 ;
618 ; GISEL-LABEL: test_redand_v4i64:
619 ; GISEL: // %bb.0:
620 ; GISEL-NEXT: and v0.16b, v0.16b, v1.16b
621 ; GISEL-NEXT: mov d1, v0.d[1]
622 ; GISEL-NEXT: fmov x8, d0
623 ; GISEL-NEXT: fmov x9, d1
624 ; GISEL-NEXT: and x0, x8, x9
625 ; GISEL-NEXT: ret
626 %and_result = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %a)
627 ret i64 %and_result
628 }
630 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
631 declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
632 declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
633 declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
634 declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
635 declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
636 declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
637 declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
638 declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
639 declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)
640 declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
641 declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)
642 declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)
643 declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8>)
644 declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8>)
645 declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
646 declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
647 declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
648 declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)