| blob | 3adf48e84b44c1e2d6935097d2262094289f2f49 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-none-elf %s -o - | FileCheck %s
4 define i32 @xori64i32(i64 %a) {
5 ; CHECK-LABEL: xori64i32:
6 ; CHECK: // %bb.0:
7 ; CHECK-NEXT: asr x8, x0, #63
8 ; CHECK-NEXT: eor w0, w8, #0x7fffffff
9 ; CHECK-NEXT: ret
10 %shr4 = ashr i64 %a, 63
11 %conv5 = trunc i64 %shr4 to i32
12 %xor = xor i32 %conv5, 2147483647
13 ret i32 %xor
14 }
16 define i64 @selecti64i64(i64 %a) {
17 ; CHECK-LABEL: selecti64i64:
18 ; CHECK: // %bb.0:
19 ; CHECK-NEXT: asr x8, x0, #63
20 ; CHECK-NEXT: eor x0, x8, #0x7fffffff
21 ; CHECK-NEXT: ret
22 %c = icmp sgt i64 %a, -1
23 %s = select i1 %c, i64 2147483647, i64 -2147483648
24 ret i64 %s
25 }
27 define i32 @selecti64i32(i64 %a) {
28 ; CHECK-LABEL: selecti64i32:
29 ; CHECK: // %bb.0:
30 ; CHECK-NEXT: asr x8, x0, #63
31 ; CHECK-NEXT: eor w0, w8, #0x7fffffff
32 ; CHECK-NEXT: ret
33 %c = icmp sgt i64 %a, -1
34 %s = select i1 %c, i32 2147483647, i32 -2147483648
35 ret i32 %s
36 }
38 define i64 @selecti32i64(i32 %a) {
39 ; CHECK-LABEL: selecti32i64:
40 ; CHECK: // %bb.0:
41 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
42 ; CHECK-NEXT: sbfx x8, x0, #31, #1
43 ; CHECK-NEXT: eor x0, x8, #0x7fffffff
44 ; CHECK-NEXT: ret
45 %c = icmp sgt i32 %a, -1
46 %s = select i1 %c, i64 2147483647, i64 -2147483648
47 ret i64 %s
48 }
52 define i8 @xori32i8(i32 %a) {
53 ; CHECK-LABEL: xori32i8:
54 ; CHECK: // %bb.0:
55 ; CHECK-NEXT: mov w8, #84 // =0x54
56 ; CHECK-NEXT: eor w0, w8, w0, asr #31
57 ; CHECK-NEXT: ret
58 %shr4 = ashr i32 %a, 31
59 %conv5 = trunc i32 %shr4 to i8
60 %xor = xor i8 %conv5, 84
61 ret i8 %xor
62 }
64 define i32 @selecti32i32(i32 %a) {
65 ; CHECK-LABEL: selecti32i32:
66 ; CHECK: // %bb.0:
67 ; CHECK-NEXT: mov w8, #84 // =0x54
68 ; CHECK-NEXT: eor w0, w8, w0, asr #31
69 ; CHECK-NEXT: ret
70 %c = icmp sgt i32 %a, -1
71 %s = select i1 %c, i32 84, i32 -85
72 ret i32 %s
73 }
75 define i8 @selecti32i8(i32 %a) {
76 ; CHECK-LABEL: selecti32i8:
77 ; CHECK: // %bb.0:
78 ; CHECK-NEXT: mov w8, #84 // =0x54
79 ; CHECK-NEXT: eor w0, w8, w0, asr #31
80 ; CHECK-NEXT: ret
81 %c = icmp sgt i32 %a, -1
82 %s = select i1 %c, i8 84, i8 -85
83 ret i8 %s
84 }
86 define i32 @selecti8i32(i8 %a) {
87 ; CHECK-LABEL: selecti8i32:
88 ; CHECK: // %bb.0:
89 ; CHECK-NEXT: sxtb w8, w0
90 ; CHECK-NEXT: mov w9, #84 // =0x54
91 ; CHECK-NEXT: eor w0, w9, w8, asr #7
92 ; CHECK-NEXT: ret
93 %c = icmp sgt i8 %a, -1
94 %s = select i1 %c, i32 84, i32 -85
95 ret i32 %s
96 }
98 define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
99 ; CHECK-LABEL: icmpasreq:
100 ; CHECK: // %bb.0:
101 ; CHECK-NEXT: cmp w0, #0
102 ; CHECK-NEXT: csel w0, w1, w2, lt
103 ; CHECK-NEXT: ret
104 %sh = ashr i32 %input, 31
105 %c = icmp eq i32 %sh, -1
106 %s = select i1 %c, i32 %a, i32 %b
107 ret i32 %s
108 }
110 define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
111 ; CHECK-LABEL: icmpasrne:
112 ; CHECK: // %bb.0:
113 ; CHECK-NEXT: cmp w0, #0
114 ; CHECK-NEXT: csel w0, w1, w2, ge
115 ; CHECK-NEXT: ret
116 %sh = ashr i32 %input, 31
117 %c = icmp ne i32 %sh, -1
118 %s = select i1 %c, i32 %a, i32 %b
119 ret i32 %s
120 }
122 define i32 @selecti32i32_0(i32 %a) {
123 ; CHECK-LABEL: selecti32i32_0:
124 ; CHECK: // %bb.0:
125 ; CHECK-NEXT: asr w0, w0, #31
126 ; CHECK-NEXT: ret
127 %c = icmp sgt i32 %a, -1
128 %s = select i1 %c, i32 0, i32 -1
129 ret i32 %s
130 }
132 define i32 @selecti32i32_m1(i32 %a) {
133 ; CHECK-LABEL: selecti32i32_m1:
134 ; CHECK: // %bb.0:
135 ; CHECK-NEXT: mvn w8, w0
136 ; CHECK-NEXT: asr w0, w8, #31
137 ; CHECK-NEXT: ret
138 %c = icmp sgt i32 %a, -1
139 %s = select i1 %c, i32 -1, i32 0
140 ret i32 %s
141 }
143 define i32 @selecti32i32_1(i32 %a) {
144 ; CHECK-LABEL: selecti32i32_1:
145 ; CHECK: // %bb.0:
146 ; CHECK-NEXT: asr w8, w0, #31
147 ; CHECK-NEXT: eor w0, w8, #0x1
148 ; CHECK-NEXT: ret
149 %c = icmp sgt i32 %a, -1
150 %s = select i1 %c, i32 1, i32 -2
151 ret i32 %s
152 }
154 define i32 @selecti32i32_sge(i32 %a) {
155 ; CHECK-LABEL: selecti32i32_sge:
156 ; CHECK: // %bb.0:
157 ; CHECK-NEXT: asr w8, w0, #31
158 ; CHECK-NEXT: eor w0, w8, #0xc
159 ; CHECK-NEXT: ret
160 %c = icmp sge i32 %a, 0
161 %s = select i1 %c, i32 12, i32 -13
162 ret i32 %s
163 }
165 define i32 @selecti32i32_slt(i32 %a) {
166 ; CHECK-LABEL: selecti32i32_slt:
167 ; CHECK: // %bb.0:
168 ; CHECK-NEXT: asr w8, w0, #31
169 ; CHECK-NEXT: eor w0, w8, #0xc
170 ; CHECK-NEXT: ret
171 %c = icmp slt i32 %a, 0
172 %s = select i1 %c, i32 -13, i32 12
173 ret i32 %s
174 }
176 define i32 @selecti32i32_sle(i32 %a) {
177 ; CHECK-LABEL: selecti32i32_sle:
178 ; CHECK: // %bb.0:
179 ; CHECK-NEXT: asr w8, w0, #31
180 ; CHECK-NEXT: eor w0, w8, #0xc
181 ; CHECK-NEXT: ret
182 %c = icmp sle i32 %a, -1
183 %s = select i1 %c, i32 -13, i32 12
184 ret i32 %s
185 }
187 define i32 @selecti32i32_sgt(i32 %a) {
188 ; CHECK-LABEL: selecti32i32_sgt:
189 ; CHECK: // %bb.0:
190 ; CHECK-NEXT: asr w8, w0, #31
191 ; CHECK-NEXT: eor w0, w8, #0xc
192 ; CHECK-NEXT: ret
193 %c = icmp sle i32 %a, -1
194 %s = select i1 %c, i32 -13, i32 12
195 ret i32 %s
196 }
198 define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
199 ; CHECK-LABEL: oneusecmp:
200 ; CHECK: // %bb.0:
201 ; CHECK-NEXT: asr w8, w0, #31
202 ; CHECK-NEXT: cmp w0, #0
203 ; CHECK-NEXT: csel w9, w2, w1, lt
204 ; CHECK-NEXT: eor w8, w8, #0x7f
205 ; CHECK-NEXT: add w0, w8, w9
206 ; CHECK-NEXT: ret
207 %c = icmp sle i32 %a, -1
208 %s = select i1 %c, i32 -128, i32 127
209 %s2 = select i1 %c, i32 %d, i32 %b
210 %x = add i32 %s, %s2
211 ret i32 %x
212 }