| blob | 2dd06e08d16b63116c772ba46e7ce3b7cb7c0e48 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
3 ; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
4 ; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
6 target triple = "aarch64-unknown-linux-gnu"
8 ;
9 ; insertelement
10 ;
12 ; Don't use SVE for 64-bit vectors.
13 define <4 x half> @insertelement_v4f16(<4 x half> %op1) vscale_range(2,0) #0 {
14 ; CHECK-LABEL: insertelement_v4f16:
15 ; CHECK: // %bb.0:
16 ; CHECK-NEXT: fmov h1, #5.00000000
17 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
18 ; CHECK-NEXT: mov v0.h[3], v1.h[0]
19 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
20 ; CHECK-NEXT: ret
21 %r = insertelement <4 x half> %op1, half 5.0, i64 3
22 ret <4 x half> %r
23 }
25 ; Don't use SVE for 128-bit vectors.
26 define <8 x half> @insertelement_v8f16(<8 x half> %op1) vscale_range(2,0) #0 {
27 ; CHECK-LABEL: insertelement_v8f16:
28 ; CHECK: // %bb.0:
29 ; CHECK-NEXT: fmov h1, #5.00000000
30 ; CHECK-NEXT: mov v0.h[7], v1.h[0]
31 ; CHECK-NEXT: ret
32 %r = insertelement <8 x half> %op1, half 5.0, i64 7
33 ret <8 x half> %r
34 }
36 define <16 x half> @insertelement_v16f16(ptr %a) vscale_range(2,0) #0 {
37 ; CHECK-LABEL: insertelement_v16f16:
38 ; CHECK: // %bb.0:
39 ; CHECK-NEXT: ptrue p0.h, vl16
40 ; CHECK-NEXT: mov w9, #15 // =0xf
41 ; CHECK-NEXT: index z0.h, #0, #1
42 ; CHECK-NEXT: ptrue p1.h
43 ; CHECK-NEXT: mov z1.h, w9
44 ; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0]
45 ; CHECK-NEXT: cmpeq p1.h, p1/z, z0.h, z1.h
46 ; CHECK-NEXT: fmov h0, #5.00000000
47 ; CHECK-NEXT: mov z2.h, p1/m, h0
48 ; CHECK-NEXT: st1h { z2.h }, p0, [x8]
49 ; CHECK-NEXT: ret
50 %op1 = load <16 x half>, ptr %a
51 %r = insertelement <16 x half> %op1, half 5.0, i64 15
52 ret <16 x half> %r
53 }
55 define <32 x half> @insertelement_v32f16(ptr %a) #0 {
56 ; VBITS_GE_256-LABEL: insertelement_v32f16:
57 ; VBITS_GE_256: // %bb.0:
58 ; VBITS_GE_256-NEXT: ptrue p0.h, vl16
59 ; VBITS_GE_256-NEXT: mov w9, #15 // =0xf
60 ; VBITS_GE_256-NEXT: index z0.h, #0, #1
61 ; VBITS_GE_256-NEXT: ptrue p1.h
62 ; VBITS_GE_256-NEXT: mov z1.h, w9
63 ; VBITS_GE_256-NEXT: mov x9, #16 // =0x10
64 ; VBITS_GE_256-NEXT: fmov h2, #5.00000000
65 ; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x0, x9, lsl #1]
66 ; VBITS_GE_256-NEXT: cmpeq p1.h, p1/z, z0.h, z1.h
67 ; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0]
68 ; VBITS_GE_256-NEXT: mov z3.h, p1/m, h2
69 ; VBITS_GE_256-NEXT: st1h { z3.h }, p0, [x8, x9, lsl #1]
70 ; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x8]
71 ; VBITS_GE_256-NEXT: ret
72 ;
73 ; VBITS_GE_512-LABEL: insertelement_v32f16:
74 ; VBITS_GE_512: // %bb.0:
75 ; VBITS_GE_512-NEXT: ptrue p0.h, vl32
76 ; VBITS_GE_512-NEXT: mov w9, #31 // =0x1f
77 ; VBITS_GE_512-NEXT: index z0.h, #0, #1
78 ; VBITS_GE_512-NEXT: ptrue p1.h
79 ; VBITS_GE_512-NEXT: mov z1.h, w9
80 ; VBITS_GE_512-NEXT: ld1h { z2.h }, p0/z, [x0]
81 ; VBITS_GE_512-NEXT: cmpeq p1.h, p1/z, z0.h, z1.h
82 ; VBITS_GE_512-NEXT: fmov h0, #5.00000000
83 ; VBITS_GE_512-NEXT: mov z2.h, p1/m, h0
84 ; VBITS_GE_512-NEXT: st1h { z2.h }, p0, [x8]
85 ; VBITS_GE_512-NEXT: ret
86 %op1 = load <32 x half>, ptr %a
87 %r = insertelement <32 x half> %op1, half 5.0, i64 31
88 ret <32 x half> %r
89 }
91 define <64 x half> @insertelement_v64f16(ptr %a) vscale_range(8,0) #0 {
92 ; CHECK-LABEL: insertelement_v64f16:
93 ; CHECK: // %bb.0:
94 ; CHECK-NEXT: ptrue p0.h, vl64
95 ; CHECK-NEXT: mov w9, #63 // =0x3f
96 ; CHECK-NEXT: index z0.h, #0, #1
97 ; CHECK-NEXT: ptrue p1.h
98 ; CHECK-NEXT: mov z1.h, w9
99 ; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0]
100 ; CHECK-NEXT: cmpeq p1.h, p1/z, z0.h, z1.h
101 ; CHECK-NEXT: fmov h0, #5.00000000
102 ; CHECK-NEXT: mov z2.h, p1/m, h0
103 ; CHECK-NEXT: st1h { z2.h }, p0, [x8]
104 ; CHECK-NEXT: ret
105 %op1 = load <64 x half>, ptr %a
106 %r = insertelement <64 x half> %op1, half 5.0, i64 63
107 ret <64 x half> %r
108 }
110 define <128 x half> @insertelement_v128f16(ptr %a) vscale_range(16,0) #0 {
111 ; CHECK-LABEL: insertelement_v128f16:
112 ; CHECK: // %bb.0:
113 ; CHECK-NEXT: ptrue p0.h, vl128
114 ; CHECK-NEXT: mov w9, #127 // =0x7f
115 ; CHECK-NEXT: index z0.h, #0, #1
116 ; CHECK-NEXT: ptrue p1.h
117 ; CHECK-NEXT: mov z1.h, w9
118 ; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0]
119 ; CHECK-NEXT: cmpeq p1.h, p1/z, z0.h, z1.h
120 ; CHECK-NEXT: fmov h0, #5.00000000
121 ; CHECK-NEXT: mov z2.h, p1/m, h0
122 ; CHECK-NEXT: st1h { z2.h }, p0, [x8]
123 ; CHECK-NEXT: ret
124 %op1 = load <128 x half>, ptr %a
125 %r = insertelement <128 x half> %op1, half 5.0, i64 127
126 ret <128 x half> %r
127 }
129 ; Don't use SVE for 64-bit vectors.
130 define <2 x float> @insertelement_v2f32(<2 x float> %op1) vscale_range(2,0) #0 {
131 ; CHECK-LABEL: insertelement_v2f32:
132 ; CHECK: // %bb.0:
133 ; CHECK-NEXT: fmov s1, #5.00000000
134 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
135 ; CHECK-NEXT: mov v0.s[1], v1.s[0]
136 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
137 ; CHECK-NEXT: ret
138 %r = insertelement <2 x float> %op1, float 5.0, i64 1
139 ret <2 x float> %r
140 }
142 ; Don't use SVE for 128-bit vectors.
143 define <4 x float> @insertelement_v4f32(<4 x float> %op1) vscale_range(2,0) #0 {
144 ; CHECK-LABEL: insertelement_v4f32:
145 ; CHECK: // %bb.0:
146 ; CHECK-NEXT: fmov s1, #5.00000000
147 ; CHECK-NEXT: mov v0.s[3], v1.s[0]
148 ; CHECK-NEXT: ret
149 %r = insertelement <4 x float> %op1, float 5.0, i64 3
150 ret <4 x float> %r
151 }
153 define <8 x float> @insertelement_v8f32(ptr %a) vscale_range(2,0) #0 {
154 ; CHECK-LABEL: insertelement_v8f32:
155 ; CHECK: // %bb.0:
156 ; CHECK-NEXT: ptrue p0.s, vl8
157 ; CHECK-NEXT: mov w9, #7 // =0x7
158 ; CHECK-NEXT: index z0.s, #0, #1
159 ; CHECK-NEXT: ptrue p1.s
160 ; CHECK-NEXT: mov z1.s, w9
161 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]
162 ; CHECK-NEXT: cmpeq p1.s, p1/z, z0.s, z1.s
163 ; CHECK-NEXT: fmov s0, #5.00000000
164 ; CHECK-NEXT: mov z2.s, p1/m, s0
165 ; CHECK-NEXT: st1w { z2.s }, p0, [x8]
166 ; CHECK-NEXT: ret
167 %op1 = load <8 x float>, ptr %a
168 %r = insertelement <8 x float> %op1, float 5.0, i64 7
169 ret <8 x float> %r
170 }
172 define <16 x float> @insertelement_v16f32(ptr %a) #0 {
173 ; VBITS_GE_256-LABEL: insertelement_v16f32:
174 ; VBITS_GE_256: // %bb.0:
175 ; VBITS_GE_256-NEXT: ptrue p0.s, vl8
176 ; VBITS_GE_256-NEXT: mov w9, #7 // =0x7
177 ; VBITS_GE_256-NEXT: index z0.s, #0, #1
178 ; VBITS_GE_256-NEXT: ptrue p1.s
179 ; VBITS_GE_256-NEXT: mov z1.s, w9
180 ; VBITS_GE_256-NEXT: mov x9, #8 // =0x8
181 ; VBITS_GE_256-NEXT: fmov s2, #5.00000000
182 ; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x0, x9, lsl #2]
183 ; VBITS_GE_256-NEXT: cmpeq p1.s, p1/z, z0.s, z1.s
184 ; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0]
185 ; VBITS_GE_256-NEXT: mov z3.s, p1/m, s2
186 ; VBITS_GE_256-NEXT: st1w { z3.s }, p0, [x8, x9, lsl #2]
187 ; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x8]
188 ; VBITS_GE_256-NEXT: ret
189 ;
190 ; VBITS_GE_512-LABEL: insertelement_v16f32:
191 ; VBITS_GE_512: // %bb.0:
192 ; VBITS_GE_512-NEXT: ptrue p0.s, vl16
193 ; VBITS_GE_512-NEXT: mov w9, #15 // =0xf
194 ; VBITS_GE_512-NEXT: index z0.s, #0, #1
195 ; VBITS_GE_512-NEXT: ptrue p1.s
196 ; VBITS_GE_512-NEXT: mov z1.s, w9
197 ; VBITS_GE_512-NEXT: ld1w { z2.s }, p0/z, [x0]
198 ; VBITS_GE_512-NEXT: cmpeq p1.s, p1/z, z0.s, z1.s
199 ; VBITS_GE_512-NEXT: fmov s0, #5.00000000
200 ; VBITS_GE_512-NEXT: mov z2.s, p1/m, s0
201 ; VBITS_GE_512-NEXT: st1w { z2.s }, p0, [x8]
202 ; VBITS_GE_512-NEXT: ret
203 %op1 = load <16 x float>, ptr %a
204 %r = insertelement <16 x float> %op1, float 5.0, i64 15
205 ret <16 x float> %r
206 }
208 define <32 x float> @insertelement_v32f32(ptr %a) vscale_range(8,0) #0 {
209 ; CHECK-LABEL: insertelement_v32f32:
210 ; CHECK: // %bb.0:
211 ; CHECK-NEXT: ptrue p0.s, vl32
212 ; CHECK-NEXT: mov w9, #31 // =0x1f
213 ; CHECK-NEXT: index z0.s, #0, #1
214 ; CHECK-NEXT: ptrue p1.s
215 ; CHECK-NEXT: mov z1.s, w9
216 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]
217 ; CHECK-NEXT: cmpeq p1.s, p1/z, z0.s, z1.s
218 ; CHECK-NEXT: fmov s0, #5.00000000
219 ; CHECK-NEXT: mov z2.s, p1/m, s0
220 ; CHECK-NEXT: st1w { z2.s }, p0, [x8]
221 ; CHECK-NEXT: ret
222 %op1 = load <32 x float>, ptr %a
223 %r = insertelement <32 x float> %op1, float 5.0, i64 31
224 ret <32 x float> %r
225 }
227 define <64 x float> @insertelement_v64f32(ptr %a) vscale_range(16,0) #0 {
228 ; CHECK-LABEL: insertelement_v64f32:
229 ; CHECK: // %bb.0:
230 ; CHECK-NEXT: ptrue p0.s, vl64
231 ; CHECK-NEXT: mov w9, #63 // =0x3f
232 ; CHECK-NEXT: index z0.s, #0, #1
233 ; CHECK-NEXT: ptrue p1.s
234 ; CHECK-NEXT: mov z1.s, w9
235 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]
236 ; CHECK-NEXT: cmpeq p1.s, p1/z, z0.s, z1.s
237 ; CHECK-NEXT: fmov s0, #5.00000000
238 ; CHECK-NEXT: mov z2.s, p1/m, s0
239 ; CHECK-NEXT: st1w { z2.s }, p0, [x8]
240 ; CHECK-NEXT: ret
241 %op1 = load <64 x float>, ptr %a
242 %r = insertelement <64 x float> %op1, float 5.0, i64 63
243 ret <64 x float> %r
244 }
246 ; Don't use SVE for 64-bit vectors.
247 define <1 x double> @insertelement_v1f64(<1 x double> %op1) vscale_range(2,0) #0 {
248 ; CHECK-LABEL: insertelement_v1f64:
249 ; CHECK: // %bb.0:
250 ; CHECK-NEXT: mov x8, #4617315517961601024 // =0x4014000000000000
251 ; CHECK-NEXT: fmov d0, x8
252 ; CHECK-NEXT: ret
253 %r = insertelement <1 x double> %op1, double 5.0, i64 0
254 ret <1 x double> %r
255 }
257 ; Don't use SVE for 128-bit vectors.
258 define <2 x double> @insertelement_v2f64(<2 x double> %op1) vscale_range(2,0) #0 {
259 ; CHECK-LABEL: insertelement_v2f64:
260 ; CHECK: // %bb.0:
261 ; CHECK-NEXT: fmov d1, #5.00000000
262 ; CHECK-NEXT: mov v0.d[1], v1.d[0]
263 ; CHECK-NEXT: ret
264 %r = insertelement <2 x double> %op1, double 5.0, i64 1
265 ret <2 x double> %r
266 }
268 define <4 x double> @insertelement_v4f64(ptr %a) vscale_range(2,0) #0 {
269 ; CHECK-LABEL: insertelement_v4f64:
270 ; CHECK: // %bb.0:
271 ; CHECK-NEXT: ptrue p0.d, vl4
272 ; CHECK-NEXT: mov w9, #3 // =0x3
273 ; CHECK-NEXT: index z0.d, #0, #1
274 ; CHECK-NEXT: ptrue p1.d
275 ; CHECK-NEXT: mov z1.d, x9
276 ; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
277 ; CHECK-NEXT: cmpeq p1.d, p1/z, z0.d, z1.d
278 ; CHECK-NEXT: fmov d0, #5.00000000
279 ; CHECK-NEXT: mov z2.d, p1/m, d0
280 ; CHECK-NEXT: st1d { z2.d }, p0, [x8]
281 ; CHECK-NEXT: ret
282 %op1 = load <4 x double>, ptr %a
283 %r = insertelement <4 x double> %op1, double 5.0, i64 3
284 ret <4 x double> %r
285 }
287 define <8 x double> @insertelement_v8f64(ptr %a) #0 {
288 ; VBITS_GE_256-LABEL: insertelement_v8f64:
289 ; VBITS_GE_256: // %bb.0:
290 ; VBITS_GE_256-NEXT: ptrue p0.d, vl4
291 ; VBITS_GE_256-NEXT: mov w9, #3 // =0x3
292 ; VBITS_GE_256-NEXT: index z0.d, #0, #1
293 ; VBITS_GE_256-NEXT: ptrue p1.d
294 ; VBITS_GE_256-NEXT: mov z1.d, x9
295 ; VBITS_GE_256-NEXT: mov x9, #4 // =0x4
296 ; VBITS_GE_256-NEXT: fmov d2, #5.00000000
297 ; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x0, x9, lsl #3]
298 ; VBITS_GE_256-NEXT: cmpeq p1.d, p1/z, z0.d, z1.d
299 ; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0]
300 ; VBITS_GE_256-NEXT: mov z3.d, p1/m, d2
301 ; VBITS_GE_256-NEXT: st1d { z3.d }, p0, [x8, x9, lsl #3]
302 ; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x8]
303 ; VBITS_GE_256-NEXT: ret
304 ;
305 ; VBITS_GE_512-LABEL: insertelement_v8f64:
306 ; VBITS_GE_512: // %bb.0:
307 ; VBITS_GE_512-NEXT: ptrue p0.d, vl8
308 ; VBITS_GE_512-NEXT: mov w9, #7 // =0x7
309 ; VBITS_GE_512-NEXT: index z0.d, #0, #1
310 ; VBITS_GE_512-NEXT: ptrue p1.d
311 ; VBITS_GE_512-NEXT: mov z1.d, x9
312 ; VBITS_GE_512-NEXT: ld1d { z2.d }, p0/z, [x0]
313 ; VBITS_GE_512-NEXT: cmpeq p1.d, p1/z, z0.d, z1.d
314 ; VBITS_GE_512-NEXT: fmov d0, #5.00000000
315 ; VBITS_GE_512-NEXT: mov z2.d, p1/m, d0
316 ; VBITS_GE_512-NEXT: st1d { z2.d }, p0, [x8]
317 ; VBITS_GE_512-NEXT: ret
318 %op1 = load <8 x double>, ptr %a
319 %r = insertelement <8 x double> %op1, double 5.0, i64 7
320 ret <8 x double> %r
321 }
323 define <16 x double> @insertelement_v16f64(ptr %a) vscale_range(8,0) #0 {
324 ; CHECK-LABEL: insertelement_v16f64:
325 ; CHECK: // %bb.0:
326 ; CHECK-NEXT: ptrue p0.d, vl16
327 ; CHECK-NEXT: mov w9, #15 // =0xf
328 ; CHECK-NEXT: index z0.d, #0, #1
329 ; CHECK-NEXT: ptrue p1.d
330 ; CHECK-NEXT: mov z1.d, x9
331 ; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
332 ; CHECK-NEXT: cmpeq p1.d, p1/z, z0.d, z1.d
333 ; CHECK-NEXT: fmov d0, #5.00000000
334 ; CHECK-NEXT: mov z2.d, p1/m, d0
335 ; CHECK-NEXT: st1d { z2.d }, p0, [x8]
336 ; CHECK-NEXT: ret
337 %op1 = load <16 x double>, ptr %a
338 %r = insertelement <16 x double> %op1, double 5.0, i64 15
339 ret <16 x double> %r
340 }
342 define <32 x double> @insertelement_v32f64(ptr %a) vscale_range(16,0) #0 {
343 ; CHECK-LABEL: insertelement_v32f64:
344 ; CHECK: // %bb.0:
345 ; CHECK-NEXT: ptrue p0.d, vl32
346 ; CHECK-NEXT: mov w9, #31 // =0x1f
347 ; CHECK-NEXT: index z0.d, #0, #1
348 ; CHECK-NEXT: ptrue p1.d
349 ; CHECK-NEXT: mov z1.d, x9
350 ; CHECK-NEXT: ld1d { z2.d }, p0/z, [x0]
351 ; CHECK-NEXT: cmpeq p1.d, p1/z, z0.d, z1.d
352 ; CHECK-NEXT: fmov d0, #5.00000000
353 ; CHECK-NEXT: mov z2.d, p1/m, d0
354 ; CHECK-NEXT: st1d { z2.d }, p0, [x8]
355 ; CHECK-NEXT: ret
356 %op1 = load <32 x double>, ptr %a
357 %r = insertelement <32 x double> %op1, double 5.0, i64 31
358 ret <32 x double> %r
359 }
361 attributes #0 = { "target-features"="+sve" }