| blob | 43113df07c079fab5ff9ff52c3a1a2932f422eb8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s
4 ; Float
6 declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f32.nxv2i32(<vscale x 2 x float>)
7 declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f32.nxv4i32(<vscale x 4 x float>)
8 declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float>)
9 declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float>)
10 declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float>)
11 declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float>)
12 declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float>)
14 define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
15 ; CHECK-LABEL: test_signed_v2f32_v2i32:
16 ; CHECK: // %bb.0:
17 ; CHECK-NEXT: ptrue p0.d
18 ; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
19 ; CHECK-NEXT: mov z2.d, #0xffffffff80000000
20 ; CHECK-NEXT: mov z1.s, w8
21 ; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
22 ; CHECK-NEXT: mov z3.s, w8
23 ; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
24 ; CHECK-NEXT: movprfx z1, z0
25 ; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.s
26 ; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z3.s
27 ; CHECK-NEXT: mov z3.d, #0x7fffffff
28 ; CHECK-NEXT: not p1.b, p0/z, p1.b
29 ; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
30 ; CHECK-NEXT: mov z1.d, p1/m, z2.d
31 ; CHECK-NEXT: sel z0.d, p2, z3.d, z1.d
32 ; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
33 ; CHECK-NEXT: ret
34 %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)
35 ret <vscale x 2 x i32> %x
36 }
38 define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
39 ; CHECK-LABEL: test_signed_v4f32_v4i32:
40 ; CHECK: // %bb.0:
41 ; CHECK-NEXT: ptrue p0.s
42 ; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
43 ; CHECK-NEXT: mov z2.s, #0x80000000
44 ; CHECK-NEXT: mov z1.s, w8
45 ; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
46 ; CHECK-NEXT: mov z3.s, w8
47 ; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
48 ; CHECK-NEXT: movprfx z1, z0
49 ; CHECK-NEXT: fcvtzs z1.s, p0/m, z0.s
50 ; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z3.s
51 ; CHECK-NEXT: mov z3.s, #0x7fffffff
52 ; CHECK-NEXT: not p1.b, p0/z, p1.b
53 ; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
54 ; CHECK-NEXT: mov z1.s, p1/m, z2.s
55 ; CHECK-NEXT: sel z0.s, p2, z3.s, z1.s
56 ; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
57 ; CHECK-NEXT: ret
58 %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)
59 ret <vscale x 4 x i32> %x
60 }
62 define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
63 ; CHECK-LABEL: test_signed_v8f32_v8i32:
64 ; CHECK: // %bb.0:
65 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
66 ; CHECK-NEXT: addvl sp, sp, #-1
67 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
68 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
69 ; CHECK-NEXT: .cfi_offset w29, -16
70 ; CHECK-NEXT: ptrue p0.s
71 ; CHECK-NEXT: mov w8, #-822083584 // =0xcf000000
72 ; CHECK-NEXT: mov z3.s, #0x80000000
73 ; CHECK-NEXT: mov z2.s, w8
74 ; CHECK-NEXT: mov w8, #1325400063 // =0x4effffff
75 ; CHECK-NEXT: mov z6.s, #0x7fffffff
76 ; CHECK-NEXT: mov z4.s, w8
77 ; CHECK-NEXT: movprfx z5, z1
78 ; CHECK-NEXT: fcvtzs z5.s, p0/m, z1.s
79 ; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z2.s
80 ; CHECK-NEXT: fcmge p2.s, p0/z, z1.s, z2.s
81 ; CHECK-NEXT: movprfx z2, z0
82 ; CHECK-NEXT: fcvtzs z2.s, p0/m, z0.s
83 ; CHECK-NEXT: fcmgt p3.s, p0/z, z0.s, z4.s
84 ; CHECK-NEXT: fcmgt p4.s, p0/z, z1.s, z4.s
85 ; CHECK-NEXT: not p1.b, p0/z, p1.b
86 ; CHECK-NEXT: not p2.b, p0/z, p2.b
87 ; CHECK-NEXT: mov z2.s, p1/m, z3.s
88 ; CHECK-NEXT: fcmuo p1.s, p0/z, z0.s, z0.s
89 ; CHECK-NEXT: fcmuo p0.s, p0/z, z1.s, z1.s
90 ; CHECK-NEXT: sel z3.s, p2, z3.s, z5.s
91 ; CHECK-NEXT: sel z0.s, p3, z6.s, z2.s
92 ; CHECK-NEXT: sel z1.s, p4, z6.s, z3.s
93 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
94 ; CHECK-NEXT: mov z0.s, p1/m, #0 // =0x0
95 ; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
96 ; CHECK-NEXT: addvl sp, sp, #1
97 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
98 ; CHECK-NEXT: ret
99 %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
100 ret <vscale x 8 x i32> %x
101 }
103 define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
104 ; CHECK-LABEL: test_signed_v4f32_v4i16:
105 ; CHECK: // %bb.0:
106 ; CHECK-NEXT: ptrue p0.s
107 ; CHECK-NEXT: mov w8, #-956301312 // =0xc7000000
108 ; CHECK-NEXT: mov z1.s, w8
109 ; CHECK-NEXT: mov w8, #65024 // =0xfe00
110 ; CHECK-NEXT: movk w8, #18175, lsl #16
111 ; CHECK-NEXT: mov z2.s, w8
112 ; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
113 ; CHECK-NEXT: movprfx z1, z0
114 ; CHECK-NEXT: fcvtzs z1.s, p0/m, z0.s
115 ; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z2.s
116 ; CHECK-NEXT: mov z2.s, #32767 // =0x7fff
117 ; CHECK-NEXT: not p1.b, p0/z, p1.b
118 ; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
119 ; CHECK-NEXT: mov z1.s, p1/m, #-32768 // =0xffffffffffff8000
120 ; CHECK-NEXT: sel z0.s, p2, z2.s, z1.s
121 ; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
122 ; CHECK-NEXT: ret
123 %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
124 ret <vscale x 4 x i16> %x
125 }
127 define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
128 ; CHECK-LABEL: test_signed_v8f32_v8i16:
129 ; CHECK: // %bb.0:
130 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
131 ; CHECK-NEXT: addvl sp, sp, #-1
132 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
133 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
134 ; CHECK-NEXT: .cfi_offset w29, -16
135 ; CHECK-NEXT: ptrue p0.s
136 ; CHECK-NEXT: mov w8, #-956301312 // =0xc7000000
137 ; CHECK-NEXT: movprfx z4, z0
138 ; CHECK-NEXT: fcvtzs z4.s, p0/m, z0.s
139 ; CHECK-NEXT: mov z2.s, w8
140 ; CHECK-NEXT: mov w8, #65024 // =0xfe00
141 ; CHECK-NEXT: mov z5.s, #32767 // =0x7fff
142 ; CHECK-NEXT: movk w8, #18175, lsl #16
143 ; CHECK-NEXT: mov z3.s, w8
144 ; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
145 ; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
146 ; CHECK-NEXT: movprfx z2, z1
147 ; CHECK-NEXT: fcvtzs z2.s, p0/m, z1.s
148 ; CHECK-NEXT: fcmgt p3.s, p0/z, z1.s, z3.s
149 ; CHECK-NEXT: fcmgt p4.s, p0/z, z0.s, z3.s
150 ; CHECK-NEXT: not p1.b, p0/z, p1.b
151 ; CHECK-NEXT: not p2.b, p0/z, p2.b
152 ; CHECK-NEXT: mov z2.s, p1/m, #-32768 // =0xffffffffffff8000
153 ; CHECK-NEXT: fcmuo p1.s, p0/z, z1.s, z1.s
154 ; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
155 ; CHECK-NEXT: mov z4.s, p2/m, #-32768 // =0xffffffffffff8000
156 ; CHECK-NEXT: sel z0.s, p3, z5.s, z2.s
157 ; CHECK-NEXT: sel z1.s, p4, z5.s, z4.s
158 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
159 ; CHECK-NEXT: mov z0.s, p1/m, #0 // =0x0
160 ; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
161 ; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
162 ; CHECK-NEXT: addvl sp, sp, #1
163 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
164 ; CHECK-NEXT: ret
165 %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
166 ret <vscale x 8 x i16> %x
167 }
169 define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
170 ; CHECK-LABEL: test_signed_v2f32_v2i64:
171 ; CHECK: // %bb.0:
172 ; CHECK-NEXT: ptrue p0.d
173 ; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
174 ; CHECK-NEXT: mov z2.d, #0x8000000000000000
175 ; CHECK-NEXT: mov z1.s, w8
176 ; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
177 ; CHECK-NEXT: mov z3.s, w8
178 ; CHECK-NEXT: fcmge p1.s, p0/z, z0.s, z1.s
179 ; CHECK-NEXT: movprfx z1, z0
180 ; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.s
181 ; CHECK-NEXT: fcmgt p2.s, p0/z, z0.s, z3.s
182 ; CHECK-NEXT: mov z3.d, #0x7fffffffffffffff
183 ; CHECK-NEXT: not p1.b, p0/z, p1.b
184 ; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
185 ; CHECK-NEXT: mov z1.d, p1/m, z2.d
186 ; CHECK-NEXT: sel z0.d, p2, z3.d, z1.d
187 ; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
188 ; CHECK-NEXT: ret
189 %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
190 ret <vscale x 2 x i64> %x
191 }
193 define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
194 ; CHECK-LABEL: test_signed_v4f32_v4i64:
195 ; CHECK: // %bb.0:
196 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
197 ; CHECK-NEXT: addvl sp, sp, #-1
198 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
199 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
200 ; CHECK-NEXT: .cfi_offset w29, -16
201 ; CHECK-NEXT: ptrue p0.d
202 ; CHECK-NEXT: mov w8, #-553648128 // =0xdf000000
203 ; CHECK-NEXT: uunpklo z1.d, z0.s
204 ; CHECK-NEXT: uunpkhi z0.d, z0.s
205 ; CHECK-NEXT: mov z2.s, w8
206 ; CHECK-NEXT: mov w8, #1593835519 // =0x5effffff
207 ; CHECK-NEXT: mov z3.d, #0x8000000000000000
208 ; CHECK-NEXT: mov z4.s, w8
209 ; CHECK-NEXT: movprfx z5, z0
210 ; CHECK-NEXT: fcvtzs z5.d, p0/m, z0.s
211 ; CHECK-NEXT: mov z6.d, #0x7fffffffffffffff
212 ; CHECK-NEXT: fcmge p1.s, p0/z, z1.s, z2.s
213 ; CHECK-NEXT: fcmge p2.s, p0/z, z0.s, z2.s
214 ; CHECK-NEXT: movprfx z2, z1
215 ; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.s
216 ; CHECK-NEXT: fcmgt p3.s, p0/z, z1.s, z4.s
217 ; CHECK-NEXT: fcmgt p4.s, p0/z, z0.s, z4.s
218 ; CHECK-NEXT: not p1.b, p0/z, p1.b
219 ; CHECK-NEXT: not p2.b, p0/z, p2.b
220 ; CHECK-NEXT: mov z2.d, p1/m, z3.d
221 ; CHECK-NEXT: fcmuo p1.s, p0/z, z1.s, z1.s
222 ; CHECK-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
223 ; CHECK-NEXT: sel z3.d, p2, z3.d, z5.d
224 ; CHECK-NEXT: sel z0.d, p3, z6.d, z2.d
225 ; CHECK-NEXT: sel z1.d, p4, z6.d, z3.d
226 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
227 ; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
228 ; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
229 ; CHECK-NEXT: addvl sp, sp, #1
230 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
231 ; CHECK-NEXT: ret
232 %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
233 ret <vscale x 4 x i64> %x
234 }
236 ; Double
238 declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)
239 declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)
240 declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)
241 declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)
242 declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)
243 declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)
244 declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)
246 define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
247 ; CHECK-LABEL: test_signed_v2f64_v2i32:
248 ; CHECK: // %bb.0:
249 ; CHECK-NEXT: ptrue p0.d
250 ; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
251 ; CHECK-NEXT: mov z2.d, #0xffffffff80000000
252 ; CHECK-NEXT: mov z1.d, x8
253 ; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
254 ; CHECK-NEXT: movk x8, #16863, lsl #48
255 ; CHECK-NEXT: mov z3.d, x8
256 ; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
257 ; CHECK-NEXT: movprfx z1, z0
258 ; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.d
259 ; CHECK-NEXT: fcmgt p2.d, p0/z, z0.d, z3.d
260 ; CHECK-NEXT: mov z3.d, #0x7fffffff
261 ; CHECK-NEXT: not p1.b, p0/z, p1.b
262 ; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
263 ; CHECK-NEXT: mov z1.d, p1/m, z2.d
264 ; CHECK-NEXT: sel z0.d, p2, z3.d, z1.d
265 ; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
266 ; CHECK-NEXT: ret
267 %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
268 ret <vscale x 2 x i32> %x
269 }
271 define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
272 ; CHECK-LABEL: test_signed_v4f64_v4i32:
273 ; CHECK: // %bb.0:
274 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
275 ; CHECK-NEXT: addvl sp, sp, #-1
276 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
277 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
278 ; CHECK-NEXT: .cfi_offset w29, -16
279 ; CHECK-NEXT: ptrue p0.d
280 ; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
281 ; CHECK-NEXT: mov z3.d, #0xffffffff80000000
282 ; CHECK-NEXT: mov z2.d, x8
283 ; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
284 ; CHECK-NEXT: mov z6.d, #0x7fffffff
285 ; CHECK-NEXT: movk x8, #16863, lsl #48
286 ; CHECK-NEXT: movprfx z5, z0
287 ; CHECK-NEXT: fcvtzs z5.d, p0/m, z0.d
288 ; CHECK-NEXT: mov z4.d, x8
289 ; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, z2.d
290 ; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, z2.d
291 ; CHECK-NEXT: movprfx z2, z1
292 ; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.d
293 ; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z4.d
294 ; CHECK-NEXT: fcmgt p4.d, p0/z, z0.d, z4.d
295 ; CHECK-NEXT: not p1.b, p0/z, p1.b
296 ; CHECK-NEXT: not p2.b, p0/z, p2.b
297 ; CHECK-NEXT: mov z2.d, p1/m, z3.d
298 ; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
299 ; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
300 ; CHECK-NEXT: sel z3.d, p2, z3.d, z5.d
301 ; CHECK-NEXT: sel z0.d, p3, z6.d, z2.d
302 ; CHECK-NEXT: sel z1.d, p4, z6.d, z3.d
303 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
304 ; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
305 ; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
306 ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
307 ; CHECK-NEXT: addvl sp, sp, #1
308 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
309 ; CHECK-NEXT: ret
310 %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
311 ret <vscale x 4 x i32> %x
312 }
314 define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
315 ; CHECK-LABEL: test_signed_v8f64_v8i32:
316 ; CHECK: // %bb.0:
317 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
318 ; CHECK-NEXT: addvl sp, sp, #-1
319 ; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Folded Spill
320 ; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Folded Spill
321 ; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Folded Spill
322 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
323 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
324 ; CHECK-NEXT: .cfi_offset w29, -16
325 ; CHECK-NEXT: ptrue p0.d
326 ; CHECK-NEXT: mov x8, #-4476578029606273024 // =0xc1e0000000000000
327 ; CHECK-NEXT: movprfx z6, z1
328 ; CHECK-NEXT: fcvtzs z6.d, p0/m, z1.d
329 ; CHECK-NEXT: mov z4.d, x8
330 ; CHECK-NEXT: mov x8, #281474972516352 // =0xffffffc00000
331 ; CHECK-NEXT: movprfx z7, z0
332 ; CHECK-NEXT: fcvtzs z7.d, p0/m, z0.d
333 ; CHECK-NEXT: movk x8, #16863, lsl #48
334 ; CHECK-NEXT: mov z26.d, #0x7fffffff
335 ; CHECK-NEXT: movprfx z24, z3
336 ; CHECK-NEXT: fcvtzs z24.d, p0/m, z3.d
337 ; CHECK-NEXT: mov z5.d, x8
338 ; CHECK-NEXT: movprfx z25, z2
339 ; CHECK-NEXT: fcvtzs z25.d, p0/m, z2.d
340 ; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, z4.d
341 ; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, z4.d
342 ; CHECK-NEXT: fcmge p3.d, p0/z, z3.d, z4.d
343 ; CHECK-NEXT: fcmge p4.d, p0/z, z2.d, z4.d
344 ; CHECK-NEXT: mov z4.d, #0xffffffff80000000
345 ; CHECK-NEXT: fcmgt p5.d, p0/z, z1.d, z5.d
346 ; CHECK-NEXT: fcmgt p6.d, p0/z, z0.d, z5.d
347 ; CHECK-NEXT: fcmgt p7.d, p0/z, z3.d, z5.d
348 ; CHECK-NEXT: not p1.b, p0/z, p1.b
349 ; CHECK-NEXT: not p2.b, p0/z, p2.b
350 ; CHECK-NEXT: not p3.b, p0/z, p3.b
351 ; CHECK-NEXT: not p4.b, p0/z, p4.b
352 ; CHECK-NEXT: mov z6.d, p1/m, z4.d
353 ; CHECK-NEXT: fcmgt p1.d, p0/z, z2.d, z5.d
354 ; CHECK-NEXT: sel z5.d, p2, z4.d, z7.d
355 ; CHECK-NEXT: fcmuo p2.d, p0/z, z1.d, z1.d
356 ; CHECK-NEXT: sel z7.d, p3, z4.d, z24.d
357 ; CHECK-NEXT: fcmuo p3.d, p0/z, z0.d, z0.d
358 ; CHECK-NEXT: sel z4.d, p4, z4.d, z25.d
359 ; CHECK-NEXT: fcmuo p4.d, p0/z, z3.d, z3.d
360 ; CHECK-NEXT: fcmuo p0.d, p0/z, z2.d, z2.d
361 ; CHECK-NEXT: sel z0.d, p5, z26.d, z6.d
362 ; CHECK-NEXT: sel z1.d, p6, z26.d, z5.d
363 ; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Folded Reload
364 ; CHECK-NEXT: sel z2.d, p7, z26.d, z7.d
365 ; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Folded Reload
366 ; CHECK-NEXT: sel z3.d, p1, z26.d, z4.d
367 ; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Folded Reload
368 ; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
369 ; CHECK-NEXT: mov z1.d, p3/m, #0 // =0x0
370 ; CHECK-NEXT: mov z2.d, p4/m, #0 // =0x0
371 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
372 ; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
373 ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
374 ; CHECK-NEXT: uzp1 z1.s, z3.s, z2.s
375 ; CHECK-NEXT: addvl sp, sp, #1
376 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
377 ; CHECK-NEXT: ret
378 %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
379 ret <vscale x 8 x i32> %x
380 }
382 define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
383 ; CHECK-LABEL: test_signed_v4f64_v4i16:
384 ; CHECK: // %bb.0:
385 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
386 ; CHECK-NEXT: addvl sp, sp, #-1
387 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
388 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
389 ; CHECK-NEXT: .cfi_offset w29, -16
390 ; CHECK-NEXT: ptrue p0.d
391 ; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000
392 ; CHECK-NEXT: movprfx z4, z0
393 ; CHECK-NEXT: fcvtzs z4.d, p0/m, z0.d
394 ; CHECK-NEXT: mov z2.d, x8
395 ; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000
396 ; CHECK-NEXT: mov z5.d, #32767 // =0x7fff
397 ; CHECK-NEXT: movk x8, #16607, lsl #48
398 ; CHECK-NEXT: mov z3.d, x8
399 ; CHECK-NEXT: fcmge p1.d, p0/z, z1.d, z2.d
400 ; CHECK-NEXT: fcmge p2.d, p0/z, z0.d, z2.d
401 ; CHECK-NEXT: movprfx z2, z1
402 ; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.d
403 ; CHECK-NEXT: fcmgt p3.d, p0/z, z1.d, z3.d
404 ; CHECK-NEXT: fcmgt p4.d, p0/z, z0.d, z3.d
405 ; CHECK-NEXT: not p1.b, p0/z, p1.b
406 ; CHECK-NEXT: not p2.b, p0/z, p2.b
407 ; CHECK-NEXT: mov z2.d, p1/m, #-32768 // =0xffffffffffff8000
408 ; CHECK-NEXT: fcmuo p1.d, p0/z, z1.d, z1.d
409 ; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
410 ; CHECK-NEXT: mov z4.d, p2/m, #-32768 // =0xffffffffffff8000
411 ; CHECK-NEXT: sel z0.d, p3, z5.d, z2.d
412 ; CHECK-NEXT: sel z1.d, p4, z5.d, z4.d
413 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
414 ; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
415 ; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
416 ; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
417 ; CHECK-NEXT: addvl sp, sp, #1
418 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
419 ; CHECK-NEXT: ret
420 %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)
421 ret <vscale x 4 x i16> %x
422 }
424 define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
425 ; CHECK-LABEL: test_signed_v8f64_v8i16:
426 ; CHECK: // %bb.0:
427 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
428 ; CHECK-NEXT: addvl sp, sp, #-1
429 ; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Folded Spill
430 ; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Folded Spill
431 ; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Folded Spill
432 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
433 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
434 ; CHECK-NEXT: .cfi_offset w29, -16
435 ; CHECK-NEXT: ptrue p0.d
436 ; CHECK-NEXT: mov x8, #-4548635623644200960 // =0xc0e0000000000000
437 ; CHECK-NEXT: movprfx z5, z3
438 ; CHECK-NEXT: fcvtzs z5.d, p0/m, z3.d
439 ; CHECK-NEXT: mov z4.d, x8
440 ; CHECK-NEXT: mov x8, #281200098803712 // =0xffc000000000
441 ; CHECK-NEXT: movprfx z6, z2
442 ; CHECK-NEXT: fcvtzs z6.d, p0/m, z2.d
443 ; CHECK-NEXT: movk x8, #16607, lsl #48
444 ; CHECK-NEXT: movprfx z7, z1
445 ; CHECK-NEXT: fcvtzs z7.d, p0/m, z1.d
446 ; CHECK-NEXT: movprfx z24, z0
447 ; CHECK-NEXT: fcvtzs z24.d, p0/m, z0.d
448 ; CHECK-NEXT: mov z25.d, #32767 // =0x7fff
449 ; CHECK-NEXT: fcmge p1.d, p0/z, z3.d, z4.d
450 ; CHECK-NEXT: fcmge p2.d, p0/z, z2.d, z4.d
451 ; CHECK-NEXT: fcmge p3.d, p0/z, z1.d, z4.d
452 ; CHECK-NEXT: fcmge p4.d, p0/z, z0.d, z4.d
453 ; CHECK-NEXT: mov z4.d, x8
454 ; CHECK-NEXT: not p1.b, p0/z, p1.b
455 ; CHECK-NEXT: fcmgt p5.d, p0/z, z3.d, z4.d
456 ; CHECK-NEXT: fcmgt p6.d, p0/z, z2.d, z4.d
457 ; CHECK-NEXT: not p2.b, p0/z, p2.b
458 ; CHECK-NEXT: fcmgt p7.d, p0/z, z1.d, z4.d
459 ; CHECK-NEXT: not p3.b, p0/z, p3.b
460 ; CHECK-NEXT: not p4.b, p0/z, p4.b
461 ; CHECK-NEXT: mov z5.d, p1/m, #-32768 // =0xffffffffffff8000
462 ; CHECK-NEXT: fcmgt p1.d, p0/z, z0.d, z4.d
463 ; CHECK-NEXT: mov z6.d, p2/m, #-32768 // =0xffffffffffff8000
464 ; CHECK-NEXT: fcmuo p2.d, p0/z, z3.d, z3.d
465 ; CHECK-NEXT: mov z7.d, p3/m, #-32768 // =0xffffffffffff8000
466 ; CHECK-NEXT: fcmuo p3.d, p0/z, z2.d, z2.d
467 ; CHECK-NEXT: mov z24.d, p4/m, #-32768 // =0xffffffffffff8000
468 ; CHECK-NEXT: fcmuo p4.d, p0/z, z1.d, z1.d
469 ; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
470 ; CHECK-NEXT: sel z2.d, p5, z25.d, z5.d
471 ; CHECK-NEXT: sel z0.d, p6, z25.d, z6.d
472 ; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Folded Reload
473 ; CHECK-NEXT: sel z1.d, p7, z25.d, z7.d
474 ; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Folded Reload
475 ; CHECK-NEXT: sel z3.d, p1, z25.d, z24.d
476 ; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Folded Reload
477 ; CHECK-NEXT: mov z2.d, p2/m, #0 // =0x0
478 ; CHECK-NEXT: mov z0.d, p3/m, #0 // =0x0
479 ; CHECK-NEXT: mov z1.d, p4/m, #0 // =0x0
480 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
481 ; CHECK-NEXT: mov z3.d, p0/m, #0 // =0x0
482 ; CHECK-NEXT: uzp1 z0.s, z0.s, z2.s
483 ; CHECK-NEXT: uzp1 z1.s, z3.s, z1.s
484 ; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
485 ; CHECK-NEXT: addvl sp, sp, #1
486 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
487 ; CHECK-NEXT: ret
488 %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)
489 ret <vscale x 8 x i16> %x
490 }
492 define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
493 ; CHECK-LABEL: test_signed_v2f64_v2i64:
494 ; CHECK: // %bb.0:
495 ; CHECK-NEXT: ptrue p0.d
496 ; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
497 ; CHECK-NEXT: mov z2.d, #0x8000000000000000
498 ; CHECK-NEXT: mov z1.d, x8
499 ; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
500 ; CHECK-NEXT: mov z3.d, x8
501 ; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z1.d
502 ; CHECK-NEXT: movprfx z1, z0
503 ; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.d
504 ; CHECK-NEXT: fcmgt p2.d, p0/z, z0.d, z3.d
505 ; CHECK-NEXT: mov z3.d, #0x7fffffffffffffff
506 ; CHECK-NEXT: not p1.b, p0/z, p1.b
507 ; CHECK-NEXT: fcmuo p0.d, p0/z, z0.d, z0.d
508 ; CHECK-NEXT: mov z1.d, p1/m, z2.d
509 ; CHECK-NEXT: sel z0.d, p2, z3.d, z1.d
510 ; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
511 ; CHECK-NEXT: ret
512 %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)
513 ret <vscale x 2 x i64> %x
514 }
516 define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {
517 ; CHECK-LABEL: test_signed_v4f64_v4i64:
518 ; CHECK: // %bb.0:
519 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
520 ; CHECK-NEXT: addvl sp, sp, #-1
521 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
522 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
523 ; CHECK-NEXT: .cfi_offset w29, -16
524 ; CHECK-NEXT: ptrue p0.d
525 ; CHECK-NEXT: mov x8, #-4332462841530417152 // =0xc3e0000000000000
526 ; CHECK-NEXT: mov z3.d, #0x8000000000000000
527 ; CHECK-NEXT: mov z2.d, x8
528 ; CHECK-NEXT: mov x8, #4890909195324358655 // =0x43dfffffffffffff
529 ; CHECK-NEXT: mov z6.d, #0x7fffffffffffffff
530 ; CHECK-NEXT: mov z4.d, x8
531 ; CHECK-NEXT: movprfx z5, z1
532 ; CHECK-NEXT: fcvtzs z5.d, p0/m, z1.d
533 ; CHECK-NEXT: fcmge p1.d, p0/z, z0.d, z2.d
534 ; CHECK-NEXT: fcmge p2.d, p0/z, z1.d, z2.d
535 ; CHECK-NEXT: movprfx z2, z0
536 ; CHECK-NEXT: fcvtzs z2.d, p0/m, z0.d
537 ; CHECK-NEXT: fcmgt p3.d, p0/z, z0.d, z4.d
538 ; CHECK-NEXT: fcmgt p4.d, p0/z, z1.d, z4.d
539 ; CHECK-NEXT: not p1.b, p0/z, p1.b
540 ; CHECK-NEXT: not p2.b, p0/z, p2.b
541 ; CHECK-NEXT: mov z2.d, p1/m, z3.d
542 ; CHECK-NEXT: fcmuo p1.d, p0/z, z0.d, z0.d
543 ; CHECK-NEXT: fcmuo p0.d, p0/z, z1.d, z1.d
544 ; CHECK-NEXT: sel z3.d, p2, z3.d, z5.d
545 ; CHECK-NEXT: sel z0.d, p3, z6.d, z2.d
546 ; CHECK-NEXT: sel z1.d, p4, z6.d, z3.d
547 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
548 ; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
549 ; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
550 ; CHECK-NEXT: addvl sp, sp, #1
551 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
552 ; CHECK-NEXT: ret
553 %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)
554 ret <vscale x 4 x i64> %x
555 }
558 ; half
560 declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half>)
561 declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half>)
562 declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half>)
563 declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f16.nxv4i16(<vscale x 4 x half>)
564 declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)
565 declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)
566 declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
568 define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
569 ; CHECK-LABEL: test_signed_v2f16_v2i32:
570 ; CHECK: // %bb.0:
571 ; CHECK-NEXT: ptrue p0.d
572 ; CHECK-NEXT: mov w8, #64511 // =0xfbff
573 ; CHECK-NEXT: mov z2.d, #0xffffffff80000000
574 ; CHECK-NEXT: mov z1.h, w8
575 ; CHECK-NEXT: mov w8, #31743 // =0x7bff
576 ; CHECK-NEXT: mov z3.h, w8
577 ; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
578 ; CHECK-NEXT: movprfx z1, z0
579 ; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.h
580 ; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z3.h
581 ; CHECK-NEXT: mov z3.d, #0x7fffffff
582 ; CHECK-NEXT: not p1.b, p0/z, p1.b
583 ; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
584 ; CHECK-NEXT: mov z1.d, p1/m, z2.d
585 ; CHECK-NEXT: sel z0.d, p2, z3.d, z1.d
586 ; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
587 ; CHECK-NEXT: ret
588 %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
589 ret <vscale x 2 x i32> %x
590 }
592 define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
593 ; CHECK-LABEL: test_signed_v4f16_v4i32:
594 ; CHECK: // %bb.0:
595 ; CHECK-NEXT: ptrue p0.s
596 ; CHECK-NEXT: mov w8, #64511 // =0xfbff
597 ; CHECK-NEXT: mov z2.s, #0x80000000
598 ; CHECK-NEXT: mov z1.h, w8
599 ; CHECK-NEXT: mov w8, #31743 // =0x7bff
600 ; CHECK-NEXT: mov z3.h, w8
601 ; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
602 ; CHECK-NEXT: movprfx z1, z0
603 ; CHECK-NEXT: fcvtzs z1.s, p0/m, z0.h
604 ; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z3.h
605 ; CHECK-NEXT: mov z3.s, #0x7fffffff
606 ; CHECK-NEXT: not p1.b, p0/z, p1.b
607 ; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
608 ; CHECK-NEXT: mov z1.s, p1/m, z2.s
609 ; CHECK-NEXT: sel z0.s, p2, z3.s, z1.s
610 ; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
611 ; CHECK-NEXT: ret
612 %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
613 ret <vscale x 4 x i32> %x
614 }
616 define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
617 ; CHECK-LABEL: test_signed_v8f16_v8i32:
618 ; CHECK: // %bb.0:
619 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
620 ; CHECK-NEXT: addvl sp, sp, #-1
621 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
622 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
623 ; CHECK-NEXT: .cfi_offset w29, -16
624 ; CHECK-NEXT: ptrue p0.s
625 ; CHECK-NEXT: mov w8, #64511 // =0xfbff
626 ; CHECK-NEXT: uunpklo z1.s, z0.h
627 ; CHECK-NEXT: uunpkhi z0.s, z0.h
628 ; CHECK-NEXT: mov z2.h, w8
629 ; CHECK-NEXT: mov w8, #31743 // =0x7bff
630 ; CHECK-NEXT: mov z3.s, #0x80000000
631 ; CHECK-NEXT: mov z4.h, w8
632 ; CHECK-NEXT: movprfx z5, z0
633 ; CHECK-NEXT: fcvtzs z5.s, p0/m, z0.h
634 ; CHECK-NEXT: mov z6.s, #0x7fffffff
635 ; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z2.h
636 ; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z2.h
637 ; CHECK-NEXT: movprfx z2, z1
638 ; CHECK-NEXT: fcvtzs z2.s, p0/m, z1.h
639 ; CHECK-NEXT: fcmgt p3.h, p0/z, z1.h, z4.h
640 ; CHECK-NEXT: fcmgt p4.h, p0/z, z0.h, z4.h
641 ; CHECK-NEXT: not p1.b, p0/z, p1.b
642 ; CHECK-NEXT: not p2.b, p0/z, p2.b
643 ; CHECK-NEXT: mov z2.s, p1/m, z3.s
644 ; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z1.h
645 ; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
646 ; CHECK-NEXT: sel z3.s, p2, z3.s, z5.s
647 ; CHECK-NEXT: sel z0.s, p3, z6.s, z2.s
648 ; CHECK-NEXT: sel z1.s, p4, z6.s, z3.s
649 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
650 ; CHECK-NEXT: mov z0.s, p1/m, #0 // =0x0
651 ; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
652 ; CHECK-NEXT: addvl sp, sp, #1
653 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
654 ; CHECK-NEXT: ret
655 %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
656 ret <vscale x 8 x i32> %x
657 }
659 define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
660 ; CHECK-LABEL: test_signed_v4f16_v4i16:
661 ; CHECK: // %bb.0:
662 ; CHECK-NEXT: ptrue p0.s
663 ; CHECK-NEXT: mov w8, #63488 // =0xf800
664 ; CHECK-NEXT: mov z1.h, w8
665 ; CHECK-NEXT: mov w8, #30719 // =0x77ff
666 ; CHECK-NEXT: mov z2.h, w8
667 ; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
668 ; CHECK-NEXT: movprfx z1, z0
669 ; CHECK-NEXT: fcvtzs z1.s, p0/m, z0.h
670 ; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h
671 ; CHECK-NEXT: mov z2.s, #32767 // =0x7fff
672 ; CHECK-NEXT: not p1.b, p0/z, p1.b
673 ; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
674 ; CHECK-NEXT: mov z1.s, p1/m, #-32768 // =0xffffffffffff8000
675 ; CHECK-NEXT: sel z0.s, p2, z2.s, z1.s
676 ; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
677 ; CHECK-NEXT: ret
678 %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)
679 ret <vscale x 4 x i16> %x
680 }
682 define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
683 ; CHECK-LABEL: test_signed_v8f16_v8i16:
684 ; CHECK: // %bb.0:
685 ; CHECK-NEXT: ptrue p0.h
686 ; CHECK-NEXT: mov w8, #63488 // =0xf800
687 ; CHECK-NEXT: mov z1.h, w8
688 ; CHECK-NEXT: mov w8, #30719 // =0x77ff
689 ; CHECK-NEXT: mov z2.h, w8
690 ; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
691 ; CHECK-NEXT: movprfx z1, z0
692 ; CHECK-NEXT: fcvtzs z1.h, p0/m, z0.h
693 ; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z2.h
694 ; CHECK-NEXT: mov z2.h, #32767 // =0x7fff
695 ; CHECK-NEXT: not p1.b, p0/z, p1.b
696 ; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
697 ; CHECK-NEXT: mov z1.h, p1/m, #-32768 // =0xffffffffffff8000
698 ; CHECK-NEXT: sel z0.h, p2, z2.h, z1.h
699 ; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0
700 ; CHECK-NEXT: ret
701 %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
702 ret <vscale x 8 x i16> %x
703 }
705 define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
706 ; CHECK-LABEL: test_signed_v2f16_v2i64:
707 ; CHECK: // %bb.0:
708 ; CHECK-NEXT: ptrue p0.d
709 ; CHECK-NEXT: mov w8, #64511 // =0xfbff
710 ; CHECK-NEXT: mov z2.d, #0x8000000000000000
711 ; CHECK-NEXT: mov z1.h, w8
712 ; CHECK-NEXT: mov w8, #31743 // =0x7bff
713 ; CHECK-NEXT: mov z3.h, w8
714 ; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
715 ; CHECK-NEXT: movprfx z1, z0
716 ; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.h
717 ; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z3.h
718 ; CHECK-NEXT: mov z3.d, #0x7fffffffffffffff
719 ; CHECK-NEXT: not p1.b, p0/z, p1.b
720 ; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
721 ; CHECK-NEXT: mov z1.d, p1/m, z2.d
722 ; CHECK-NEXT: sel z0.d, p2, z3.d, z1.d
723 ; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
724 ; CHECK-NEXT: ret
725 %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
726 ret <vscale x 2 x i64> %x
727 }
729 define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
730 ; CHECK-LABEL: test_signed_v4f16_v4i64:
731 ; CHECK: // %bb.0:
732 ; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
733 ; CHECK-NEXT: addvl sp, sp, #-1
734 ; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
735 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
736 ; CHECK-NEXT: .cfi_offset w29, -16
737 ; CHECK-NEXT: ptrue p0.d
738 ; CHECK-NEXT: mov w8, #64511 // =0xfbff
739 ; CHECK-NEXT: uunpklo z1.d, z0.s
740 ; CHECK-NEXT: uunpkhi z0.d, z0.s
741 ; CHECK-NEXT: mov z2.h, w8
742 ; CHECK-NEXT: mov w8, #31743 // =0x7bff
743 ; CHECK-NEXT: mov z3.d, #0x8000000000000000
744 ; CHECK-NEXT: mov z4.h, w8
745 ; CHECK-NEXT: movprfx z5, z0
746 ; CHECK-NEXT: fcvtzs z5.d, p0/m, z0.h
747 ; CHECK-NEXT: mov z6.d, #0x7fffffffffffffff
748 ; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z2.h
749 ; CHECK-NEXT: fcmge p2.h, p0/z, z0.h, z2.h
750 ; CHECK-NEXT: movprfx z2, z1
751 ; CHECK-NEXT: fcvtzs z2.d, p0/m, z1.h
752 ; CHECK-NEXT: fcmgt p3.h, p0/z, z1.h, z4.h
753 ; CHECK-NEXT: fcmgt p4.h, p0/z, z0.h, z4.h
754 ; CHECK-NEXT: not p1.b, p0/z, p1.b
755 ; CHECK-NEXT: not p2.b, p0/z, p2.b
756 ; CHECK-NEXT: mov z2.d, p1/m, z3.d
757 ; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z1.h
758 ; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
759 ; CHECK-NEXT: sel z3.d, p2, z3.d, z5.d
760 ; CHECK-NEXT: sel z0.d, p3, z6.d, z2.d
761 ; CHECK-NEXT: sel z1.d, p4, z6.d, z3.d
762 ; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
763 ; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
764 ; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
765 ; CHECK-NEXT: addvl sp, sp, #1
766 ; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
767 ; CHECK-NEXT: ret
768 %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
769 ret <vscale x 4 x i64> %x
770 }