1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
4 define <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
5 ; CHECK-LABEL: add_i64:
7 ; CHECK-NEXT: add z0.d, z0.d, z1.d
9 %res = add <vscale x 2 x i64> %a, %b
10 ret <vscale x 2 x i64> %res
13 define <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
14 ; CHECK-LABEL: add_i32:
16 ; CHECK-NEXT: add z0.s, z0.s, z1.s
18 %res = add <vscale x 4 x i32> %a, %b
19 ret <vscale x 4 x i32> %res
22 define <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
23 ; CHECK-LABEL: add_i16:
25 ; CHECK-NEXT: add z0.h, z0.h, z1.h
27 %res = add <vscale x 8 x i16> %a, %b
28 ret <vscale x 8 x i16> %res
31 define <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
32 ; CHECK-LABEL: add_i8:
34 ; CHECK-NEXT: add z0.b, z0.b, z1.b
36 %res = add <vscale x 16 x i8> %a, %b
37 ret <vscale x 16 x i8> %res
40 define <vscale x 16 x i8> @add_i8_zero(<vscale x 16 x i8> %a) {
41 ; CHECK-LABEL: add_i8_zero:
44 %res = add <vscale x 16 x i8> %a, zeroinitializer
45 ret <vscale x 16 x i8> %res
48 define <vscale x 1 x i32> @add_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {
49 ; CHECK-LABEL: add_nxv1i32:
50 ; CHECK: // %bb.0: // %entry
51 ; CHECK-NEXT: add z0.s, z0.s, z1.s
54 %c = add <vscale x 1 x i32> %a, %b
55 ret <vscale x 1 x i32> %c
58 define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
59 ; CHECK-LABEL: sub_i64:
61 ; CHECK-NEXT: sub z0.d, z0.d, z1.d
63 %res = sub <vscale x 2 x i64> %a, %b
64 ret <vscale x 2 x i64> %res
67 define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
68 ; CHECK-LABEL: sub_i32:
70 ; CHECK-NEXT: sub z0.s, z0.s, z1.s
72 %res = sub <vscale x 4 x i32> %a, %b
73 ret <vscale x 4 x i32> %res
76 define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
77 ; CHECK-LABEL: sub_i16:
79 ; CHECK-NEXT: sub z0.h, z0.h, z1.h
81 %res = sub <vscale x 8 x i16> %a, %b
82 ret <vscale x 8 x i16> %res
85 define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
86 ; CHECK-LABEL: sub_i8:
88 ; CHECK-NEXT: sub z0.b, z0.b, z1.b
90 %res = sub <vscale x 16 x i8> %a, %b
91 ret <vscale x 16 x i8> %res
94 define <vscale x 16 x i8> @sub_i8_zero(<vscale x 16 x i8> %a) {
95 ; CHECK-LABEL: sub_i8_zero:
98 %res = sub <vscale x 16 x i8> %a, zeroinitializer
99 ret <vscale x 16 x i8> %res
102 define <vscale x 16 x i8> @abs_nxv16i8(<vscale x 16 x i8> %a) {
103 ; CHECK-LABEL: abs_nxv16i8:
105 ; CHECK-NEXT: ptrue p0.b
106 ; CHECK-NEXT: abs z0.b, p0/m, z0.b
108 %res = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %a, i1 false)
109 ret <vscale x 16 x i8> %res
112 define <vscale x 8 x i16> @abs_nxv8i16(<vscale x 8 x i16> %a) {
113 ; CHECK-LABEL: abs_nxv8i16:
115 ; CHECK-NEXT: ptrue p0.h
116 ; CHECK-NEXT: abs z0.h, p0/m, z0.h
118 %res = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %a, i1 false)
119 ret <vscale x 8 x i16> %res
122 define <vscale x 4 x i32> @abs_nxv4i32(<vscale x 4 x i32> %a) {
123 ; CHECK-LABEL: abs_nxv4i32:
125 ; CHECK-NEXT: ptrue p0.s
126 ; CHECK-NEXT: abs z0.s, p0/m, z0.s
128 %res = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %a, i1 false)
129 ret <vscale x 4 x i32> %res
132 define <vscale x 2 x i64> @abs_nxv2i64(<vscale x 2 x i64> %a) {
133 ; CHECK-LABEL: abs_nxv2i64:
135 ; CHECK-NEXT: ptrue p0.d
136 ; CHECK-NEXT: abs z0.d, p0/m, z0.d
138 %res = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %a, i1 false)
139 ret <vscale x 2 x i64> %res
142 define <vscale x 4 x i16> @abs_nxv4i16(<vscale x 4 x i16> %a) {
143 ; CHECK-LABEL: abs_nxv4i16:
145 ; CHECK-NEXT: ptrue p0.s
146 ; CHECK-NEXT: sxth z0.s, p0/m, z0.s
147 ; CHECK-NEXT: abs z0.s, p0/m, z0.s
149 %res = call <vscale x 4 x i16> @llvm.abs.nxv4i16(<vscale x 4 x i16> %a, i1 false)
150 ret <vscale x 4 x i16> %res
153 define <vscale x 32 x i8> @abs_nxv32i8(<vscale x 32 x i8> %a) {
154 ; CHECK-LABEL: abs_nxv32i8:
156 ; CHECK-NEXT: ptrue p0.b
157 ; CHECK-NEXT: abs z0.b, p0/m, z0.b
158 ; CHECK-NEXT: abs z1.b, p0/m, z1.b
160 %res = call <vscale x 32 x i8> @llvm.abs.nxv32i8(<vscale x 32 x i8> %a, i1 false)
161 ret <vscale x 32 x i8> %res
164 define <vscale x 8 x i64> @abs_nxv8i64(<vscale x 8 x i64> %a) {
165 ; CHECK-LABEL: abs_nxv8i64:
167 ; CHECK-NEXT: ptrue p0.d
168 ; CHECK-NEXT: abs z0.d, p0/m, z0.d
169 ; CHECK-NEXT: abs z1.d, p0/m, z1.d
170 ; CHECK-NEXT: abs z2.d, p0/m, z2.d
171 ; CHECK-NEXT: abs z3.d, p0/m, z3.d
173 %res = call <vscale x 8 x i64> @llvm.abs.nxv8i64(<vscale x 8 x i64> %a, i1 false)
174 ret <vscale x 8 x i64> %res
177 define <vscale x 2 x i64> @sqadd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
178 ; CHECK-LABEL: sqadd_i64:
180 ; CHECK-NEXT: sqadd z0.d, z0.d, z1.d
182 %res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
183 ret <vscale x 2 x i64> %res
186 define <vscale x 4 x i32> @sqadd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
187 ; CHECK-LABEL: sqadd_i32:
189 ; CHECK-NEXT: sqadd z0.s, z0.s, z1.s
191 %res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
192 ret <vscale x 4 x i32> %res
195 define <vscale x 4 x i32> @sqadd_i32_zero(<vscale x 4 x i32> %a) {
196 ; CHECK-LABEL: sqadd_i32_zero:
199 %res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer)
200 ret <vscale x 4 x i32> %res
203 define <vscale x 8 x i16> @sqadd_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
204 ; CHECK-LABEL: sqadd_i16:
206 ; CHECK-NEXT: sqadd z0.h, z0.h, z1.h
208 %res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
209 ret <vscale x 8 x i16> %res
212 define <vscale x 16 x i8> @sqadd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
213 ; CHECK-LABEL: sqadd_i8:
215 ; CHECK-NEXT: sqadd z0.b, z0.b, z1.b
217 %res = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
218 ret <vscale x 16 x i8> %res
222 define <vscale x 2 x i64> @sqsub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
223 ; CHECK-LABEL: sqsub_i64:
225 ; CHECK-NEXT: sqsub z0.d, z0.d, z1.d
227 %res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
228 ret <vscale x 2 x i64> %res
231 define <vscale x 2 x i64> @sqsub_i64_zero(<vscale x 2 x i64> %a) {
232 ; CHECK-LABEL: sqsub_i64_zero:
235 %res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer)
236 ret <vscale x 2 x i64> %res
239 define <vscale x 4 x i32> @sqsub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
240 ; CHECK-LABEL: sqsub_i32:
242 ; CHECK-NEXT: sqsub z0.s, z0.s, z1.s
244 %res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
245 ret <vscale x 4 x i32> %res
248 define <vscale x 8 x i16> @sqsub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
249 ; CHECK-LABEL: sqsub_i16:
251 ; CHECK-NEXT: sqsub z0.h, z0.h, z1.h
253 %res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
254 ret <vscale x 8 x i16> %res
257 define <vscale x 16 x i8> @sqsub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
258 ; CHECK-LABEL: sqsub_i8:
260 ; CHECK-NEXT: sqsub z0.b, z0.b, z1.b
262 %res = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
263 ret <vscale x 16 x i8> %res
267 define <vscale x 2 x i64> @uqadd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
268 ; CHECK-LABEL: uqadd_i64:
270 ; CHECK-NEXT: uqadd z0.d, z0.d, z1.d
272 %res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
273 ret <vscale x 2 x i64> %res
276 define <vscale x 4 x i32> @uqadd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
277 ; CHECK-LABEL: uqadd_i32:
279 ; CHECK-NEXT: uqadd z0.s, z0.s, z1.s
281 %res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
282 ret <vscale x 4 x i32> %res
285 define <vscale x 8 x i16> @uqadd_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
286 ; CHECK-LABEL: uqadd_i16:
288 ; CHECK-NEXT: uqadd z0.h, z0.h, z1.h
290 %res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
291 ret <vscale x 8 x i16> %res
294 define <vscale x 16 x i8> @uqadd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
295 ; CHECK-LABEL: uqadd_i8:
297 ; CHECK-NEXT: uqadd z0.b, z0.b, z1.b
299 %res = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
300 ret <vscale x 16 x i8> %res
304 define <vscale x 2 x i64> @uqsub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
305 ; CHECK-LABEL: uqsub_i64:
307 ; CHECK-NEXT: uqsub z0.d, z0.d, z1.d
309 %res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
310 ret <vscale x 2 x i64> %res
313 define <vscale x 4 x i32> @uqsub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
314 ; CHECK-LABEL: uqsub_i32:
316 ; CHECK-NEXT: uqsub z0.s, z0.s, z1.s
318 %res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
319 ret <vscale x 4 x i32> %res
322 define <vscale x 8 x i16> @uqsub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
323 ; CHECK-LABEL: uqsub_i16:
325 ; CHECK-NEXT: uqsub z0.h, z0.h, z1.h
327 %res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
328 ret <vscale x 8 x i16> %res
331 define <vscale x 16 x i8> @uqsub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
332 ; CHECK-LABEL: uqsub_i8:
334 ; CHECK-NEXT: uqsub z0.b, z0.b, z1.b
336 %res = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
337 ret <vscale x 16 x i8> %res
340 define <vscale x 16 x i8> @mad_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
341 ; CHECK-LABEL: mad_i8:
343 ; CHECK-NEXT: ptrue p0.b
344 ; CHECK-NEXT: mad z0.b, p0/m, z1.b, z2.b
346 %prod = mul <vscale x 16 x i8> %a, %b
347 %res = add <vscale x 16 x i8> %c, %prod
348 ret <vscale x 16 x i8> %res
351 define <vscale x 8 x i16> @mad_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
352 ; CHECK-LABEL: mad_i16:
354 ; CHECK-NEXT: ptrue p0.h
355 ; CHECK-NEXT: mad z0.h, p0/m, z1.h, z2.h
357 %prod = mul <vscale x 8 x i16> %a, %b
358 %res = add <vscale x 8 x i16> %c, %prod
359 ret <vscale x 8 x i16> %res
362 define <vscale x 4 x i32> @mad_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
363 ; CHECK-LABEL: mad_i32:
365 ; CHECK-NEXT: ptrue p0.s
366 ; CHECK-NEXT: mad z0.s, p0/m, z1.s, z2.s
368 %prod = mul <vscale x 4 x i32> %a, %b
369 %res = add <vscale x 4 x i32> %c, %prod
370 ret <vscale x 4 x i32> %res
373 define <vscale x 2 x i64> @mad_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
374 ; CHECK-LABEL: mad_i64:
376 ; CHECK-NEXT: ptrue p0.d
377 ; CHECK-NEXT: mad z0.d, p0/m, z1.d, z2.d
379 %prod = mul <vscale x 2 x i64> %a, %b
380 %res = add <vscale x 2 x i64> %c, %prod
381 ret <vscale x 2 x i64> %res
384 define <vscale x 16 x i8> @mla_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
385 ; CHECK-LABEL: mla_i8:
387 ; CHECK-NEXT: ptrue p0.b
388 ; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b
390 %prod = mul <vscale x 16 x i8> %b, %c
391 %res = add <vscale x 16 x i8> %a, %prod
392 ret <vscale x 16 x i8> %res
395 define <vscale x 8 x i16> @mla_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
396 ; CHECK-LABEL: mla_i16:
398 ; CHECK-NEXT: ptrue p0.h
399 ; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h
401 %prod = mul <vscale x 8 x i16> %b, %c
402 %res = add <vscale x 8 x i16> %a, %prod
403 ret <vscale x 8 x i16> %res
406 define <vscale x 4 x i32> @mla_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
407 ; CHECK-LABEL: mla_i32:
409 ; CHECK-NEXT: ptrue p0.s
410 ; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s
412 %prod = mul <vscale x 4 x i32> %b, %c
413 %res = add <vscale x 4 x i32> %a, %prod
414 ret <vscale x 4 x i32> %res
417 define <vscale x 2 x i64> @mla_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
418 ; CHECK-LABEL: mla_i64:
420 ; CHECK-NEXT: ptrue p0.d
421 ; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d
423 %prod = mul <vscale x 2 x i64> %b, %c
424 %res = add <vscale x 2 x i64> %a, %prod
425 ret <vscale x 2 x i64> %res
428 define <vscale x 16 x i8> @mla_i8_multiuse(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8>* %p) {
429 ; CHECK-LABEL: mla_i8_multiuse:
431 ; CHECK-NEXT: ptrue p0.b
432 ; CHECK-NEXT: mul z1.b, p0/m, z1.b, z0.b
433 ; CHECK-NEXT: add z0.b, z2.b, z1.b
434 ; CHECK-NEXT: st1b { z1.b }, p0, [x0]
436 %prod = mul <vscale x 16 x i8> %a, %b
437 store <vscale x 16 x i8> %prod, <vscale x 16 x i8>* %p
438 %res = add <vscale x 16 x i8> %c, %prod
439 ret <vscale x 16 x i8> %res
442 define <vscale x 16 x i8> @msb_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
443 ; CHECK-LABEL: msb_i8:
445 ; CHECK-NEXT: ptrue p0.b
446 ; CHECK-NEXT: msb z0.b, p0/m, z1.b, z2.b
448 %prod = mul <vscale x 16 x i8> %a, %b
449 %res = sub <vscale x 16 x i8> %c, %prod
450 ret <vscale x 16 x i8> %res
453 define <vscale x 8 x i16> @msb_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
454 ; CHECK-LABEL: msb_i16:
456 ; CHECK-NEXT: ptrue p0.h
457 ; CHECK-NEXT: msb z0.h, p0/m, z1.h, z2.h
459 %prod = mul <vscale x 8 x i16> %a, %b
460 %res = sub <vscale x 8 x i16> %c, %prod
461 ret <vscale x 8 x i16> %res
464 define <vscale x 4 x i32> @msb_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
465 ; CHECK-LABEL: msb_i32:
467 ; CHECK-NEXT: ptrue p0.s
468 ; CHECK-NEXT: msb z0.s, p0/m, z1.s, z2.s
470 %prod = mul <vscale x 4 x i32> %a, %b
471 %res = sub <vscale x 4 x i32> %c, %prod
472 ret <vscale x 4 x i32> %res
475 define <vscale x 2 x i64> @msb_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
476 ; CHECK-LABEL: msb_i64:
478 ; CHECK-NEXT: ptrue p0.d
479 ; CHECK-NEXT: msb z0.d, p0/m, z1.d, z2.d
481 %prod = mul <vscale x 2 x i64> %a, %b
482 %res = sub <vscale x 2 x i64> %c, %prod
483 ret <vscale x 2 x i64> %res
486 define <vscale x 16 x i8> @mls_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
487 ; CHECK-LABEL: mls_i8:
489 ; CHECK-NEXT: ptrue p0.b
490 ; CHECK-NEXT: mls z0.b, p0/m, z1.b, z2.b
492 %prod = mul <vscale x 16 x i8> %b, %c
493 %res = sub <vscale x 16 x i8> %a, %prod
494 ret <vscale x 16 x i8> %res
497 define <vscale x 8 x i16> @mls_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
498 ; CHECK-LABEL: mls_i16:
500 ; CHECK-NEXT: ptrue p0.h
501 ; CHECK-NEXT: mls z0.h, p0/m, z1.h, z2.h
503 %prod = mul <vscale x 8 x i16> %b, %c
504 %res = sub <vscale x 8 x i16> %a, %prod
505 ret <vscale x 8 x i16> %res
508 define <vscale x 4 x i32> @mls_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
509 ; CHECK-LABEL: mls_i32:
511 ; CHECK-NEXT: ptrue p0.s
512 ; CHECK-NEXT: mls z0.s, p0/m, z1.s, z2.s
514 %prod = mul <vscale x 4 x i32> %b, %c
515 %res = sub <vscale x 4 x i32> %a, %prod
516 ret <vscale x 4 x i32> %res
519 define <vscale x 2 x i64> @mls_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
520 ; CHECK-LABEL: mls_i64:
522 ; CHECK-NEXT: ptrue p0.d
523 ; CHECK-NEXT: mls z0.d, p0/m, z1.d, z2.d
525 %prod = mul <vscale x 2 x i64> %b, %c
526 %res = sub <vscale x 2 x i64> %a, %prod
527 ret <vscale x 2 x i64> %res
530 ; Test cases below have one of the add/sub operands as constant splat
532 define <vscale x 2 x i64> @muladd_i64_positiveAddend(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
533 ; CHECK-LABEL: muladd_i64_positiveAddend:
535 ; CHECK-NEXT: ptrue p0.d
536 ; CHECK-NEXT: mov z2.d, #0xffffffff
537 ; CHECK-NEXT: mad z0.d, p0/m, z1.d, z2.d
540 %1 = mul <vscale x 2 x i64> %a, %b
541 %2 = add <vscale x 2 x i64> %1, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 4294967295, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
542 ret <vscale x 2 x i64> %2
545 define <vscale x 2 x i64> @muladd_i64_negativeAddend(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
546 ; CHECK-LABEL: muladd_i64_negativeAddend:
548 ; CHECK-NEXT: ptrue p0.d
549 ; CHECK-NEXT: mov z2.d, #0xffffffff00000001
550 ; CHECK-NEXT: mad z0.d, p0/m, z1.d, z2.d
553 %1 = mul <vscale x 2 x i64> %a, %b
554 %2 = add <vscale x 2 x i64> %1, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -4294967295, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
555 ret <vscale x 2 x i64> %2
559 define <vscale x 4 x i32> @muladd_i32_positiveAddend(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
560 ; CHECK-LABEL: muladd_i32_positiveAddend:
562 ; CHECK-NEXT: ptrue p0.s
563 ; CHECK-NEXT: mov z2.s, #0x10000
564 ; CHECK-NEXT: mad z0.s, p0/m, z1.s, z2.s
567 %1 = mul <vscale x 4 x i32> %a, %b
568 %2 = add <vscale x 4 x i32> %1, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 65536, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
569 ret <vscale x 4 x i32> %2
572 define <vscale x 4 x i32> @muladd_i32_negativeAddend(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
573 ; CHECK-LABEL: muladd_i32_negativeAddend:
575 ; CHECK-NEXT: ptrue p0.s
576 ; CHECK-NEXT: mov z2.s, #0xffff0000
577 ; CHECK-NEXT: mad z0.s, p0/m, z1.s, z2.s
580 %1 = mul <vscale x 4 x i32> %a, %b
581 %2 = add <vscale x 4 x i32> %1, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -65536, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
582 ret <vscale x 4 x i32> %2
585 define <vscale x 8 x i16> @muladd_i16_positiveAddend(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
586 ; CHECK-LABEL: muladd_i16_positiveAddend:
588 ; CHECK-NEXT: ptrue p0.h
589 ; CHECK-NEXT: mov z2.h, #255 // =0xff
590 ; CHECK-NEXT: mad z0.h, p0/m, z1.h, z2.h
593 %1 = mul <vscale x 8 x i16> %a, %b
594 %2 = add <vscale x 8 x i16> %1, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 255, i16 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
595 ret <vscale x 8 x i16> %2
598 define <vscale x 8 x i16> @muladd_i16_negativeAddend(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
599 ; CHECK-LABEL: muladd_i16_negativeAddend:
601 ; CHECK-NEXT: ptrue p0.h
602 ; CHECK-NEXT: mov z2.h, #-255 // =0xffffffffffffff01
603 ; CHECK-NEXT: mad z0.h, p0/m, z1.h, z2.h
606 %1 = mul <vscale x 8 x i16> %a, %b
607 %2 = add <vscale x 8 x i16> %1, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -255, i16 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
608 ret <vscale x 8 x i16> %2
611 define <vscale x 16 x i8> @muladd_i8_positiveAddend(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
612 ; CHECK-LABEL: muladd_i8_positiveAddend:
614 ; CHECK-NEXT: ptrue p0.b
615 ; CHECK-NEXT: mov z2.b, #15 // =0xf
616 ; CHECK-NEXT: mad z0.b, p0/m, z1.b, z2.b
619 %1 = mul <vscale x 16 x i8> %a, %b
620 %2 = add <vscale x 16 x i8> %1, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 15, i8 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
621 ret <vscale x 16 x i8> %2
624 define <vscale x 16 x i8> @muladd_i8_negativeAddend(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
625 ; CHECK-LABEL: muladd_i8_negativeAddend:
627 ; CHECK-NEXT: ptrue p0.b
628 ; CHECK-NEXT: mov z2.b, #-15 // =0xfffffffffffffff1
629 ; CHECK-NEXT: mad z0.b, p0/m, z1.b, z2.b
632 %1 = mul <vscale x 16 x i8> %a, %b
633 %2 = add <vscale x 16 x i8> %1, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -15, i8 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
634 ret <vscale x 16 x i8> %2
637 define <vscale x 2 x i64> @mulsub_i64_positiveAddend(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
638 ; CHECK-LABEL: mulsub_i64_positiveAddend:
640 ; CHECK-NEXT: ptrue p0.d
641 ; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
642 ; CHECK-NEXT: mov z1.d, #0xffffffff
643 ; CHECK-NEXT: sub z0.d, z0.d, z1.d
646 %1 = mul <vscale x 2 x i64> %a, %b
647 %2 = sub <vscale x 2 x i64> %1, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 4294967295, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
648 ret <vscale x 2 x i64> %2
651 define <vscale x 2 x i64> @mulsub_i64_negativeAddend(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
652 ; CHECK-LABEL: mulsub_i64_negativeAddend:
654 ; CHECK-NEXT: ptrue p0.d
655 ; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
656 ; CHECK-NEXT: mov z1.d, #0xffffffff00000001
657 ; CHECK-NEXT: sub z0.d, z0.d, z1.d
660 %1 = mul <vscale x 2 x i64> %a, %b
661 %2 = sub <vscale x 2 x i64> %1, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -4294967295, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
662 ret <vscale x 2 x i64> %2
666 define <vscale x 4 x i32> @mulsub_i32_positiveAddend(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
667 ; CHECK-LABEL: mulsub_i32_positiveAddend:
669 ; CHECK-NEXT: ptrue p0.s
670 ; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
671 ; CHECK-NEXT: mov z1.s, #0x10000
672 ; CHECK-NEXT: sub z0.s, z0.s, z1.s
675 %1 = mul <vscale x 4 x i32> %a, %b
676 %2 = sub <vscale x 4 x i32> %1, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 65536, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
677 ret <vscale x 4 x i32> %2
680 define <vscale x 4 x i32> @mulsub_i32_negativeAddend(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
681 ; CHECK-LABEL: mulsub_i32_negativeAddend:
683 ; CHECK-NEXT: ptrue p0.s
684 ; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
685 ; CHECK-NEXT: mov z1.s, #0xffff0000
686 ; CHECK-NEXT: sub z0.s, z0.s, z1.s
689 %1 = mul <vscale x 4 x i32> %a, %b
690 %2 = sub <vscale x 4 x i32> %1, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -65536, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
691 ret <vscale x 4 x i32> %2
694 define <vscale x 8 x i16> @mulsub_i16_positiveAddend(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
695 ; CHECK-LABEL: mulsub_i16_positiveAddend:
697 ; CHECK-NEXT: ptrue p0.h
698 ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
699 ; CHECK-NEXT: sub z0.h, z0.h, #255 // =0xff
702 %1 = mul <vscale x 8 x i16> %a, %b
703 %2 = sub <vscale x 8 x i16> %1, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 255, i16 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
704 ret <vscale x 8 x i16> %2
707 define <vscale x 8 x i16> @mulsub_i16_negativeAddend(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
708 ; CHECK-LABEL: mulsub_i16_negativeAddend:
710 ; CHECK-NEXT: ptrue p0.h
711 ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
712 ; CHECK-NEXT: mov z1.h, #-255 // =0xffffffffffffff01
713 ; CHECK-NEXT: sub z0.h, z0.h, z1.h
716 %1 = mul <vscale x 8 x i16> %a, %b
717 %2 = sub <vscale x 8 x i16> %1, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -255, i16 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
718 ret <vscale x 8 x i16> %2
721 define <vscale x 16 x i8> @mulsub_i8_positiveAddend(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
722 ; CHECK-LABEL: mulsub_i8_positiveAddend:
724 ; CHECK-NEXT: ptrue p0.b
725 ; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b
726 ; CHECK-NEXT: sub z0.b, z0.b, #15 // =0xf
729 %1 = mul <vscale x 16 x i8> %a, %b
730 %2 = sub <vscale x 16 x i8> %1, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 15, i8 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
731 ret <vscale x 16 x i8> %2
734 define <vscale x 16 x i8> @mulsub_i8_negativeAddend(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
735 ; CHECK-LABEL: mulsub_i8_negativeAddend:
737 ; CHECK-NEXT: ptrue p0.b
738 ; CHECK-NEXT: mul z0.b, p0/m, z0.b, z1.b
739 ; CHECK-NEXT: sub z0.b, z0.b, #241 // =0xf1
742 %1 = mul <vscale x 16 x i8> %a, %b
743 %2 = sub <vscale x 16 x i8> %1, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -15, i8 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
744 ret <vscale x 16 x i8> %2
747 ; TOFIX: Should generate msb for mul+sub in this case. Shuffling operand of sub generates the required msb instruction.
748 define <vscale x 8 x i16> @multiple_fused_ops(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
749 ; CHECK-LABEL: multiple_fused_ops:
751 ; CHECK-NEXT: ptrue p0.h
752 ; CHECK-NEXT: mov w8, #200 // =0xc8
753 ; CHECK-NEXT: mov z2.h, w8
754 ; CHECK-NEXT: mla z2.h, p0/m, z0.h, z1.h
755 ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h
756 ; CHECK-NEXT: sub z0.h, z0.h, z1.h
759 %1 = mul <vscale x 8 x i16> %a, %b
760 %2 = add <vscale x 8 x i16> %1, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 200, i16 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
761 %3 = mul <vscale x 8 x i16> %2, %a
762 %4 = sub <vscale x 8 x i16> %3, %b
763 ret <vscale x 8 x i16> %4
766 define void @mad_in_loop(ptr %dst, ptr %src1, ptr %src2, i32 %n) {
767 ; CHECK-LABEL: mad_in_loop:
768 ; CHECK: // %bb.0: // %entry
769 ; CHECK-NEXT: cmp w3, #1
770 ; CHECK-NEXT: b.lt .LBB70_3
771 ; CHECK-NEXT: // %bb.1: // %for.body.preheader
772 ; CHECK-NEXT: mov w9, w3
773 ; CHECK-NEXT: ptrue p1.s
774 ; CHECK-NEXT: mov z0.s, #1 // =0x1
775 ; CHECK-NEXT: whilelo p0.s, xzr, x9
776 ; CHECK-NEXT: mov x8, xzr
777 ; CHECK-NEXT: cntw x10
778 ; CHECK-NEXT: .LBB70_2: // %vector.body
779 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
780 ; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]
781 ; CHECK-NEXT: ld1w { z2.s }, p0/z, [x2, x8, lsl #2]
782 ; CHECK-NEXT: mad z1.s, p1/m, z2.s, z0.s
783 ; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
784 ; CHECK-NEXT: add x8, x8, x10
785 ; CHECK-NEXT: whilelo p0.s, x8, x9
786 ; CHECK-NEXT: b.mi .LBB70_2
787 ; CHECK-NEXT: .LBB70_3: // %for.cond.cleanup
790 %cmp9 = icmp sgt i32 %n, 0
791 br i1 %cmp9, label %for.body.preheader, label %for.cond.cleanup
793 for.body.preheader: ; preds = %entry
794 %wide.trip.count = zext i32 %n to i64
795 %active.lane.mask.entry = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 %wide.trip.count)
796 %0 = tail call i64 @llvm.vscale.i64()
797 %1 = shl nuw nsw i64 %0, 2
798 br label %vector.body
800 vector.body: ; preds = %vector.body, %for.body.preheader
801 %index = phi i64 [ 0, %for.body.preheader ], [ %index.next, %vector.body ]
802 %active.lane.mask = phi <vscale x 4 x i1> [ %active.lane.mask.entry, %for.body.preheader ], [ %active.lane.mask.next, %vector.body ]
803 %2 = getelementptr inbounds i32, ptr %src1, i64 %index
804 %wide.masked.load = tail call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr %2, i32 4, <vscale x 4 x i1> %active.lane.mask, <vscale x 4 x i32> poison)
805 %3 = getelementptr inbounds i32, ptr %src2, i64 %index
806 %wide.masked.load12 = tail call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr %3, i32 4, <vscale x 4 x i1> %active.lane.mask, <vscale x 4 x i32> poison)
807 %4 = mul nsw <vscale x 4 x i32> %wide.masked.load12, %wide.masked.load
808 %5 = add nsw <vscale x 4 x i32> %4, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
809 %6 = getelementptr inbounds i32, ptr %dst, i64 %index
810 tail call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> %5, ptr %6, i32 4, <vscale x 4 x i1> %active.lane.mask)
811 %index.next = add i64 %index, %1
812 %active.lane.mask.next = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 %index.next, i64 %wide.trip.count)
813 %7 = extractelement <vscale x 4 x i1> %active.lane.mask.next, i64 0
814 br i1 %7, label %vector.body, label %for.cond.cleanup
816 for.cond.cleanup: ; preds = %vector.body, %entry
820 declare i64 @llvm.vscale.i64()
821 declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64, i64)
822 declare <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr nocapture, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i32>)
823 declare void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32>, ptr nocapture, i32 immarg, <vscale x 4 x i1>)
825 declare <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
826 declare <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
827 declare <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
828 declare <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
830 declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
831 declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
832 declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
833 declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
835 declare <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
836 declare <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
837 declare <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
838 declare <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
840 declare <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
841 declare <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
842 declare <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
843 declare <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
845 declare <vscale x 32 x i8> @llvm.abs.nxv32i8(<vscale x 32 x i8>, i1)
846 declare <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8>, i1)
847 declare <vscale x 4 x i16> @llvm.abs.nxv4i16(<vscale x 4 x i16>, i1)
848 declare <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16>, i1)
849 declare <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32>, i1)
850 declare <vscale x 8 x i64> @llvm.abs.nxv8i64(<vscale x 8 x i64>, i1)
851 declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)