| blob | bd954df190477bf4c506073ec5dfbb3728e98411 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
4 target triple = "aarch64-unknown-linux-gnu"
6 define <4 x i8> @load_v4i8(ptr %a) {
7 ; CHECK-LABEL: load_v4i8:
8 ; CHECK: // %bb.0:
9 ; CHECK-NEXT: ptrue p0.h, vl4
10 ; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
11 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
12 ; CHECK-NEXT: ret
13 %load = load <4 x i8>, ptr %a
14 ret <4 x i8> %load
15 }
17 define <8 x i8> @load_v8i8(ptr %a) {
18 ; CHECK-LABEL: load_v8i8:
19 ; CHECK: // %bb.0:
20 ; CHECK-NEXT: ldr d0, [x0]
21 ; CHECK-NEXT: ret
22 %load = load <8 x i8>, ptr %a
23 ret <8 x i8> %load
24 }
26 define <16 x i8> @load_v16i8(ptr %a) {
27 ; CHECK-LABEL: load_v16i8:
28 ; CHECK: // %bb.0:
29 ; CHECK-NEXT: ldr q0, [x0]
30 ; CHECK-NEXT: ret
31 %load = load <16 x i8>, ptr %a
32 ret <16 x i8> %load
33 }
35 define <32 x i8> @load_v32i8(ptr %a) {
36 ; CHECK-LABEL: load_v32i8:
37 ; CHECK: // %bb.0:
38 ; CHECK-NEXT: ldp q0, q1, [x0]
39 ; CHECK-NEXT: ret
40 %load = load <32 x i8>, ptr %a
41 ret <32 x i8> %load
42 }
44 define <2 x i16> @load_v2i16(ptr %a) {
45 ; CHECK-LABEL: load_v2i16:
46 ; CHECK: // %bb.0:
47 ; CHECK-NEXT: sub sp, sp, #16
48 ; CHECK-NEXT: .cfi_def_cfa_offset 16
49 ; CHECK-NEXT: ldrh w8, [x0, #2]
50 ; CHECK-NEXT: str w8, [sp, #12]
51 ; CHECK-NEXT: ldrh w8, [x0]
52 ; CHECK-NEXT: str w8, [sp, #8]
53 ; CHECK-NEXT: ldr d0, [sp, #8]
54 ; CHECK-NEXT: add sp, sp, #16
55 ; CHECK-NEXT: ret
56 %load = load <2 x i16>, ptr %a
57 ret <2 x i16> %load
58 }
60 define <2 x half> @load_v2f16(ptr %a) {
61 ; CHECK-LABEL: load_v2f16:
62 ; CHECK: // %bb.0:
63 ; CHECK-NEXT: ldr s0, [x0]
64 ; CHECK-NEXT: ret
65 %load = load <2 x half>, ptr %a
66 ret <2 x half> %load
67 }
69 define <4 x i16> @load_v4i16(ptr %a) {
70 ; CHECK-LABEL: load_v4i16:
71 ; CHECK: // %bb.0:
72 ; CHECK-NEXT: ldr d0, [x0]
73 ; CHECK-NEXT: ret
74 %load = load <4 x i16>, ptr %a
75 ret <4 x i16> %load
76 }
78 define <4 x half> @load_v4f16(ptr %a) {
79 ; CHECK-LABEL: load_v4f16:
80 ; CHECK: // %bb.0:
81 ; CHECK-NEXT: ldr d0, [x0]
82 ; CHECK-NEXT: ret
83 %load = load <4 x half>, ptr %a
84 ret <4 x half> %load
85 }
87 define <8 x i16> @load_v8i16(ptr %a) {
88 ; CHECK-LABEL: load_v8i16:
89 ; CHECK: // %bb.0:
90 ; CHECK-NEXT: ldr q0, [x0]
91 ; CHECK-NEXT: ret
92 %load = load <8 x i16>, ptr %a
93 ret <8 x i16> %load
94 }
96 define <8 x half> @load_v8f16(ptr %a) {
97 ; CHECK-LABEL: load_v8f16:
98 ; CHECK: // %bb.0:
99 ; CHECK-NEXT: ldr q0, [x0]
100 ; CHECK-NEXT: ret
101 %load = load <8 x half>, ptr %a
102 ret <8 x half> %load
103 }
105 define <16 x i16> @load_v16i16(ptr %a) {
106 ; CHECK-LABEL: load_v16i16:
107 ; CHECK: // %bb.0:
108 ; CHECK-NEXT: ldp q0, q1, [x0]
109 ; CHECK-NEXT: ret
110 %load = load <16 x i16>, ptr %a
111 ret <16 x i16> %load
112 }
114 define <16 x half> @load_v16f16(ptr %a) {
115 ; CHECK-LABEL: load_v16f16:
116 ; CHECK: // %bb.0:
117 ; CHECK-NEXT: ldp q0, q1, [x0]
118 ; CHECK-NEXT: ret
119 %load = load <16 x half>, ptr %a
120 ret <16 x half> %load
121 }
123 define <2 x i32> @load_v2i32(ptr %a) {
124 ; CHECK-LABEL: load_v2i32:
125 ; CHECK: // %bb.0:
126 ; CHECK-NEXT: ldr d0, [x0]
127 ; CHECK-NEXT: ret
128 %load = load <2 x i32>, ptr %a
129 ret <2 x i32> %load
130 }
132 define <2 x float> @load_v2f32(ptr %a) {
133 ; CHECK-LABEL: load_v2f32:
134 ; CHECK: // %bb.0:
135 ; CHECK-NEXT: ldr d0, [x0]
136 ; CHECK-NEXT: ret
137 %load = load <2 x float>, ptr %a
138 ret <2 x float> %load
139 }
141 define <4 x i32> @load_v4i32(ptr %a) {
142 ; CHECK-LABEL: load_v4i32:
143 ; CHECK: // %bb.0:
144 ; CHECK-NEXT: ldr q0, [x0]
145 ; CHECK-NEXT: ret
146 %load = load <4 x i32>, ptr %a
147 ret <4 x i32> %load
148 }
150 define <4 x float> @load_v4f32(ptr %a) {
151 ; CHECK-LABEL: load_v4f32:
152 ; CHECK: // %bb.0:
153 ; CHECK-NEXT: ldr q0, [x0]
154 ; CHECK-NEXT: ret
155 %load = load <4 x float>, ptr %a
156 ret <4 x float> %load
157 }
159 define <8 x i32> @load_v8i32(ptr %a) {
160 ; CHECK-LABEL: load_v8i32:
161 ; CHECK: // %bb.0:
162 ; CHECK-NEXT: ldp q0, q1, [x0]
163 ; CHECK-NEXT: ret
164 %load = load <8 x i32>, ptr %a
165 ret <8 x i32> %load
166 }
168 define <8 x float> @load_v8f32(ptr %a) {
169 ; CHECK-LABEL: load_v8f32:
170 ; CHECK: // %bb.0:
171 ; CHECK-NEXT: ldp q0, q1, [x0]
172 ; CHECK-NEXT: ret
173 %load = load <8 x float>, ptr %a
174 ret <8 x float> %load
175 }
177 define <1 x i64> @load_v1i64(ptr %a) {
178 ; CHECK-LABEL: load_v1i64:
179 ; CHECK: // %bb.0:
180 ; CHECK-NEXT: ldr d0, [x0]
181 ; CHECK-NEXT: ret
182 %load = load <1 x i64>, ptr %a
183 ret <1 x i64> %load
184 }
186 define <1 x double> @load_v1f64(ptr %a) {
187 ; CHECK-LABEL: load_v1f64:
188 ; CHECK: // %bb.0:
189 ; CHECK-NEXT: ldr d0, [x0]
190 ; CHECK-NEXT: ret
191 %load = load <1 x double>, ptr %a
192 ret <1 x double> %load
193 }
195 define <2 x i64> @load_v2i64(ptr %a) {
196 ; CHECK-LABEL: load_v2i64:
197 ; CHECK: // %bb.0:
198 ; CHECK-NEXT: ldr q0, [x0]
199 ; CHECK-NEXT: ret
200 %load = load <2 x i64>, ptr %a
201 ret <2 x i64> %load
202 }
204 define <2 x double> @load_v2f64(ptr %a) {
205 ; CHECK-LABEL: load_v2f64:
206 ; CHECK: // %bb.0:
207 ; CHECK-NEXT: ldr q0, [x0]
208 ; CHECK-NEXT: ret
209 %load = load <2 x double>, ptr %a
210 ret <2 x double> %load
211 }
213 define <4 x i64> @load_v4i64(ptr %a) {
214 ; CHECK-LABEL: load_v4i64:
215 ; CHECK: // %bb.0:
216 ; CHECK-NEXT: ldp q0, q1, [x0]
217 ; CHECK-NEXT: ret
218 %load = load <4 x i64>, ptr %a
219 ret <4 x i64> %load
220 }
222 define <4 x double> @load_v4f64(ptr %a) {
223 ; CHECK-LABEL: load_v4f64:
224 ; CHECK: // %bb.0:
225 ; CHECK-NEXT: ldp q0, q1, [x0]
226 ; CHECK-NEXT: ret
227 %load = load <4 x double>, ptr %a
228 ret <4 x double> %load
229 }