| blob | a2bfc3c438da36497a0438b7f253ddc13bbf1c54 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-SD
3 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-SD
4 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-GI
5 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-GI
7 ; CHECK-NOFP-GI: warning: Instruction selection used fallback path for test_v11f16
8 ; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
9 ; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
10 ; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
11 ; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
12 ;
13 ; CHECK-FP-GI: warning: Instruction selection used fallback path for test_v11f16
14 ; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf
15 ; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32
16 ; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v3f32_ninf
17 ; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v2f128
19 declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
20 declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
21 declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
22 declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
24 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
25 declare half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)
26 declare half @llvm.vector.reduce.fmin.v16f16(<16 x half> %a)
27 declare float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a)
28 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
29 declare float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a)
30 declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
31 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
32 declare double @llvm.vector.reduce.fmin.v4f64(<4 x double> %a)
34 declare half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
35 declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
36 declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
38 define half @test_v1f16(<1 x half> %a) nounwind {
39 ; CHECK-LABEL: test_v1f16:
40 ; CHECK: // %bb.0:
41 ; CHECK-NEXT: ret
42 %b = call nnan half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)
43 ret half %b
44 }
46 define float @test_v1f32(<1 x float> %a) nounwind {
47 ; CHECK-NOFP-SD-LABEL: test_v1f32:
48 ; CHECK-NOFP-SD: // %bb.0:
49 ; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
50 ; CHECK-NOFP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
51 ; CHECK-NOFP-SD-NEXT: ret
52 ;
53 ; CHECK-FP-SD-LABEL: test_v1f32:
54 ; CHECK-FP-SD: // %bb.0:
55 ; CHECK-FP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
56 ; CHECK-FP-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
57 ; CHECK-FP-SD-NEXT: ret
58 ;
59 ; CHECK-NOFP-GI-LABEL: test_v1f32:
60 ; CHECK-NOFP-GI: // %bb.0:
61 ; CHECK-NOFP-GI-NEXT: fmov x8, d0
62 ; CHECK-NOFP-GI-NEXT: fmov s0, w8
63 ; CHECK-NOFP-GI-NEXT: ret
64 ;
65 ; CHECK-FP-GI-LABEL: test_v1f32:
66 ; CHECK-FP-GI: // %bb.0:
67 ; CHECK-FP-GI-NEXT: fmov x8, d0
68 ; CHECK-FP-GI-NEXT: fmov s0, w8
69 ; CHECK-FP-GI-NEXT: ret
70 %b = call nnan float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)
71 ret float %b
72 }
74 define double @test_v1f64(<1 x double> %a) nounwind {
75 ; CHECK-LABEL: test_v1f64:
76 ; CHECK: // %bb.0:
77 ; CHECK-NEXT: ret
78 %b = call nnan double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)
79 ret double %b
80 }
82 define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
83 ; CHECK-LABEL: test_v1f128:
84 ; CHECK: // %bb.0:
85 ; CHECK-NEXT: ret
86 %b = call nnan fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)
87 ret fp128 %b
88 }
90 define half @test_v4f16(<4 x half> %a) nounwind {
91 ; CHECK-NOFP-SD-LABEL: test_v4f16:
92 ; CHECK-NOFP-SD: // %bb.0:
93 ; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
94 ; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
95 ; CHECK-NOFP-SD-NEXT: fcvt s2, h0
96 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
97 ; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1
98 ; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
99 ; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
100 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
101 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
102 ; CHECK-NOFP-SD-NEXT: fcvt s0, h0
103 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
104 ; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
105 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
106 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
107 ; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
108 ; CHECK-NOFP-SD-NEXT: fcvt h0, s0
109 ; CHECK-NOFP-SD-NEXT: ret
110 ;
111 ; CHECK-FP-LABEL: test_v4f16:
112 ; CHECK-FP: // %bb.0:
113 ; CHECK-FP-NEXT: fminnmv h0, v0.4h
114 ; CHECK-FP-NEXT: ret
115 ;
116 ; CHECK-NOFP-GI-LABEL: test_v4f16:
117 ; CHECK-NOFP-GI: // %bb.0:
118 ; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
119 ; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
120 ; CHECK-NOFP-GI-NEXT: fcvt h0, s0
121 ; CHECK-NOFP-GI-NEXT: ret
122 %b = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
123 ret half %b
124 }
126 define half @test_v4f16_ninf(<4 x half> %a) nounwind {
127 ; CHECK-NOFP-SD-LABEL: test_v4f16_ninf:
128 ; CHECK-NOFP-SD: // %bb.0:
129 ; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0
130 ; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
131 ; CHECK-NOFP-SD-NEXT: fcvt s2, h0
132 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
133 ; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1
134 ; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
135 ; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]
136 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
137 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
138 ; CHECK-NOFP-SD-NEXT: fcvt s0, h0
139 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
140 ; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
141 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
142 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
143 ; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
144 ; CHECK-NOFP-SD-NEXT: fcvt h0, s0
145 ; CHECK-NOFP-SD-NEXT: ret
146 ;
147 ; CHECK-FP-LABEL: test_v4f16_ninf:
148 ; CHECK-FP: // %bb.0:
149 ; CHECK-FP-NEXT: fminnmv h0, v0.4h
150 ; CHECK-FP-NEXT: ret
151 ;
152 ; CHECK-NOFP-GI-LABEL: test_v4f16_ninf:
153 ; CHECK-NOFP-GI: // %bb.0:
154 ; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h
155 ; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
156 ; CHECK-NOFP-GI-NEXT: fcvt h0, s0
157 ; CHECK-NOFP-GI-NEXT: ret
158 %b = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
159 ret half %b
160 }
162 define half @test_v8f16(<8 x half> %a) nounwind {
163 ; CHECK-NOFP-SD-LABEL: test_v8f16:
164 ; CHECK-NOFP-SD: // %bb.0:
165 ; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]
166 ; CHECK-NOFP-SD-NEXT: fcvt s2, h0
167 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
168 ; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1
169 ; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]
170 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
171 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
172 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
173 ; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
174 ; CHECK-NOFP-SD-NEXT: mov h2, v0.h[3]
175 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
176 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
177 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
178 ; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
179 ; CHECK-NOFP-SD-NEXT: mov h2, v0.h[4]
180 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
181 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
182 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
183 ; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
184 ; CHECK-NOFP-SD-NEXT: mov h2, v0.h[5]
185 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
186 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
187 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
188 ; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
189 ; CHECK-NOFP-SD-NEXT: mov h2, v0.h[6]
190 ; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
191 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
192 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
193 ; CHECK-NOFP-SD-NEXT: fcvt s0, h0
194 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
195 ; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2
196 ; CHECK-NOFP-SD-NEXT: fcvt h1, s1
197 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
198 ; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
199 ; CHECK-NOFP-SD-NEXT: fcvt h0, s0
200 ; CHECK-NOFP-SD-NEXT: ret
201 ;
202 ; CHECK-FP-LABEL: test_v8f16:
203 ; CHECK-FP: // %bb.0:
204 ; CHECK-FP-NEXT: fminnmv h0, v0.8h
205 ; CHECK-FP-NEXT: ret
206 ;
207 ; CHECK-NOFP-GI-LABEL: test_v8f16:
208 ; CHECK-NOFP-GI: // %bb.0:
209 ; CHECK-NOFP-GI-NEXT: fcvtl v1.4s, v0.4h
210 ; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
211 ; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v1.4s, v0.4s
212 ; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
213 ; CHECK-NOFP-GI-NEXT: fcvt h0, s0
214 ; CHECK-NOFP-GI-NEXT: ret
215 %b = call nnan half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)
216 ret half %b
217 }
219 define half @test_v16f16(<16 x half> %a) nounwind {
220 ; CHECK-NOFP-SD-LABEL: test_v16f16:
221 ; CHECK-NOFP-SD: // %bb.0:
222 ; CHECK-NOFP-SD-NEXT: mov h2, v1.h[1]
223 ; CHECK-NOFP-SD-NEXT: mov h3, v0.h[1]
224 ; CHECK-NOFP-SD-NEXT: fcvt s4, h1
225 ; CHECK-NOFP-SD-NEXT: fcvt s5, h0
226 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
227 ; CHECK-NOFP-SD-NEXT: fcvt s3, h3
228 ; CHECK-NOFP-SD-NEXT: fcmp s3, s2
229 ; CHECK-NOFP-SD-NEXT: fcsel s2, s3, s2, lt
230 ; CHECK-NOFP-SD-NEXT: fcmp s5, s4
231 ; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
232 ; CHECK-NOFP-SD-NEXT: mov h4, v1.h[2]
233 ; CHECK-NOFP-SD-NEXT: mov h5, v0.h[2]
234 ; CHECK-NOFP-SD-NEXT: fcvt h2, s2
235 ; CHECK-NOFP-SD-NEXT: fcvt h3, s3
236 ; CHECK-NOFP-SD-NEXT: fcvt s4, h4
237 ; CHECK-NOFP-SD-NEXT: fcvt s5, h5
238 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
239 ; CHECK-NOFP-SD-NEXT: fcvt s3, h3
240 ; CHECK-NOFP-SD-NEXT: fcmp s5, s4
241 ; CHECK-NOFP-SD-NEXT: fminnm s2, s3, s2
242 ; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
243 ; CHECK-NOFP-SD-NEXT: mov h4, v1.h[3]
244 ; CHECK-NOFP-SD-NEXT: mov h5, v0.h[3]
245 ; CHECK-NOFP-SD-NEXT: fcvt h2, s2
246 ; CHECK-NOFP-SD-NEXT: fcvt h3, s3
247 ; CHECK-NOFP-SD-NEXT: fcvt s4, h4
248 ; CHECK-NOFP-SD-NEXT: fcvt s5, h5
249 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
250 ; CHECK-NOFP-SD-NEXT: fcvt s3, h3
251 ; CHECK-NOFP-SD-NEXT: fcmp s5, s4
252 ; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
253 ; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
254 ; CHECK-NOFP-SD-NEXT: mov h4, v1.h[4]
255 ; CHECK-NOFP-SD-NEXT: mov h5, v0.h[4]
256 ; CHECK-NOFP-SD-NEXT: fcvt h2, s2
257 ; CHECK-NOFP-SD-NEXT: fcvt h3, s3
258 ; CHECK-NOFP-SD-NEXT: fcvt s4, h4
259 ; CHECK-NOFP-SD-NEXT: fcvt s5, h5
260 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
261 ; CHECK-NOFP-SD-NEXT: fcvt s3, h3
262 ; CHECK-NOFP-SD-NEXT: fcmp s5, s4
263 ; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
264 ; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
265 ; CHECK-NOFP-SD-NEXT: mov h4, v1.h[5]
266 ; CHECK-NOFP-SD-NEXT: mov h5, v0.h[5]
267 ; CHECK-NOFP-SD-NEXT: fcvt h2, s2
268 ; CHECK-NOFP-SD-NEXT: fcvt h3, s3
269 ; CHECK-NOFP-SD-NEXT: fcvt s4, h4
270 ; CHECK-NOFP-SD-NEXT: fcvt s5, h5
271 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
272 ; CHECK-NOFP-SD-NEXT: fcvt s3, h3
273 ; CHECK-NOFP-SD-NEXT: fcmp s5, s4
274 ; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
275 ; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
276 ; CHECK-NOFP-SD-NEXT: mov h4, v1.h[6]
277 ; CHECK-NOFP-SD-NEXT: mov h5, v0.h[6]
278 ; CHECK-NOFP-SD-NEXT: mov h1, v1.h[7]
279 ; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
280 ; CHECK-NOFP-SD-NEXT: fcvt h2, s2
281 ; CHECK-NOFP-SD-NEXT: fcvt h3, s3
282 ; CHECK-NOFP-SD-NEXT: fcvt s4, h4
283 ; CHECK-NOFP-SD-NEXT: fcvt s5, h5
284 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
285 ; CHECK-NOFP-SD-NEXT: fcvt s0, h0
286 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
287 ; CHECK-NOFP-SD-NEXT: fcvt s3, h3
288 ; CHECK-NOFP-SD-NEXT: fcmp s5, s4
289 ; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
290 ; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, lt
291 ; CHECK-NOFP-SD-NEXT: fcmp s0, s1
292 ; CHECK-NOFP-SD-NEXT: fcsel s0, s0, s1, lt
293 ; CHECK-NOFP-SD-NEXT: fcvt h2, s2
294 ; CHECK-NOFP-SD-NEXT: fcvt h3, s3
295 ; CHECK-NOFP-SD-NEXT: fcvt h0, s0
296 ; CHECK-NOFP-SD-NEXT: fcvt s2, h2
297 ; CHECK-NOFP-SD-NEXT: fcvt s3, h3
298 ; CHECK-NOFP-SD-NEXT: fcvt s0, h0
299 ; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3
300 ; CHECK-NOFP-SD-NEXT: fcvt h1, s2
301 ; CHECK-NOFP-SD-NEXT: fcvt s1, h1
302 ; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0
303 ; CHECK-NOFP-SD-NEXT: fcvt h0, s0
304 ; CHECK-NOFP-SD-NEXT: ret
305 ;
306 ; CHECK-FP-LABEL: test_v16f16:
307 ; CHECK-FP: // %bb.0:
308 ; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
309 ; CHECK-FP-NEXT: fminnmv h0, v0.8h
310 ; CHECK-FP-NEXT: ret
311 ;
312 ; CHECK-NOFP-GI-LABEL: test_v16f16:
313 ; CHECK-NOFP-GI: // %bb.0:
314 ; CHECK-NOFP-GI-NEXT: fcvtl v2.4s, v0.4h
315 ; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h
316 ; CHECK-NOFP-GI-NEXT: fcvtl v3.4s, v1.4h
317 ; CHECK-NOFP-GI-NEXT: fcvtl2 v1.4s, v1.8h
318 ; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v2.4s, v0.4s
319 ; CHECK-NOFP-GI-NEXT: fminnm v1.4s, v3.4s, v1.4s
320 ; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
321 ; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
322 ; CHECK-NOFP-GI-NEXT: fcvt h0, s0
323 ; CHECK-NOFP-GI-NEXT: ret
324 %b = call nnan half @llvm.vector.reduce.fmin.v16f16(<16 x half> %a)
325 ret half %b
326 }
328 define float @test_v2f32_ninf(<2 x float> %a) nounwind {
329 ; CHECK-LABEL: test_v2f32_ninf:
330 ; CHECK: // %bb.0:
331 ; CHECK-NEXT: fminnmp s0, v0.2s
332 ; CHECK-NEXT: ret
333 %b = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a)
334 ret float %b
335 }
337 define float @test_v4f32_ninf(<4 x float> %a) nounwind {
338 ; CHECK-LABEL: test_v4f32_ninf:
339 ; CHECK: // %bb.0:
340 ; CHECK-NEXT: fminnmv s0, v0.4s
341 ; CHECK-NEXT: ret
342 %b = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
343 ret float %b
344 }
346 define float @test_v8f32(<8 x float> %a) nounwind {
347 ; CHECK-LABEL: test_v8f32:
348 ; CHECK: // %bb.0:
349 ; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
350 ; CHECK-NEXT: fminnmv s0, v0.4s
351 ; CHECK-NEXT: ret
352 %b = call nnan float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a)
353 ret float %b
354 }
356 define float @test_v16f32(<16 x float> %a) nounwind {
357 ; CHECK-NOFP-SD-LABEL: test_v16f32:
358 ; CHECK-NOFP-SD: // %bb.0:
359 ; CHECK-NOFP-SD-NEXT: fminnm v1.4s, v1.4s, v3.4s
360 ; CHECK-NOFP-SD-NEXT: fminnm v0.4s, v0.4s, v2.4s
361 ; CHECK-NOFP-SD-NEXT: fminnm v0.4s, v0.4s, v1.4s
362 ; CHECK-NOFP-SD-NEXT: fminnmv s0, v0.4s
363 ; CHECK-NOFP-SD-NEXT: ret
364 ;
365 ; CHECK-FP-SD-LABEL: test_v16f32:
366 ; CHECK-FP-SD: // %bb.0:
367 ; CHECK-FP-SD-NEXT: fminnm v1.4s, v1.4s, v3.4s
368 ; CHECK-FP-SD-NEXT: fminnm v0.4s, v0.4s, v2.4s
369 ; CHECK-FP-SD-NEXT: fminnm v0.4s, v0.4s, v1.4s
370 ; CHECK-FP-SD-NEXT: fminnmv s0, v0.4s
371 ; CHECK-FP-SD-NEXT: ret
372 ;
373 ; CHECK-NOFP-GI-LABEL: test_v16f32:
374 ; CHECK-NOFP-GI: // %bb.0:
375 ; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
376 ; CHECK-NOFP-GI-NEXT: fminnm v1.4s, v2.4s, v3.4s
377 ; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
378 ; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s
379 ; CHECK-NOFP-GI-NEXT: ret
380 ;
381 ; CHECK-FP-GI-LABEL: test_v16f32:
382 ; CHECK-FP-GI: // %bb.0:
383 ; CHECK-FP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
384 ; CHECK-FP-GI-NEXT: fminnm v1.4s, v2.4s, v3.4s
385 ; CHECK-FP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s
386 ; CHECK-FP-GI-NEXT: fminnmv s0, v0.4s
387 ; CHECK-FP-GI-NEXT: ret
388 %b = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)
389 ret float %b
390 }
392 define double @test_v2f64(<2 x double> %a) nounwind {
393 ; CHECK-LABEL: test_v2f64:
394 ; CHECK: // %bb.0:
395 ; CHECK-NEXT: fminnmp d0, v0.2d
396 ; CHECK-NEXT: ret
397 %b = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
398 ret double %b
399 }
401 define double @test_v4f64(<4 x double> %a) nounwind {
402 ; CHECK-LABEL: test_v4f64:
403 ; CHECK: // %bb.0:
404 ; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
405 ; CHECK-NEXT: fminnmp d0, v0.2d
406 ; CHECK-NEXT: ret
407 %b = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %a)
408 ret double %b
409 }
411 define half @test_v11f16(<11 x half> %a) nounwind {
412 ; CHECK-NOFP-LABEL: test_v11f16:
413 ; CHECK-NOFP: // %bb.0:
414 ; CHECK-NOFP-NEXT: ldr h16, [sp, #8]
415 ; CHECK-NOFP-NEXT: fcvt s1, h1
416 ; CHECK-NOFP-NEXT: ldr h17, [sp]
417 ; CHECK-NOFP-NEXT: fcvt s0, h0
418 ; CHECK-NOFP-NEXT: fcvt s2, h2
419 ; CHECK-NOFP-NEXT: adrp x8, .LCPI14_0
420 ; CHECK-NOFP-NEXT: fcvt s16, h16
421 ; CHECK-NOFP-NEXT: fcvt s17, h17
422 ; CHECK-NOFP-NEXT: fcvt s3, h3
423 ; CHECK-NOFP-NEXT: fcmp s1, s16
424 ; CHECK-NOFP-NEXT: fcsel s1, s1, s16, lt
425 ; CHECK-NOFP-NEXT: fcmp s0, s17
426 ; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
427 ; CHECK-NOFP-NEXT: fcvt s16, h16
428 ; CHECK-NOFP-NEXT: fcsel s0, s0, s17, lt
429 ; CHECK-NOFP-NEXT: fcvt h1, s1
430 ; CHECK-NOFP-NEXT: fcmp s2, s16
431 ; CHECK-NOFP-NEXT: fcvt h0, s0
432 ; CHECK-NOFP-NEXT: fcvt s1, h1
433 ; CHECK-NOFP-NEXT: fcvt s0, h0
434 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
435 ; CHECK-NOFP-NEXT: fcsel s1, s2, s16, lt
436 ; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI14_0]
437 ; CHECK-NOFP-NEXT: mov w8, #2139095040 // =0x7f800000
438 ; CHECK-NOFP-NEXT: fcvt s2, h2
439 ; CHECK-NOFP-NEXT: fmov s16, w8
440 ; CHECK-NOFP-NEXT: fcvt h0, s0
441 ; CHECK-NOFP-NEXT: fcvt h1, s1
442 ; CHECK-NOFP-NEXT: fcmp s3, s2
443 ; CHECK-NOFP-NEXT: fcvt s0, h0
444 ; CHECK-NOFP-NEXT: fcvt s1, h1
445 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
446 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
447 ; CHECK-NOFP-NEXT: fcvt s3, h4
448 ; CHECK-NOFP-NEXT: fcvt h0, s0
449 ; CHECK-NOFP-NEXT: fcvt h1, s1
450 ; CHECK-NOFP-NEXT: fcmp s3, s2
451 ; CHECK-NOFP-NEXT: fcvt s0, h0
452 ; CHECK-NOFP-NEXT: fcvt s1, h1
453 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
454 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
455 ; CHECK-NOFP-NEXT: fcvt s3, h5
456 ; CHECK-NOFP-NEXT: fcvt h0, s0
457 ; CHECK-NOFP-NEXT: fcvt h1, s1
458 ; CHECK-NOFP-NEXT: fcmp s3, s2
459 ; CHECK-NOFP-NEXT: fcvt s0, h0
460 ; CHECK-NOFP-NEXT: fcvt s1, h1
461 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
462 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
463 ; CHECK-NOFP-NEXT: fcvt s3, h6
464 ; CHECK-NOFP-NEXT: fcvt h0, s0
465 ; CHECK-NOFP-NEXT: fcvt h1, s1
466 ; CHECK-NOFP-NEXT: fcmp s3, s2
467 ; CHECK-NOFP-NEXT: fcvt s0, h0
468 ; CHECK-NOFP-NEXT: fcvt s1, h1
469 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
470 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
471 ; CHECK-NOFP-NEXT: fcvt s3, h7
472 ; CHECK-NOFP-NEXT: fcvt h0, s0
473 ; CHECK-NOFP-NEXT: fcvt h1, s1
474 ; CHECK-NOFP-NEXT: fcmp s3, s2
475 ; CHECK-NOFP-NEXT: fcvt s0, h0
476 ; CHECK-NOFP-NEXT: fcvt s1, h1
477 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
478 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
479 ; CHECK-NOFP-NEXT: fcvt h0, s0
480 ; CHECK-NOFP-NEXT: fcvt h1, s1
481 ; CHECK-NOFP-NEXT: fcvt s0, h0
482 ; CHECK-NOFP-NEXT: fcvt s1, h1
483 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
484 ; CHECK-NOFP-NEXT: fcvt h0, s0
485 ; CHECK-NOFP-NEXT: ret
486 ;
487 ; CHECK-FP-LABEL: test_v11f16:
488 ; CHECK-FP: // %bb.0:
489 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
490 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
491 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
492 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
493 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
494 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
495 ; CHECK-FP-NEXT: mov x8, sp
496 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
497 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
498 ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
499 ; CHECK-FP-NEXT: movi v1.8h, #124, lsl #8
500 ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
501 ; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
502 ; CHECK-FP-NEXT: add x8, sp, #8
503 ; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
504 ; CHECK-FP-NEXT: add x8, sp, #16
505 ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
506 ; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
507 ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
508 ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
509 ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
510 ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
511 ; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
512 ; CHECK-FP-NEXT: fminnmv h0, v0.8h
513 ; CHECK-FP-NEXT: ret
514 %b = call nnan half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
515 ret half %b
516 }
518 define half @test_v11f16_ninf(<11 x half> %a) nounwind {
519 ; CHECK-NOFP-LABEL: test_v11f16_ninf:
520 ; CHECK-NOFP: // %bb.0:
521 ; CHECK-NOFP-NEXT: ldr h16, [sp, #8]
522 ; CHECK-NOFP-NEXT: fcvt s1, h1
523 ; CHECK-NOFP-NEXT: ldr h17, [sp]
524 ; CHECK-NOFP-NEXT: fcvt s0, h0
525 ; CHECK-NOFP-NEXT: fcvt s2, h2
526 ; CHECK-NOFP-NEXT: adrp x8, .LCPI15_0
527 ; CHECK-NOFP-NEXT: fcvt s16, h16
528 ; CHECK-NOFP-NEXT: fcvt s17, h17
529 ; CHECK-NOFP-NEXT: fcvt s3, h3
530 ; CHECK-NOFP-NEXT: fcmp s1, s16
531 ; CHECK-NOFP-NEXT: fcsel s1, s1, s16, lt
532 ; CHECK-NOFP-NEXT: fcmp s0, s17
533 ; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
534 ; CHECK-NOFP-NEXT: fcvt s16, h16
535 ; CHECK-NOFP-NEXT: fcsel s0, s0, s17, lt
536 ; CHECK-NOFP-NEXT: fcvt h1, s1
537 ; CHECK-NOFP-NEXT: fcmp s2, s16
538 ; CHECK-NOFP-NEXT: fcvt h0, s0
539 ; CHECK-NOFP-NEXT: fcvt s1, h1
540 ; CHECK-NOFP-NEXT: fcvt s0, h0
541 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
542 ; CHECK-NOFP-NEXT: fcsel s1, s2, s16, lt
543 ; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI15_0]
544 ; CHECK-NOFP-NEXT: mov w8, #57344 // =0xe000
545 ; CHECK-NOFP-NEXT: fcvt s2, h2
546 ; CHECK-NOFP-NEXT: movk w8, #18303, lsl #16
547 ; CHECK-NOFP-NEXT: fmov s16, w8
548 ; CHECK-NOFP-NEXT: fcvt h0, s0
549 ; CHECK-NOFP-NEXT: fcvt h1, s1
550 ; CHECK-NOFP-NEXT: fcmp s3, s2
551 ; CHECK-NOFP-NEXT: fcvt s0, h0
552 ; CHECK-NOFP-NEXT: fcvt s1, h1
553 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
554 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
555 ; CHECK-NOFP-NEXT: fcvt s3, h4
556 ; CHECK-NOFP-NEXT: fcvt h0, s0
557 ; CHECK-NOFP-NEXT: fcvt h1, s1
558 ; CHECK-NOFP-NEXT: fcmp s3, s2
559 ; CHECK-NOFP-NEXT: fcvt s0, h0
560 ; CHECK-NOFP-NEXT: fcvt s1, h1
561 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
562 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
563 ; CHECK-NOFP-NEXT: fcvt s3, h5
564 ; CHECK-NOFP-NEXT: fcvt h0, s0
565 ; CHECK-NOFP-NEXT: fcvt h1, s1
566 ; CHECK-NOFP-NEXT: fcmp s3, s2
567 ; CHECK-NOFP-NEXT: fcvt s0, h0
568 ; CHECK-NOFP-NEXT: fcvt s1, h1
569 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
570 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
571 ; CHECK-NOFP-NEXT: fcvt s3, h6
572 ; CHECK-NOFP-NEXT: fcvt h0, s0
573 ; CHECK-NOFP-NEXT: fcvt h1, s1
574 ; CHECK-NOFP-NEXT: fcmp s3, s2
575 ; CHECK-NOFP-NEXT: fcvt s0, h0
576 ; CHECK-NOFP-NEXT: fcvt s1, h1
577 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
578 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
579 ; CHECK-NOFP-NEXT: fcvt s3, h7
580 ; CHECK-NOFP-NEXT: fcvt h0, s0
581 ; CHECK-NOFP-NEXT: fcvt h1, s1
582 ; CHECK-NOFP-NEXT: fcmp s3, s2
583 ; CHECK-NOFP-NEXT: fcvt s0, h0
584 ; CHECK-NOFP-NEXT: fcvt s1, h1
585 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
586 ; CHECK-NOFP-NEXT: fcsel s1, s3, s16, lt
587 ; CHECK-NOFP-NEXT: fcvt h0, s0
588 ; CHECK-NOFP-NEXT: fcvt h1, s1
589 ; CHECK-NOFP-NEXT: fcvt s0, h0
590 ; CHECK-NOFP-NEXT: fcvt s1, h1
591 ; CHECK-NOFP-NEXT: fminnm s0, s0, s1
592 ; CHECK-NOFP-NEXT: fcvt h0, s0
593 ; CHECK-NOFP-NEXT: ret
594 ;
595 ; CHECK-FP-LABEL: test_v11f16_ninf:
596 ; CHECK-FP: // %bb.0:
597 ; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0
598 ; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1
599 ; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2
600 ; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3
601 ; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4
602 ; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5
603 ; CHECK-FP-NEXT: mov x8, sp
604 ; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6
605 ; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7
606 ; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]
607 ; CHECK-FP-NEXT: mvni v1.8h, #132, lsl #8
608 ; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]
609 ; CHECK-FP-NEXT: add x8, sp, #8
610 ; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]
611 ; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]
612 ; CHECK-FP-NEXT: add x8, sp, #16
613 ; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]
614 ; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]
615 ; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]
616 ; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]
617 ; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]
618 ; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]
619 ; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h
620 ; CHECK-FP-NEXT: fminnmv h0, v0.8h
621 ; CHECK-FP-NEXT: ret
622 %b = call nnan ninf half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)
623 ret half %b
624 }
626 define float @test_v3f32(<3 x float> %a) nounwind {
627 ; CHECK-LABEL: test_v3f32:
628 ; CHECK: // %bb.0:
629 ; CHECK-NEXT: mov w8, #2139095040 // =0x7f800000
630 ; CHECK-NEXT: fmov s1, w8
631 ; CHECK-NEXT: mov v0.s[3], v1.s[0]
632 ; CHECK-NEXT: fminnmv s0, v0.4s
633 ; CHECK-NEXT: ret
634 %b = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
635 ret float %b
636 }
638 define float @test_v3f32_ninf(<3 x float> %a) nounwind {
639 ; CHECK-LABEL: test_v3f32_ninf:
640 ; CHECK: // %bb.0:
641 ; CHECK-NEXT: mov w8, #2139095039 // =0x7f7fffff
642 ; CHECK-NEXT: fmov s1, w8
643 ; CHECK-NEXT: mov v0.s[3], v1.s[0]
644 ; CHECK-NEXT: fminnmv s0, v0.4s
645 ; CHECK-NEXT: ret
646 %b = call nnan ninf float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
647 ret float %b
648 }
650 define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
651 ; CHECK-LABEL: test_v2f128:
652 ; CHECK: // %bb.0:
653 ; CHECK-NEXT: b fminl
654 %b = call nnan fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
655 ret fp128 %b
656 }