1 ; RUN: llc -march=hexagon < %s | FileCheck %s
3 ; Check that the resulting register pair has the registers in the right order.
7 ; CHECK: v[[V1:[0-9]+]]:[[V0:[0-9]+]] = vshuff
10 ; CHECK-NEXT: vmem(r[[RA:[0-9]+]]+#0) = v[[V0]]
13 ; CHECK-NEXT: r0 = memw(r1+#0)
16 ; CHECK-NEXT: r1 = memw(r1+#4)
19 ; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
22 define i64 @foo(<64 x i16> %a0, <64 x i16> %a1) #0 {
23 %v0 = icmp ugt <64 x i16> %a0, %a1
24 %v1 = bitcast <64 x i1> %v0 to i64
28 attributes #0 = { nounwind readnone "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b,-packets" }