| blob | 9ad00cd83ad8169da94f100cfcf2497d9b879af7 |
1 ; RUN: llc -march=hexagon < %s
2 ; REQUIRES: asserts
4 ; Test that the register scavenger does not assert because a spill slot
5 ; was not found. The bug is that the Hexagon spill code was not allocating
6 ; the spill slot because the function that returns true, which indicates
7 ; the code changed when a spill is inserted, was not always returning true.
9 ; Function Attrs: nounwind
10 define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr noalias nocapture %a4, i32 %a5) #0 {
11 b0:
12 %v0 = sub i32 0, %a1
13 %v1 = getelementptr inbounds i8, ptr %a0, i32 %v0
14 %v2 = getelementptr inbounds i8, ptr %a0, i32 %a1
15 %v3 = mul nsw i32 %a1, 2
16 %v4 = getelementptr inbounds i8, ptr %a0, i32 %v3
17 %v6 = getelementptr inbounds i8, ptr %a4, i32 %a5
18 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
19 %v9 = load <16 x i32>, ptr undef, align 64
20 %v10 = or i64 undef, 0
21 %v11 = trunc i64 %v10 to i32
22 %v12 = load i8, ptr undef, align 1
23 %v13 = zext i8 %v12 to i64
24 %v14 = shl nuw nsw i64 %v13, 8
25 %v15 = or i64 0, %v14
26 %v16 = trunc i64 %v15 to i32
27 %v17 = load i8, ptr undef, align 1
28 %v18 = zext i8 %v17 to i64
29 %v19 = or i64 0, %v18
30 %v20 = or i64 %v19, 0
31 %v21 = or i64 %v20, 0
32 %v22 = trunc i64 %v21 to i32
33 %v23 = load i8, ptr undef, align 1
34 %v24 = zext i8 %v23 to i64
35 %v25 = shl nuw nsw i64 %v24, 8
36 %v26 = or i64 undef, %v25
37 %v27 = trunc i64 %v26 to i32
38 %v28 = icmp sgt i32 %a2, 64
39 br i1 %v28, label %b1, label %b6
41 b1: ; preds = %b0
42 %v29 = getelementptr inbounds i8, ptr %v4, i32 64
43 %v31 = getelementptr inbounds i8, ptr %v2, i32 64
44 %v33 = getelementptr inbounds i8, ptr %a0, i32 64
45 %v35 = getelementptr inbounds i8, ptr %v1, i32 64
46 %v37 = add i32 0, 64
47 %v38 = getelementptr i8, ptr %a4, i32 %v37
48 %v39 = add i32 %a2, -65
49 %v40 = lshr i32 %v39, 6
50 %v41 = add nuw nsw i32 %v40, 1
51 %v42 = and i32 %v41, 3
52 %v43 = icmp eq i32 %v42, 0
53 br i1 undef, label %b2, label %b4
55 b2: ; preds = %b2, %b1
56 %v44 = phi i32 [ %v144, %b2 ], [ %a2, %b1 ]
57 %v45 = phi <16 x i32> [ %v101, %b2 ], [ %v8, %b1 ]
58 %v46 = phi <16 x i32> [ %v113, %b2 ], [ undef, %b1 ]
59 %v47 = phi <16 x i32> [ %v102, %b2 ], [ %v8, %b1 ]
60 %v48 = phi <16 x i32> [ %v118, %b2 ], [ undef, %b1 ]
61 %v49 = phi ptr [ %v112, %b2 ], [ %v35, %b1 ]
62 %v50 = phi ptr [ %v114, %b2 ], [ %v33, %b1 ]
63 %v51 = phi ptr [ %v116, %b2 ], [ %v31, %b1 ]
64 %v52 = phi ptr [ undef, %b2 ], [ %v29, %b1 ]
65 %v53 = phi ptr [ %v139, %b2 ], [ %a4, %b1 ]
66 %v54 = phi ptr [ %v143, %b2 ], [ %v6, %b1 ]
67 %v55 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v46, <16 x i32> %v45, i32 1)
68 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v47, i32 1)
69 %v57 = getelementptr inbounds <16 x i32>, ptr %v49, i32 1
70 %v58 = load <16 x i32>, ptr %v49, align 64
71 %v59 = getelementptr inbounds <16 x i32>, ptr %v50, i32 1
72 %v60 = load <16 x i32>, ptr %v50, align 64
73 %v61 = load <16 x i32>, ptr %v51, align 64
74 %v62 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v58, <16 x i32> %v46, i32 1)
75 %v63 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v60, <16 x i32> undef, i32 1)
76 %v64 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v61, <16 x i32> undef, i32 1)
77 %v65 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> %v48, i32 1)
78 %v66 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v55)
79 %v67 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v63, <16 x i32> %v56)
80 %v68 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v66, i32 %v11)
81 %v69 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> undef)
82 %v70 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v68, <32 x i32> %v67, i32 %v16)
83 %v71 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v63)
84 %v72 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v70, <32 x i32> %v71, i32 %v22)
85 %v73 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v72, <32 x i32> %v69, i32 0)
86 %v74 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v73, <16 x i32> %v64, i32 %v27)
87 %v75 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> zeroinitializer, <16 x i32> %v65, i32 %v27)
88 %v76 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v74)
89 %v77 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v76, <16 x i32> undef, i32 %a3)
90 %v78 = getelementptr inbounds <16 x i32>, ptr %v53, i32 1
91 store <16 x i32> %v77, ptr %v53, align 64
92 %v79 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v75)
93 %v80 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v79, <16 x i32> undef, i32 %a3)
94 %v81 = getelementptr inbounds <16 x i32>, ptr %v54, i32 1
95 store <16 x i32> %v80, ptr %v54, align 64
96 %v82 = getelementptr inbounds <16 x i32>, ptr %v49, i32 2
97 %v83 = load <16 x i32>, ptr %v57, align 64
98 %v84 = getelementptr inbounds <16 x i32>, ptr %v50, i32 2
99 %v85 = load <16 x i32>, ptr %v59, align 64
100 %v86 = load <16 x i32>, ptr undef, align 64
101 %v87 = load <16 x i32>, ptr null, align 64
102 %v88 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v83, <16 x i32> %v58, i32 1)
103 %v89 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v85, <16 x i32> %v60, i32 1)
104 %v90 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v86, <16 x i32> %v61, i32 1)
105 %v91 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v90, <16 x i32> undef)
106 %v92 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> undef, <32 x i32> undef, i32 %v16)
107 %v93 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v88, <16 x i32> %v89)
108 %v94 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v92, <32 x i32> %v93, i32 %v22)
109 %v95 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v94, <32 x i32> %v91, i32 0)
110 %v96 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v95, <16 x i32> %v90, i32 %v27)
111 %v97 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v96)
112 %v98 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v97, <16 x i32> undef, i32 %a3)
113 store <16 x i32> %v98, ptr %v78, align 64
114 %v99 = getelementptr inbounds <16 x i32>, ptr %v54, i32 2
115 store <16 x i32> undef, ptr %v81, align 64
116 %v100 = getelementptr inbounds <16 x i32>, ptr %v49, i32 3
117 %v101 = load <16 x i32>, ptr %v82, align 64
118 %v102 = load <16 x i32>, ptr %v84, align 64
119 %v103 = getelementptr inbounds <16 x i32>, ptr %v51, i32 3
120 %v104 = load <16 x i32>, ptr null, align 64
121 %v105 = getelementptr inbounds <16 x i32>, ptr %v52, i32 3
122 %v106 = load <16 x i32>, ptr undef, align 64
123 %v107 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> undef, i32 %a3)
124 store <16 x i32> %v107, ptr undef, align 64
125 %v108 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> undef, i32 %a3)
126 %v109 = getelementptr inbounds <16 x i32>, ptr %v54, i32 3
127 store <16 x i32> %v108, ptr %v99, align 64
128 %v110 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v104, <16 x i32> %v86, i32 1)
129 %v111 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v106, <16 x i32> %v87, i32 1)
130 %v112 = getelementptr inbounds <16 x i32>, ptr %v49, i32 4
131 %v113 = load <16 x i32>, ptr %v100, align 64
132 %v114 = getelementptr inbounds <16 x i32>, ptr %v50, i32 4
133 %v115 = load <16 x i32>, ptr undef, align 64
134 %v116 = getelementptr inbounds <16 x i32>, ptr %v51, i32 4
135 %v117 = load <16 x i32>, ptr %v103, align 64
136 %v118 = load <16 x i32>, ptr %v105, align 64
137 %v119 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v113, <16 x i32> %v101, i32 1)
138 %v120 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v115, <16 x i32> %v102, i32 1)
139 %v121 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v117, <16 x i32> %v104, i32 1)
140 %v122 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v118, <16 x i32> %v106, i32 1)
141 %v123 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v119, <16 x i32> undef)
142 %v124 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v120, <16 x i32> undef)
143 %v125 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v123, i32 %v11)
144 %v126 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32> %v124, i32 %v11)
145 %v127 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v121, <16 x i32> %v110)
146 %v128 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v125, <32 x i32> %v124, i32 %v16)
147 %v129 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v126, <32 x i32> %v127, i32 %v16)
148 %v130 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v128, <32 x i32> undef, i32 %v22)
149 %v131 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v129, <32 x i32> undef, i32 %v22)
150 %v132 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v122, <16 x i32> %v111)
151 %v133 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v130, <32 x i32> %v127, i32 0)
152 %v134 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v131, <32 x i32> %v132, i32 0)
153 %v135 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v133, <16 x i32> %v121, i32 %v27)
154 %v136 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v134, <16 x i32> %v122, i32 %v27)
155 %v137 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v135)
156 %v138 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v137, <16 x i32> undef, i32 %a3)
157 %v139 = getelementptr inbounds <16 x i32>, ptr %v53, i32 4
158 store <16 x i32> %v138, ptr undef, align 64
159 %v140 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v136)
160 %v141 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v136)
161 %v142 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v140, <16 x i32> %v141, i32 %a3)
162 %v143 = getelementptr inbounds <16 x i32>, ptr %v54, i32 4
163 store <16 x i32> %v142, ptr %v109, align 64
164 %v144 = add nsw i32 %v44, -256
165 %v145 = icmp sgt i32 %v144, 256
166 br i1 %v145, label %b2, label %b3
168 b3: ; preds = %b2
169 %v146 = phi ptr [ %v116, %b2 ]
170 %v147 = phi ptr [ %v114, %b2 ]
171 %v148 = phi ptr [ %v112, %b2 ]
172 br i1 %v43, label %b5, label %b4
174 b4: ; preds = %b3, %b1
175 %v149 = phi <16 x i32> [ %v9, %b1 ], [ undef, %b3 ]
176 %v150 = phi ptr [ %v35, %b1 ], [ %v148, %b3 ]
177 %v151 = phi ptr [ %v33, %b1 ], [ %v147, %b3 ]
178 %v152 = phi ptr [ %v31, %b1 ], [ %v146, %b3 ]
179 %v153 = phi ptr [ %a4, %b1 ], [ undef, %b3 ]
180 %v154 = load <16 x i32>, ptr %v150, align 64
181 %v155 = load <16 x i32>, ptr %v151, align 64
182 %v156 = load <16 x i32>, ptr %v152, align 64
183 %v157 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v154, <16 x i32> undef, i32 1)
184 %v158 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v155, <16 x i32> undef, i32 1)
185 %v159 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v156, <16 x i32> %v149, i32 1)
186 %v160 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v157, <16 x i32> %v158)
187 %v161 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v160, i32 %v22)
188 %v162 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v161, <32 x i32> undef, i32 0)
189 %v163 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v162, <16 x i32> %v159, i32 %v27)
190 %v164 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v163)
191 %v165 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> %v164, <16 x i32> undef, i32 %a3)
192 store <16 x i32> %v165, ptr %v153, align 64
193 unreachable
195 b5: ; preds = %b3
196 br label %b6
198 b6: ; preds = %b5, %b0
199 %v167 = phi <16 x i32> [ %v8, %b0 ], [ undef, %b5 ]
200 %v168 = phi ptr [ %a4, %b0 ], [ %v38, %b5 ]
201 %v169 = phi ptr [ %v6, %b0 ], [ undef, %b5 ]
202 %v170 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v167, i32 1)
203 %v171 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> undef, i32 1)
204 %v172 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v170)
205 %v173 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v171)
206 %v174 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v171, <16 x i32> undef)
207 %v175 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v173, i32 %v22)
208 %v176 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v174, i32 %v22)
209 %v177 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v175, <32 x i32> %v172, i32 0)
210 %v178 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v176, <32 x i32> undef, i32 0)
211 %v179 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v177, <16 x i32> undef, i32 %v27)
212 %v180 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v178, <16 x i32> undef, i32 %v27)
213 %v181 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v179)
214 %v182 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v181, i32 %a3)
215 store <16 x i32> %v182, ptr %v168, align 64
216 %v183 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v180)
217 %v184 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v183, i32 %a3)
218 store <16 x i32> %v184, ptr %v169, align 64
219 ret void
220 }
222 ; Function Attrs: nounwind readnone
223 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
225 ; Function Attrs: nounwind readnone
226 declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1
228 ; Function Attrs: nounwind readnone
229 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
231 ; Function Attrs: nounwind readnone
232 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
234 ; Function Attrs: nounwind readnone
235 declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv(<32 x i32>, i32) #1
237 ; Function Attrs: nounwind readnone
238 declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #1
240 ; Function Attrs: nounwind readnone
241 declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1
243 ; Function Attrs: nounwind readnone
244 declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #1
246 ; Function Attrs: nounwind readnone
247 declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #1
249 ; Function Attrs: nounwind readnone
250 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
252 ; Function Attrs: nounwind readnone
253 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
255 attributes #0 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" }
256 attributes #1 = { nounwind readnone }