1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
4 define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, i32 %a2, ptr nocapture %a3, i32 %a4, i32 %a5) #0 {
6 %v1 = load i64, ptr %a1, align 8
8 %v3 = trunc i64 %v2 to i32
9 %v4 = trunc i64 %v1 to i32
10 %v5 = and i32 %v4, 16777215
11 %v7 = load <16 x i32>, ptr %a0, align 64
12 %v8 = getelementptr inbounds i8, ptr %a0, i32 32
13 %v10 = load <16 x i32>, ptr %v8, align 64
14 %v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> %v7)
15 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v5, i32 0)
16 %v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v3, i32 0)
17 %v14 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v12)
18 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v14, <16 x i32> %v14, i32 %a2)
19 %v16 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)
20 %v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v16, <16 x i32> %v16, i32 %a2)
21 %v18 = getelementptr inbounds i8, ptr %a3, i32 32
22 store <16 x i32> %v15, ptr %v18, align 64
23 store <16 x i32> %v17, ptr %a3, align 64
27 ; Function Attrs: nounwind readnone
28 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
30 ; Function Attrs: nounwind readnone
31 declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1
33 ; Function Attrs: nounwind readnone
34 declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #1
36 ; Function Attrs: nounwind readnone
37 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
39 ; Function Attrs: nounwind readnone
40 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
42 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
43 attributes #1 = { nounwind readnone }