1 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW
2 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW
3 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW
4 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH
5 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH
6 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
8 ; Make sure that the instructions with immediate operands are generated.
9 ; CHECK-ASLW: vaslw({{.*}},#9)
10 ; CHECK-ASRW: vasrw({{.*}},#8)
11 ; CHECK-LSRW: vlsrw({{.*}},#7)
12 ; CHECK-ASLH: vaslh({{.*}},#6)
13 ; CHECK-ASRH: vasrh({{.*}},#5)
14 ; CHECK-LSRH: vlsrh({{.*}},#4)
16 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
17 target triple = "hexagon"
19 define i64 @foo(i64 %x) nounwind readnone {
21 %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
22 %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8)
23 %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7)
24 %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
25 %4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5)
26 %5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4)
28 %add1 = add i64 %add, %2
29 %add2 = add i64 %add1, %3
30 %add3 = add i64 %add2, %4
31 %add4 = add i64 %add3, %5
35 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
36 declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone
37 declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone
38 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
39 declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone
40 declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone