| blob | 46ce3bfd450bd0d7e34cd2836b49bde1a8122efa |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
3 ; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \
4 ; RUN: --check-prefix=SMALL32
5 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
6 ; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \
7 ; RUN: | FileCheck %s --check-prefix=LARGE32
8 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
9 ; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \
10 ; RUN: --check-prefix=SMALL64
11 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \
12 ; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \
13 ; RUN: | FileCheck %s --check-prefix=LARGE64
15 @TGInit = thread_local global double 1.000000e+00, align 8
16 @TWInit = weak thread_local global double 1.000000e+00, align 8
17 @GInit = global double 1.000000e+00, align 8
18 @TGUninit = thread_local global double 0.000000e+00, align 8
19 @TIInit = internal thread_local global double 1.000000e+00, align 8
21 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
22 define void @storesTGUninit(double %Val) #0 {
23 ; SMALL32-LABEL: storesTGUninit:
24 ; SMALL32: # %bb.0: # %entry
25 ; SMALL32-NEXT: mflr 0
26 ; SMALL32-NEXT: stwu 1, -32(1)
27 ; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
28 ; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
29 ; SMALL32-NEXT: stw 0, 40(1)
30 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
31 ; SMALL32-NEXT: stfd 1, 0(3)
32 ; SMALL32-NEXT: addi 1, 1, 32
33 ; SMALL32-NEXT: lwz 0, 8(1)
34 ; SMALL32-NEXT: mtlr 0
35 ; SMALL32-NEXT: blr
36 ;
37 ; LARGE32-LABEL: storesTGUninit:
38 ; LARGE32: # %bb.0: # %entry
39 ; LARGE32-NEXT: mflr 0
40 ; LARGE32-NEXT: stwu 1, -32(1)
41 ; LARGE32-NEXT: stw 0, 40(1)
42 ; LARGE32-NEXT: addis 3, L..C0@u(2)
43 ; LARGE32-NEXT: addis 4, L..C1@u(2)
44 ; LARGE32-NEXT: lwz 3, L..C0@l(3)
45 ; LARGE32-NEXT: lwz 4, L..C1@l(4)
46 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
47 ; LARGE32-NEXT: stfd 1, 0(3)
48 ; LARGE32-NEXT: addi 1, 1, 32
49 ; LARGE32-NEXT: lwz 0, 8(1)
50 ; LARGE32-NEXT: mtlr 0
51 ; LARGE32-NEXT: blr
52 ;
53 ; SMALL64-LABEL: storesTGUninit:
54 ; SMALL64: # %bb.0: # %entry
55 ; SMALL64-NEXT: mflr 0
56 ; SMALL64-NEXT: stdu 1, -48(1)
57 ; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
58 ; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
59 ; SMALL64-NEXT: std 0, 64(1)
60 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
61 ; SMALL64-NEXT: stfd 1, 0(3)
62 ; SMALL64-NEXT: addi 1, 1, 48
63 ; SMALL64-NEXT: ld 0, 16(1)
64 ; SMALL64-NEXT: mtlr 0
65 ; SMALL64-NEXT: blr
66 ;
67 ; LARGE64-LABEL: storesTGUninit:
68 ; LARGE64: # %bb.0: # %entry
69 ; LARGE64-NEXT: mflr 0
70 ; LARGE64-NEXT: stdu 1, -48(1)
71 ; LARGE64-NEXT: addis 3, L..C0@u(2)
72 ; LARGE64-NEXT: addis 4, L..C1@u(2)
73 ; LARGE64-NEXT: std 0, 64(1)
74 ; LARGE64-NEXT: ld 3, L..C0@l(3)
75 ; LARGE64-NEXT: ld 4, L..C1@l(4)
76 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
77 ; LARGE64-NEXT: stfd 1, 0(3)
78 ; LARGE64-NEXT: addi 1, 1, 48
79 ; LARGE64-NEXT: ld 0, 16(1)
80 ; LARGE64-NEXT: mtlr 0
81 ; LARGE64-NEXT: blr
82 entry:
83 store double %Val, ptr @TGUninit, align 8
84 ret void
85 }
87 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
88 define void @storesTGInit(double %Val) #0 {
89 ; SMALL32-LABEL: storesTGInit:
90 ; SMALL32: # %bb.0: # %entry
91 ; SMALL32-NEXT: mflr 0
92 ; SMALL32-NEXT: stwu 1, -32(1)
93 ; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-lo) @TGInit
94 ; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
95 ; SMALL32-NEXT: stw 0, 40(1)
96 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
97 ; SMALL32-NEXT: stfd 1, 0(3)
98 ; SMALL32-NEXT: addi 1, 1, 32
99 ; SMALL32-NEXT: lwz 0, 8(1)
100 ; SMALL32-NEXT: mtlr 0
101 ; SMALL32-NEXT: blr
102 ;
103 ; LARGE32-LABEL: storesTGInit:
104 ; LARGE32: # %bb.0: # %entry
105 ; LARGE32-NEXT: mflr 0
106 ; LARGE32-NEXT: stwu 1, -32(1)
107 ; LARGE32-NEXT: stw 0, 40(1)
108 ; LARGE32-NEXT: addis 3, L..C2@u(2)
109 ; LARGE32-NEXT: addis 4, L..C3@u(2)
110 ; LARGE32-NEXT: lwz 3, L..C2@l(3)
111 ; LARGE32-NEXT: lwz 4, L..C3@l(4)
112 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
113 ; LARGE32-NEXT: stfd 1, 0(3)
114 ; LARGE32-NEXT: addi 1, 1, 32
115 ; LARGE32-NEXT: lwz 0, 8(1)
116 ; LARGE32-NEXT: mtlr 0
117 ; LARGE32-NEXT: blr
118 ;
119 ; SMALL64-LABEL: storesTGInit:
120 ; SMALL64: # %bb.0: # %entry
121 ; SMALL64-NEXT: mflr 0
122 ; SMALL64-NEXT: stdu 1, -48(1)
123 ; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-lo) @TGInit
124 ; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
125 ; SMALL64-NEXT: std 0, 64(1)
126 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
127 ; SMALL64-NEXT: stfd 1, 0(3)
128 ; SMALL64-NEXT: addi 1, 1, 48
129 ; SMALL64-NEXT: ld 0, 16(1)
130 ; SMALL64-NEXT: mtlr 0
131 ; SMALL64-NEXT: blr
132 ;
133 ; LARGE64-LABEL: storesTGInit:
134 ; LARGE64: # %bb.0: # %entry
135 ; LARGE64-NEXT: mflr 0
136 ; LARGE64-NEXT: stdu 1, -48(1)
137 ; LARGE64-NEXT: addis 3, L..C2@u(2)
138 ; LARGE64-NEXT: addis 4, L..C3@u(2)
139 ; LARGE64-NEXT: std 0, 64(1)
140 ; LARGE64-NEXT: ld 3, L..C2@l(3)
141 ; LARGE64-NEXT: ld 4, L..C3@l(4)
142 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
143 ; LARGE64-NEXT: stfd 1, 0(3)
144 ; LARGE64-NEXT: addi 1, 1, 48
145 ; LARGE64-NEXT: ld 0, 16(1)
146 ; LARGE64-NEXT: mtlr 0
147 ; LARGE64-NEXT: blr
148 entry:
149 store double %Val, ptr @TGInit, align 8
150 ret void
151 }
153 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
154 define void @storesTIInit(double %Val) #0 {
155 ; SMALL32-LABEL: storesTIInit:
156 ; SMALL32: # %bb.0: # %entry
157 ; SMALL32-NEXT: mflr 0
158 ; SMALL32-NEXT: stwu 1, -32(1)
159 ; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-lo) @TIInit
160 ; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
161 ; SMALL32-NEXT: stw 0, 40(1)
162 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
163 ; SMALL32-NEXT: stfd 1, 0(3)
164 ; SMALL32-NEXT: addi 1, 1, 32
165 ; SMALL32-NEXT: lwz 0, 8(1)
166 ; SMALL32-NEXT: mtlr 0
167 ; SMALL32-NEXT: blr
168 ;
169 ; LARGE32-LABEL: storesTIInit:
170 ; LARGE32: # %bb.0: # %entry
171 ; LARGE32-NEXT: mflr 0
172 ; LARGE32-NEXT: stwu 1, -32(1)
173 ; LARGE32-NEXT: stw 0, 40(1)
174 ; LARGE32-NEXT: addis 3, L..C4@u(2)
175 ; LARGE32-NEXT: addis 4, L..C5@u(2)
176 ; LARGE32-NEXT: lwz 3, L..C4@l(3)
177 ; LARGE32-NEXT: lwz 4, L..C5@l(4)
178 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
179 ; LARGE32-NEXT: stfd 1, 0(3)
180 ; LARGE32-NEXT: addi 1, 1, 32
181 ; LARGE32-NEXT: lwz 0, 8(1)
182 ; LARGE32-NEXT: mtlr 0
183 ; LARGE32-NEXT: blr
184 ;
185 ; SMALL64-LABEL: storesTIInit:
186 ; SMALL64: # %bb.0: # %entry
187 ; SMALL64-NEXT: mflr 0
188 ; SMALL64-NEXT: stdu 1, -48(1)
189 ; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-lo) @TIInit
190 ; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
191 ; SMALL64-NEXT: std 0, 64(1)
192 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
193 ; SMALL64-NEXT: stfd 1, 0(3)
194 ; SMALL64-NEXT: addi 1, 1, 48
195 ; SMALL64-NEXT: ld 0, 16(1)
196 ; SMALL64-NEXT: mtlr 0
197 ; SMALL64-NEXT: blr
198 ;
199 ; LARGE64-LABEL: storesTIInit:
200 ; LARGE64: # %bb.0: # %entry
201 ; LARGE64-NEXT: mflr 0
202 ; LARGE64-NEXT: stdu 1, -48(1)
203 ; LARGE64-NEXT: addis 3, L..C4@u(2)
204 ; LARGE64-NEXT: addis 4, L..C5@u(2)
205 ; LARGE64-NEXT: std 0, 64(1)
206 ; LARGE64-NEXT: ld 3, L..C4@l(3)
207 ; LARGE64-NEXT: ld 4, L..C5@l(4)
208 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
209 ; LARGE64-NEXT: stfd 1, 0(3)
210 ; LARGE64-NEXT: addi 1, 1, 48
211 ; LARGE64-NEXT: ld 0, 16(1)
212 ; LARGE64-NEXT: mtlr 0
213 ; LARGE64-NEXT: blr
214 entry:
215 store double %Val, ptr @TIInit, align 8
216 ret void
217 }
219 ; Function Attrs: nofree norecurse nounwind willreturn writeonly
220 define void @storesTWInit(double %Val) #0 {
221 ; SMALL32-LABEL: storesTWInit:
222 ; SMALL32: # %bb.0: # %entry
223 ; SMALL32-NEXT: mflr 0
224 ; SMALL32-NEXT: stwu 1, -32(1)
225 ; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-lo) @TWInit
226 ; SMALL32-NEXT: lwz 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
227 ; SMALL32-NEXT: stw 0, 40(1)
228 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
229 ; SMALL32-NEXT: stfd 1, 0(3)
230 ; SMALL32-NEXT: addi 1, 1, 32
231 ; SMALL32-NEXT: lwz 0, 8(1)
232 ; SMALL32-NEXT: mtlr 0
233 ; SMALL32-NEXT: blr
234 ;
235 ; LARGE32-LABEL: storesTWInit:
236 ; LARGE32: # %bb.0: # %entry
237 ; LARGE32-NEXT: mflr 0
238 ; LARGE32-NEXT: stwu 1, -32(1)
239 ; LARGE32-NEXT: stw 0, 40(1)
240 ; LARGE32-NEXT: addis 3, L..C6@u(2)
241 ; LARGE32-NEXT: addis 4, L..C7@u(2)
242 ; LARGE32-NEXT: lwz 3, L..C6@l(3)
243 ; LARGE32-NEXT: lwz 4, L..C7@l(4)
244 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
245 ; LARGE32-NEXT: stfd 1, 0(3)
246 ; LARGE32-NEXT: addi 1, 1, 32
247 ; LARGE32-NEXT: lwz 0, 8(1)
248 ; LARGE32-NEXT: mtlr 0
249 ; LARGE32-NEXT: blr
250 ;
251 ; SMALL64-LABEL: storesTWInit:
252 ; SMALL64: # %bb.0: # %entry
253 ; SMALL64-NEXT: mflr 0
254 ; SMALL64-NEXT: stdu 1, -48(1)
255 ; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-lo) @TWInit
256 ; SMALL64-NEXT: ld 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
257 ; SMALL64-NEXT: std 0, 64(1)
258 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
259 ; SMALL64-NEXT: stfd 1, 0(3)
260 ; SMALL64-NEXT: addi 1, 1, 48
261 ; SMALL64-NEXT: ld 0, 16(1)
262 ; SMALL64-NEXT: mtlr 0
263 ; SMALL64-NEXT: blr
264 ;
265 ; LARGE64-LABEL: storesTWInit:
266 ; LARGE64: # %bb.0: # %entry
267 ; LARGE64-NEXT: mflr 0
268 ; LARGE64-NEXT: stdu 1, -48(1)
269 ; LARGE64-NEXT: addis 3, L..C6@u(2)
270 ; LARGE64-NEXT: addis 4, L..C7@u(2)
271 ; LARGE64-NEXT: std 0, 64(1)
272 ; LARGE64-NEXT: ld 3, L..C6@l(3)
273 ; LARGE64-NEXT: ld 4, L..C7@l(4)
274 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
275 ; LARGE64-NEXT: stfd 1, 0(3)
276 ; LARGE64-NEXT: addi 1, 1, 48
277 ; LARGE64-NEXT: ld 0, 16(1)
278 ; LARGE64-NEXT: mtlr 0
279 ; LARGE64-NEXT: blr
280 entry:
281 store double %Val, ptr @TWInit, align 8
282 ret void
283 }
285 ; Function Attrs: norecurse nounwind readonly willreturn
286 define double @loadsTGUninit() #1 {
287 ; SMALL32-LABEL: loadsTGUninit:
288 ; SMALL32: # %bb.0: # %entry
289 ; SMALL32-NEXT: mflr 0
290 ; SMALL32-NEXT: stwu 1, -32(1)
291 ; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
292 ; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
293 ; SMALL32-NEXT: stw 0, 40(1)
294 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
295 ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
296 ; SMALL32-NEXT: lfd 0, 0(3)
297 ; SMALL32-NEXT: lfd 1, 0(4)
298 ; SMALL32-NEXT: fadd 1, 0, 1
299 ; SMALL32-NEXT: addi 1, 1, 32
300 ; SMALL32-NEXT: lwz 0, 8(1)
301 ; SMALL32-NEXT: mtlr 0
302 ; SMALL32-NEXT: blr
303 ;
304 ; LARGE32-LABEL: loadsTGUninit:
305 ; LARGE32: # %bb.0: # %entry
306 ; LARGE32-NEXT: mflr 0
307 ; LARGE32-NEXT: stwu 1, -32(1)
308 ; LARGE32-NEXT: stw 0, 40(1)
309 ; LARGE32-NEXT: addis 3, L..C0@u(2)
310 ; LARGE32-NEXT: addis 4, L..C1@u(2)
311 ; LARGE32-NEXT: lwz 3, L..C0@l(3)
312 ; LARGE32-NEXT: lwz 4, L..C1@l(4)
313 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
314 ; LARGE32-NEXT: lfd 0, 0(3)
315 ; LARGE32-NEXT: addis 3, L..C8@u(2)
316 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
317 ; LARGE32-NEXT: lfd 1, 0(3)
318 ; LARGE32-NEXT: fadd 1, 0, 1
319 ; LARGE32-NEXT: addi 1, 1, 32
320 ; LARGE32-NEXT: lwz 0, 8(1)
321 ; LARGE32-NEXT: mtlr 0
322 ; LARGE32-NEXT: blr
323 ;
324 ; SMALL64-LABEL: loadsTGUninit:
325 ; SMALL64: # %bb.0: # %entry
326 ; SMALL64-NEXT: mflr 0
327 ; SMALL64-NEXT: stdu 1, -48(1)
328 ; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-lo) @TGUninit
329 ; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGUninit
330 ; SMALL64-NEXT: std 0, 64(1)
331 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
332 ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
333 ; SMALL64-NEXT: lfd 0, 0(3)
334 ; SMALL64-NEXT: lfd 1, 0(4)
335 ; SMALL64-NEXT: fadd 1, 0, 1
336 ; SMALL64-NEXT: addi 1, 1, 48
337 ; SMALL64-NEXT: ld 0, 16(1)
338 ; SMALL64-NEXT: mtlr 0
339 ; SMALL64-NEXT: blr
340 ;
341 ; LARGE64-LABEL: loadsTGUninit:
342 ; LARGE64: # %bb.0: # %entry
343 ; LARGE64-NEXT: mflr 0
344 ; LARGE64-NEXT: stdu 1, -48(1)
345 ; LARGE64-NEXT: addis 3, L..C0@u(2)
346 ; LARGE64-NEXT: addis 4, L..C1@u(2)
347 ; LARGE64-NEXT: std 0, 64(1)
348 ; LARGE64-NEXT: ld 3, L..C0@l(3)
349 ; LARGE64-NEXT: ld 4, L..C1@l(4)
350 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
351 ; LARGE64-NEXT: addis 4, L..C8@u(2)
352 ; LARGE64-NEXT: lfd 0, 0(3)
353 ; LARGE64-NEXT: ld 3, L..C8@l(4)
354 ; LARGE64-NEXT: lfd 1, 0(3)
355 ; LARGE64-NEXT: fadd 1, 0, 1
356 ; LARGE64-NEXT: addi 1, 1, 48
357 ; LARGE64-NEXT: ld 0, 16(1)
358 ; LARGE64-NEXT: mtlr 0
359 ; LARGE64-NEXT: blr
360 entry:
361 %0 = load double, ptr @TGUninit, align 8
362 %1 = load double, ptr @GInit, align 8
363 %add = fadd double %0, %1
364 ret double %add
365 }
367 ; Function Attrs: norecurse nounwind readonly willreturn
368 define double @loadsTGInit() #1 {
369 ; SMALL32-LABEL: loadsTGInit:
370 ; SMALL32: # %bb.0: # %entry
371 ; SMALL32-NEXT: mflr 0
372 ; SMALL32-NEXT: stwu 1, -32(1)
373 ; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-lo) @TGInit
374 ; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
375 ; SMALL32-NEXT: stw 0, 40(1)
376 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
377 ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
378 ; SMALL32-NEXT: lfd 0, 0(3)
379 ; SMALL32-NEXT: lfd 1, 0(4)
380 ; SMALL32-NEXT: fadd 1, 0, 1
381 ; SMALL32-NEXT: addi 1, 1, 32
382 ; SMALL32-NEXT: lwz 0, 8(1)
383 ; SMALL32-NEXT: mtlr 0
384 ; SMALL32-NEXT: blr
385 ;
386 ; LARGE32-LABEL: loadsTGInit:
387 ; LARGE32: # %bb.0: # %entry
388 ; LARGE32-NEXT: mflr 0
389 ; LARGE32-NEXT: stwu 1, -32(1)
390 ; LARGE32-NEXT: stw 0, 40(1)
391 ; LARGE32-NEXT: addis 3, L..C2@u(2)
392 ; LARGE32-NEXT: addis 4, L..C3@u(2)
393 ; LARGE32-NEXT: lwz 3, L..C2@l(3)
394 ; LARGE32-NEXT: lwz 4, L..C3@l(4)
395 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
396 ; LARGE32-NEXT: lfd 0, 0(3)
397 ; LARGE32-NEXT: addis 3, L..C8@u(2)
398 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
399 ; LARGE32-NEXT: lfd 1, 0(3)
400 ; LARGE32-NEXT: fadd 1, 0, 1
401 ; LARGE32-NEXT: addi 1, 1, 32
402 ; LARGE32-NEXT: lwz 0, 8(1)
403 ; LARGE32-NEXT: mtlr 0
404 ; LARGE32-NEXT: blr
405 ;
406 ; SMALL64-LABEL: loadsTGInit:
407 ; SMALL64: # %bb.0: # %entry
408 ; SMALL64-NEXT: mflr 0
409 ; SMALL64-NEXT: stdu 1, -48(1)
410 ; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-lo) @TGInit
411 ; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsgd) @TGInit
412 ; SMALL64-NEXT: std 0, 64(1)
413 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
414 ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
415 ; SMALL64-NEXT: lfd 0, 0(3)
416 ; SMALL64-NEXT: lfd 1, 0(4)
417 ; SMALL64-NEXT: fadd 1, 0, 1
418 ; SMALL64-NEXT: addi 1, 1, 48
419 ; SMALL64-NEXT: ld 0, 16(1)
420 ; SMALL64-NEXT: mtlr 0
421 ; SMALL64-NEXT: blr
422 ;
423 ; LARGE64-LABEL: loadsTGInit:
424 ; LARGE64: # %bb.0: # %entry
425 ; LARGE64-NEXT: mflr 0
426 ; LARGE64-NEXT: stdu 1, -48(1)
427 ; LARGE64-NEXT: addis 3, L..C2@u(2)
428 ; LARGE64-NEXT: addis 4, L..C3@u(2)
429 ; LARGE64-NEXT: std 0, 64(1)
430 ; LARGE64-NEXT: ld 3, L..C2@l(3)
431 ; LARGE64-NEXT: ld 4, L..C3@l(4)
432 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
433 ; LARGE64-NEXT: addis 4, L..C8@u(2)
434 ; LARGE64-NEXT: lfd 0, 0(3)
435 ; LARGE64-NEXT: ld 3, L..C8@l(4)
436 ; LARGE64-NEXT: lfd 1, 0(3)
437 ; LARGE64-NEXT: fadd 1, 0, 1
438 ; LARGE64-NEXT: addi 1, 1, 48
439 ; LARGE64-NEXT: ld 0, 16(1)
440 ; LARGE64-NEXT: mtlr 0
441 ; LARGE64-NEXT: blr
442 entry:
443 %0 = load double, ptr @TGInit, align 8
444 %1 = load double, ptr @GInit, align 8
445 %add = fadd double %0, %1
446 ret double %add
447 }
449 ; Function Attrs: norecurse nounwind readonly willreturn
450 define double @loadsTIInit() #1 {
451 ; SMALL32-LABEL: loadsTIInit:
452 ; SMALL32: # %bb.0: # %entry
453 ; SMALL32-NEXT: mflr 0
454 ; SMALL32-NEXT: stwu 1, -32(1)
455 ; SMALL32-NEXT: lwz 3, L..C4(2) # target-flags(ppc-lo) @TIInit
456 ; SMALL32-NEXT: lwz 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
457 ; SMALL32-NEXT: stw 0, 40(1)
458 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
459 ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
460 ; SMALL32-NEXT: lfd 0, 0(3)
461 ; SMALL32-NEXT: lfd 1, 0(4)
462 ; SMALL32-NEXT: fadd 1, 0, 1
463 ; SMALL32-NEXT: addi 1, 1, 32
464 ; SMALL32-NEXT: lwz 0, 8(1)
465 ; SMALL32-NEXT: mtlr 0
466 ; SMALL32-NEXT: blr
467 ;
468 ; LARGE32-LABEL: loadsTIInit:
469 ; LARGE32: # %bb.0: # %entry
470 ; LARGE32-NEXT: mflr 0
471 ; LARGE32-NEXT: stwu 1, -32(1)
472 ; LARGE32-NEXT: stw 0, 40(1)
473 ; LARGE32-NEXT: addis 3, L..C4@u(2)
474 ; LARGE32-NEXT: addis 4, L..C5@u(2)
475 ; LARGE32-NEXT: lwz 3, L..C4@l(3)
476 ; LARGE32-NEXT: lwz 4, L..C5@l(4)
477 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
478 ; LARGE32-NEXT: lfd 0, 0(3)
479 ; LARGE32-NEXT: addis 3, L..C8@u(2)
480 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
481 ; LARGE32-NEXT: lfd 1, 0(3)
482 ; LARGE32-NEXT: fadd 1, 0, 1
483 ; LARGE32-NEXT: addi 1, 1, 32
484 ; LARGE32-NEXT: lwz 0, 8(1)
485 ; LARGE32-NEXT: mtlr 0
486 ; LARGE32-NEXT: blr
487 ;
488 ; SMALL64-LABEL: loadsTIInit:
489 ; SMALL64: # %bb.0: # %entry
490 ; SMALL64-NEXT: mflr 0
491 ; SMALL64-NEXT: stdu 1, -48(1)
492 ; SMALL64-NEXT: ld 3, L..C4(2) # target-flags(ppc-lo) @TIInit
493 ; SMALL64-NEXT: ld 4, L..C5(2) # target-flags(ppc-tlsgd) @TIInit
494 ; SMALL64-NEXT: std 0, 64(1)
495 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
496 ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
497 ; SMALL64-NEXT: lfd 0, 0(3)
498 ; SMALL64-NEXT: lfd 1, 0(4)
499 ; SMALL64-NEXT: fadd 1, 0, 1
500 ; SMALL64-NEXT: addi 1, 1, 48
501 ; SMALL64-NEXT: ld 0, 16(1)
502 ; SMALL64-NEXT: mtlr 0
503 ; SMALL64-NEXT: blr
504 ;
505 ; LARGE64-LABEL: loadsTIInit:
506 ; LARGE64: # %bb.0: # %entry
507 ; LARGE64-NEXT: mflr 0
508 ; LARGE64-NEXT: stdu 1, -48(1)
509 ; LARGE64-NEXT: addis 3, L..C4@u(2)
510 ; LARGE64-NEXT: addis 4, L..C5@u(2)
511 ; LARGE64-NEXT: std 0, 64(1)
512 ; LARGE64-NEXT: ld 3, L..C4@l(3)
513 ; LARGE64-NEXT: ld 4, L..C5@l(4)
514 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
515 ; LARGE64-NEXT: addis 4, L..C8@u(2)
516 ; LARGE64-NEXT: lfd 0, 0(3)
517 ; LARGE64-NEXT: ld 3, L..C8@l(4)
518 ; LARGE64-NEXT: lfd 1, 0(3)
519 ; LARGE64-NEXT: fadd 1, 0, 1
520 ; LARGE64-NEXT: addi 1, 1, 48
521 ; LARGE64-NEXT: ld 0, 16(1)
522 ; LARGE64-NEXT: mtlr 0
523 ; LARGE64-NEXT: blr
524 entry:
525 %0 = load double, ptr @TIInit, align 8
526 %1 = load double, ptr @GInit, align 8
527 %add = fadd double %0, %1
528 ret double %add
529 }
531 ; Function Attrs: norecurse nounwind readonly willreturn
532 define double @loadsTWInit() #1 {
533 ; SMALL32-LABEL: loadsTWInit:
534 ; SMALL32: # %bb.0: # %entry
535 ; SMALL32-NEXT: mflr 0
536 ; SMALL32-NEXT: stwu 1, -32(1)
537 ; SMALL32-NEXT: lwz 3, L..C6(2) # target-flags(ppc-lo) @TWInit
538 ; SMALL32-NEXT: lwz 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
539 ; SMALL32-NEXT: stw 0, 40(1)
540 ; SMALL32-NEXT: bla .__tls_get_addr[PR]
541 ; SMALL32-NEXT: lwz 4, L..C8(2) # @GInit
542 ; SMALL32-NEXT: lfd 0, 0(3)
543 ; SMALL32-NEXT: lfd 1, 0(4)
544 ; SMALL32-NEXT: fadd 1, 0, 1
545 ; SMALL32-NEXT: addi 1, 1, 32
546 ; SMALL32-NEXT: lwz 0, 8(1)
547 ; SMALL32-NEXT: mtlr 0
548 ; SMALL32-NEXT: blr
549 ;
550 ; LARGE32-LABEL: loadsTWInit:
551 ; LARGE32: # %bb.0: # %entry
552 ; LARGE32-NEXT: mflr 0
553 ; LARGE32-NEXT: stwu 1, -32(1)
554 ; LARGE32-NEXT: stw 0, 40(1)
555 ; LARGE32-NEXT: addis 3, L..C6@u(2)
556 ; LARGE32-NEXT: addis 4, L..C7@u(2)
557 ; LARGE32-NEXT: lwz 3, L..C6@l(3)
558 ; LARGE32-NEXT: lwz 4, L..C7@l(4)
559 ; LARGE32-NEXT: bla .__tls_get_addr[PR]
560 ; LARGE32-NEXT: lfd 0, 0(3)
561 ; LARGE32-NEXT: addis 3, L..C8@u(2)
562 ; LARGE32-NEXT: lwz 3, L..C8@l(3)
563 ; LARGE32-NEXT: lfd 1, 0(3)
564 ; LARGE32-NEXT: fadd 1, 0, 1
565 ; LARGE32-NEXT: addi 1, 1, 32
566 ; LARGE32-NEXT: lwz 0, 8(1)
567 ; LARGE32-NEXT: mtlr 0
568 ; LARGE32-NEXT: blr
569 ;
570 ; SMALL64-LABEL: loadsTWInit:
571 ; SMALL64: # %bb.0: # %entry
572 ; SMALL64-NEXT: mflr 0
573 ; SMALL64-NEXT: stdu 1, -48(1)
574 ; SMALL64-NEXT: ld 3, L..C6(2) # target-flags(ppc-lo) @TWInit
575 ; SMALL64-NEXT: ld 4, L..C7(2) # target-flags(ppc-tlsgd) @TWInit
576 ; SMALL64-NEXT: std 0, 64(1)
577 ; SMALL64-NEXT: bla .__tls_get_addr[PR]
578 ; SMALL64-NEXT: ld 4, L..C8(2) # @GInit
579 ; SMALL64-NEXT: lfd 0, 0(3)
580 ; SMALL64-NEXT: lfd 1, 0(4)
581 ; SMALL64-NEXT: fadd 1, 0, 1
582 ; SMALL64-NEXT: addi 1, 1, 48
583 ; SMALL64-NEXT: ld 0, 16(1)
584 ; SMALL64-NEXT: mtlr 0
585 ; SMALL64-NEXT: blr
586 ;
587 ; LARGE64-LABEL: loadsTWInit:
588 ; LARGE64: # %bb.0: # %entry
589 ; LARGE64-NEXT: mflr 0
590 ; LARGE64-NEXT: stdu 1, -48(1)
591 ; LARGE64-NEXT: addis 3, L..C6@u(2)
592 ; LARGE64-NEXT: addis 4, L..C7@u(2)
593 ; LARGE64-NEXT: std 0, 64(1)
594 ; LARGE64-NEXT: ld 3, L..C6@l(3)
595 ; LARGE64-NEXT: ld 4, L..C7@l(4)
596 ; LARGE64-NEXT: bla .__tls_get_addr[PR]
597 ; LARGE64-NEXT: addis 4, L..C8@u(2)
598 ; LARGE64-NEXT: lfd 0, 0(3)
599 ; LARGE64-NEXT: ld 3, L..C8@l(4)
600 ; LARGE64-NEXT: lfd 1, 0(3)
601 ; LARGE64-NEXT: fadd 1, 0, 1
602 ; LARGE64-NEXT: addi 1, 1, 48
603 ; LARGE64-NEXT: ld 0, 16(1)
604 ; LARGE64-NEXT: mtlr 0
605 ; LARGE64-NEXT: blr
606 entry:
607 %0 = load double, ptr @TWInit, align 8
608 %1 = load double, ptr @GInit, align 8
609 %add = fadd double %0, %1
610 ret double %add
611 }
613 ; External symbol reference checks for .__tls_get_addr
615 ; SMALL32: .extern .__tls_get_addr[PR]
616 ; SMALL64: .extern .__tls_get_addr[PR]
617 ; LARGE32: .extern .__tls_get_addr[PR]
618 ; LARGE64: .extern .__tls_get_addr[PR]
620 ; TOC entry checks
622 ; SMALL32-LABEL: .toc
623 ; SMALL32-LABEL: L..C0:
624 ; SMALL32-NEXT: .tc .TGUninit[TC],TGUninit[TL]@m
625 ; SMALL32-LABEL: L..C1:
626 ; SMALL32-NEXT: .tc TGUninit[TC],TGUninit[TL]@gd
627 ; SMALL32-LABEL: L..C2:
628 ; SMALL32-NEXT: .tc .TGInit[TC],TGInit[TL]@m
629 ; SMALL32-LABEL: L..C3:
630 ; SMALL32-NEXT: .tc TGInit[TC],TGInit[TL]@gd
631 ; SMALL32-LABEL: L..C4:
632 ; SMALL32-NEXT: .tc .TIInit[TC],TIInit[TL]@m
633 ; SMALL32-LABEL: L..C5:
634 ; SMALL32-NEXT: .tc TIInit[TC],TIInit[TL]@gd
635 ; SMALL32-LABEL: L..C6:
636 ; SMALL32-NEXT: .tc .TWInit[TC],TWInit[TL]@m
637 ; SMALL32-LABEL: L..C7:
638 ; SMALL32-NEXT: .tc TWInit[TC],TWInit[TL]@gd
639 ; SMALL32-LABEL: L..C8:
640 ; SMALL32-NEXT: .tc GInit[TC],GInit[RW]
642 ; LARGE32-LABEL: .toc
643 ; LARGE32-LABEL: L..C0:
644 ; LARGE32-NEXT: .tc .TGUninit[TE],TGUninit[TL]@m
645 ; LARGE32-LABEL: L..C1:
646 ; LARGE32-NEXT: .tc TGUninit[TE],TGUninit[TL]@gd
647 ; LARGE32-LABEL: L..C2:
648 ; LARGE32-NEXT: .tc .TGInit[TE],TGInit[TL]@m
649 ; LARGE32-LABEL: L..C3:
650 ; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@gd
651 ; LARGE32-LABEL: L..C4:
652 ; LARGE32-NEXT: .tc .TIInit[TE],TIInit[TL]@m
653 ; LARGE32-LABEL: L..C5:
654 ; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]@gd
655 ; LARGE32-LABEL: L..C6:
656 ; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m
657 ; LARGE32-LABEL: L..C7:
658 ; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL]@gd
659 ; LARGE32-LABEL: L..C8:
660 ; LARGE32-NEXT: .tc GInit[TE],GInit[RW]
662 ; SMALL64-LABEL: .toc
663 ; SMALL64-LABEL: L..C0:
664 ; SMALL64-NEXT: .tc .TGUninit[TC],TGUninit[TL]@m
665 ; SMALL64-LABEL: L..C1:
666 ; SMALL64-NEXT: .tc TGUninit[TC],TGUninit[TL]@gd
667 ; SMALL64-LABEL: L..C2:
668 ; SMALL64-NEXT: .tc .TGInit[TC],TGInit[TL]@m
669 ; SMALL64-LABEL: L..C3:
670 ; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]@gd
671 ; SMALL64-LABEL: L..C4:
672 ; SMALL64-NEXT: .tc .TIInit[TC],TIInit[TL]@m
673 ; SMALL64-LABEL: L..C5:
674 ; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]@gd
675 ; SMALL64-LABEL: L..C6:
676 ; SMALL64-NEXT: .tc .TWInit[TC],TWInit[TL]@m
677 ; SMALL64-LABEL: L..C7:
678 ; SMALL64-NEXT: .tc TWInit[TC],TWInit[TL]@gd
679 ; SMALL64-LABEL: L..C8:
680 ; SMALL64-NEXT: .tc GInit[TC],GInit[RW]
682 ; LARGE64-LABEL: .toc
683 ; LARGE64-LABEL: L..C0:
684 ; LARGE64-NEXT: .tc .TGUninit[TE],TGUninit[TL]@m
685 ; LARGE64-LABEL: L..C1:
686 ; LARGE64-NEXT: .tc TGUninit[TE],TGUninit[TL]@gd
687 ; LARGE64-LABEL: L..C2:
688 ; LARGE64-NEXT: .tc .TGInit[TE],TGInit[TL]@m
689 ; LARGE64-LABEL: L..C3:
690 ; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@gd
691 ; LARGE64-LABEL: L..C4:
692 ; LARGE64-NEXT: .tc .TIInit[TE],TIInit[TL]@m
693 ; LARGE64-LABEL: L..C5:
694 ; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]@gd
695 ; LARGE64-LABEL: L..C6:
696 ; LARGE64-NEXT: .tc .TWInit[TE],TWInit[TL]@m
697 ; LARGE64-LABEL: L..C7:
698 ; LARGE64-NEXT: .tc TWInit[TE],TWInit[TL]@gd
699 ; LARGE64-LABEL: L..C8:
700 ; LARGE64-NEXT: .tc GInit[TE],GInit[RW]
703 attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" }
704 attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" }