| blob | adfdc94e7640057a48955c0f1320656e6e731485 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
3 ; RUN: -mtriple powerpc64-ibm-aix-xcoff -code-model=large < %s | \
4 ; RUN: FileCheck %s -check-prefix=LARGE64
5 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
6 ; RUN: -mtriple powerpc64-ibm-aix-xcoff -code-model=small < %s | \
7 ; RUN: FileCheck %s -check-prefix=SMALL64
8 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
9 ; RUN: -mtriple powerpc-ibm-aix-xcoff -code-model=large < %s | \
10 ; RUN: FileCheck %s -check-prefix=LARGE32
11 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
12 ; RUN: -mtriple powerpc-ibm-aix-xcoff -code-model=small < %s | \
13 ; RUN: FileCheck %s -check-prefix=SMALL32
15 @global_int_zero = thread_local(initialexec) global i32 0, align 4
16 @global_int_nonzero = thread_local(initialexec) global i32 1, align 4
17 @intern_int_zero = internal thread_local(initialexec) global i32 0, align 4
18 @intern_int_nonzero = internal thread_local(initialexec) global i32 1, align 4
20 @global_long_zero = thread_local(initialexec) global i64 0, align 8
21 @global_long_nonzero = thread_local(initialexec) global i64 1, align 8
22 @intern_long_zero = internal thread_local(initialexec) global i64 0, align 8
23 @intern_long_nonzero = internal thread_local(initialexec) global i64 1, align 8
25 @global_float_zero = thread_local(initialexec) global float 0.000000, align 4
26 @global_float_nonzero = thread_local(initialexec) global float 1.000000, align 4
27 @intern_float_zero = internal thread_local(initialexec) global float 0.000000, align 4
28 @intern_float_nonzero = internal thread_local(initialexec) global float 1.000000, align 4
30 @global_double_zero = thread_local(initialexec) global double 0.000000, align 8
31 @global_double_nonzero = thread_local(initialexec) global double 1.000000, align 8
32 @intern_double_zero = internal thread_local(initialexec) global double 0.000000, align 8
33 @intern_double_nonzero = internal thread_local(initialexec) global double 1.000000, align 8
35 define void @store_global_int_zero(i32 noundef signext %i) {
36 ; LARGE64-LABEL: store_global_int_zero:
37 ; LARGE64: # %bb.0: # %entry
38 ; LARGE64-NEXT: addis r4, L..C0@u(r2)
39 ; LARGE64-NEXT: ld r4, L..C0@l(r4)
40 ; LARGE64-NEXT: stwx r3, r13, r4
41 ; LARGE64-NEXT: blr
42 ;
43 ; SMALL64-LABEL: store_global_int_zero:
44 ; SMALL64: # %bb.0: # %entry
45 ; SMALL64-NEXT: ld r4, L..C0(r2) # target-flags(ppc-tprel) @global_int_zero
46 ; SMALL64-NEXT: stwx r3, r13, r4
47 ; SMALL64-NEXT: blr
48 ;
49 ; LARGE32-LABEL: store_global_int_zero:
50 ; LARGE32: # %bb.0: # %entry
51 ; LARGE32-NEXT: mflr r0
52 ; LARGE32-NEXT: stwu r1, -32(r1)
53 ; LARGE32-NEXT: stw r0, 40(r1)
54 ; LARGE32-NEXT: mr r4, r3
55 ; LARGE32-NEXT: addis r3, L..C0@u(r2)
56 ; LARGE32-NEXT: lwz r5, L..C0@l(r3)
57 ; LARGE32-NEXT: bla .__get_tpointer[PR]
58 ; LARGE32-NEXT: stwx r4, r3, r5
59 ; LARGE32-NEXT: addi r1, r1, 32
60 ; LARGE32-NEXT: lwz r0, 8(r1)
61 ; LARGE32-NEXT: mtlr r0
62 ; LARGE32-NEXT: blr
63 ;
64 ; SMALL32-LABEL: store_global_int_zero:
65 ; SMALL32: # %bb.0: # %entry
66 ; SMALL32-NEXT: mflr r0
67 ; SMALL32-NEXT: stwu r1, -32(r1)
68 ; SMALL32-NEXT: lwz r5, L..C0(r2) # target-flags(ppc-tprel) @global_int_zero
69 ; SMALL32-NEXT: mr r4, r3
70 ; SMALL32-NEXT: bla .__get_tpointer[PR]
71 ; SMALL32-NEXT: stw r0, 40(r1)
72 ; SMALL32-NEXT: stwx r4, r3, r5
73 ; SMALL32-NEXT: addi r1, r1, 32
74 ; SMALL32-NEXT: lwz r0, 8(r1)
75 ; SMALL32-NEXT: mtlr r0
76 ; SMALL32-NEXT: blr
77 entry:
78 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_int_zero)
79 store i32 %i, ptr %addr, align 4
80 ret void
81 }
83 define void @store_global_int_nonzero(i32 noundef signext %i) {
84 ; LARGE64-LABEL: store_global_int_nonzero:
85 ; LARGE64: # %bb.0: # %entry
86 ; LARGE64-NEXT: addis r4, L..C1@u(r2)
87 ; LARGE64-NEXT: ld r4, L..C1@l(r4)
88 ; LARGE64-NEXT: stwx r3, r13, r4
89 ; LARGE64-NEXT: blr
90 ;
91 ; SMALL64-LABEL: store_global_int_nonzero:
92 ; SMALL64: # %bb.0: # %entry
93 ; SMALL64-NEXT: ld r4, L..C1(r2) # target-flags(ppc-tprel) @global_int_nonzero
94 ; SMALL64-NEXT: stwx r3, r13, r4
95 ; SMALL64-NEXT: blr
96 ;
97 ; LARGE32-LABEL: store_global_int_nonzero:
98 ; LARGE32: # %bb.0: # %entry
99 ; LARGE32-NEXT: mflr r0
100 ; LARGE32-NEXT: stwu r1, -32(r1)
101 ; LARGE32-NEXT: stw r0, 40(r1)
102 ; LARGE32-NEXT: mr r4, r3
103 ; LARGE32-NEXT: addis r3, L..C1@u(r2)
104 ; LARGE32-NEXT: lwz r5, L..C1@l(r3)
105 ; LARGE32-NEXT: bla .__get_tpointer[PR]
106 ; LARGE32-NEXT: stwx r4, r3, r5
107 ; LARGE32-NEXT: addi r1, r1, 32
108 ; LARGE32-NEXT: lwz r0, 8(r1)
109 ; LARGE32-NEXT: mtlr r0
110 ; LARGE32-NEXT: blr
111 ;
112 ; SMALL32-LABEL: store_global_int_nonzero:
113 ; SMALL32: # %bb.0: # %entry
114 ; SMALL32-NEXT: mflr r0
115 ; SMALL32-NEXT: stwu r1, -32(r1)
116 ; SMALL32-NEXT: lwz r5, L..C1(r2) # target-flags(ppc-tprel) @global_int_nonzero
117 ; SMALL32-NEXT: mr r4, r3
118 ; SMALL32-NEXT: bla .__get_tpointer[PR]
119 ; SMALL32-NEXT: stw r0, 40(r1)
120 ; SMALL32-NEXT: stwx r4, r3, r5
121 ; SMALL32-NEXT: addi r1, r1, 32
122 ; SMALL32-NEXT: lwz r0, 8(r1)
123 ; SMALL32-NEXT: mtlr r0
124 ; SMALL32-NEXT: blr
125 entry:
126 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_int_nonzero)
127 store i32 %i, ptr %addr, align 4
128 ret void
129 }
131 define void @store_intern_int_zero(i32 noundef signext %i) {
132 ; LARGE64-LABEL: store_intern_int_zero:
133 ; LARGE64: # %bb.0: # %entry
134 ; LARGE64-NEXT: addis r4, L..C2@u(r2)
135 ; LARGE64-NEXT: ld r4, L..C2@l(r4)
136 ; LARGE64-NEXT: stwx r3, r13, r4
137 ; LARGE64-NEXT: blr
138 ;
139 ; SMALL64-LABEL: store_intern_int_zero:
140 ; SMALL64: # %bb.0: # %entry
141 ; SMALL64-NEXT: ld r4, L..C2(r2) # target-flags(ppc-tprel) @intern_int_zero
142 ; SMALL64-NEXT: stwx r3, r13, r4
143 ; SMALL64-NEXT: blr
144 ;
145 ; LARGE32-LABEL: store_intern_int_zero:
146 ; LARGE32: # %bb.0: # %entry
147 ; LARGE32-NEXT: mflr r0
148 ; LARGE32-NEXT: stwu r1, -32(r1)
149 ; LARGE32-NEXT: stw r0, 40(r1)
150 ; LARGE32-NEXT: mr r4, r3
151 ; LARGE32-NEXT: addis r3, L..C2@u(r2)
152 ; LARGE32-NEXT: lwz r5, L..C2@l(r3)
153 ; LARGE32-NEXT: bla .__get_tpointer[PR]
154 ; LARGE32-NEXT: stwx r4, r3, r5
155 ; LARGE32-NEXT: addi r1, r1, 32
156 ; LARGE32-NEXT: lwz r0, 8(r1)
157 ; LARGE32-NEXT: mtlr r0
158 ; LARGE32-NEXT: blr
159 ;
160 ; SMALL32-LABEL: store_intern_int_zero:
161 ; SMALL32: # %bb.0: # %entry
162 ; SMALL32-NEXT: mflr r0
163 ; SMALL32-NEXT: stwu r1, -32(r1)
164 ; SMALL32-NEXT: lwz r5, L..C2(r2) # target-flags(ppc-tprel) @intern_int_zero
165 ; SMALL32-NEXT: mr r4, r3
166 ; SMALL32-NEXT: bla .__get_tpointer[PR]
167 ; SMALL32-NEXT: stw r0, 40(r1)
168 ; SMALL32-NEXT: stwx r4, r3, r5
169 ; SMALL32-NEXT: addi r1, r1, 32
170 ; SMALL32-NEXT: lwz r0, 8(r1)
171 ; SMALL32-NEXT: mtlr r0
172 ; SMALL32-NEXT: blr
173 entry:
174 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_int_zero)
175 store i32 %i, ptr %addr, align 4
176 ret void
177 }
179 define void @store_intern_int_nonzero(i32 noundef signext %i) {
180 ; LARGE64-LABEL: store_intern_int_nonzero:
181 ; LARGE64: # %bb.0: # %entry
182 ; LARGE64-NEXT: addis r4, L..C3@u(r2)
183 ; LARGE64-NEXT: ld r4, L..C3@l(r4)
184 ; LARGE64-NEXT: stwx r3, r13, r4
185 ; LARGE64-NEXT: blr
186 ;
187 ; SMALL64-LABEL: store_intern_int_nonzero:
188 ; SMALL64: # %bb.0: # %entry
189 ; SMALL64-NEXT: ld r4, L..C3(r2) # target-flags(ppc-tprel) @intern_int_nonzero
190 ; SMALL64-NEXT: stwx r3, r13, r4
191 ; SMALL64-NEXT: blr
192 ;
193 ; LARGE32-LABEL: store_intern_int_nonzero:
194 ; LARGE32: # %bb.0: # %entry
195 ; LARGE32-NEXT: mflr r0
196 ; LARGE32-NEXT: stwu r1, -32(r1)
197 ; LARGE32-NEXT: stw r0, 40(r1)
198 ; LARGE32-NEXT: mr r4, r3
199 ; LARGE32-NEXT: addis r3, L..C3@u(r2)
200 ; LARGE32-NEXT: lwz r5, L..C3@l(r3)
201 ; LARGE32-NEXT: bla .__get_tpointer[PR]
202 ; LARGE32-NEXT: stwx r4, r3, r5
203 ; LARGE32-NEXT: addi r1, r1, 32
204 ; LARGE32-NEXT: lwz r0, 8(r1)
205 ; LARGE32-NEXT: mtlr r0
206 ; LARGE32-NEXT: blr
207 ;
208 ; SMALL32-LABEL: store_intern_int_nonzero:
209 ; SMALL32: # %bb.0: # %entry
210 ; SMALL32-NEXT: mflr r0
211 ; SMALL32-NEXT: stwu r1, -32(r1)
212 ; SMALL32-NEXT: lwz r5, L..C3(r2) # target-flags(ppc-tprel) @intern_int_nonzero
213 ; SMALL32-NEXT: mr r4, r3
214 ; SMALL32-NEXT: bla .__get_tpointer[PR]
215 ; SMALL32-NEXT: stw r0, 40(r1)
216 ; SMALL32-NEXT: stwx r4, r3, r5
217 ; SMALL32-NEXT: addi r1, r1, 32
218 ; SMALL32-NEXT: lwz r0, 8(r1)
219 ; SMALL32-NEXT: mtlr r0
220 ; SMALL32-NEXT: blr
221 entry:
222 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_int_nonzero)
223 store i32 %i, ptr %addr, align 4
224 ret void
225 }
227 define signext i32 @load_global_int_zero() {
228 ; LARGE64-LABEL: load_global_int_zero:
229 ; LARGE64: # %bb.0: # %entry
230 ; LARGE64-NEXT: addis r3, L..C0@u(r2)
231 ; LARGE64-NEXT: ld r3, L..C0@l(r3)
232 ; LARGE64-NEXT: lwax r3, r13, r3
233 ; LARGE64-NEXT: blr
234 ;
235 ; SMALL64-LABEL: load_global_int_zero:
236 ; SMALL64: # %bb.0: # %entry
237 ; SMALL64-NEXT: ld r3, L..C0(r2) # target-flags(ppc-tprel) @global_int_zero
238 ; SMALL64-NEXT: lwax r3, r13, r3
239 ; SMALL64-NEXT: blr
240 ;
241 ; LARGE32-LABEL: load_global_int_zero:
242 ; LARGE32: # %bb.0: # %entry
243 ; LARGE32-NEXT: mflr r0
244 ; LARGE32-NEXT: stwu r1, -32(r1)
245 ; LARGE32-NEXT: stw r0, 40(r1)
246 ; LARGE32-NEXT: addis r3, L..C0@u(r2)
247 ; LARGE32-NEXT: lwz r4, L..C0@l(r3)
248 ; LARGE32-NEXT: bla .__get_tpointer[PR]
249 ; LARGE32-NEXT: lwzx r3, r3, r4
250 ; LARGE32-NEXT: addi r1, r1, 32
251 ; LARGE32-NEXT: lwz r0, 8(r1)
252 ; LARGE32-NEXT: mtlr r0
253 ; LARGE32-NEXT: blr
254 ;
255 ; SMALL32-LABEL: load_global_int_zero:
256 ; SMALL32: # %bb.0: # %entry
257 ; SMALL32-NEXT: mflr r0
258 ; SMALL32-NEXT: stwu r1, -32(r1)
259 ; SMALL32-NEXT: lwz r4, L..C0(r2) # target-flags(ppc-tprel) @global_int_zero
260 ; SMALL32-NEXT: stw r0, 40(r1)
261 ; SMALL32-NEXT: bla .__get_tpointer[PR]
262 ; SMALL32-NEXT: lwzx r3, r3, r4
263 ; SMALL32-NEXT: addi r1, r1, 32
264 ; SMALL32-NEXT: lwz r0, 8(r1)
265 ; SMALL32-NEXT: mtlr r0
266 ; SMALL32-NEXT: blr
267 entry:
268 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_int_zero)
269 %val = load i32, ptr %addr, align 4
270 ret i32 %val
271 }
273 define signext i32 @load_global_int_nonzero() {
274 ; LARGE64-LABEL: load_global_int_nonzero:
275 ; LARGE64: # %bb.0: # %entry
276 ; LARGE64-NEXT: addis r3, L..C1@u(r2)
277 ; LARGE64-NEXT: ld r3, L..C1@l(r3)
278 ; LARGE64-NEXT: lwax r3, r13, r3
279 ; LARGE64-NEXT: blr
280 ;
281 ; SMALL64-LABEL: load_global_int_nonzero:
282 ; SMALL64: # %bb.0: # %entry
283 ; SMALL64-NEXT: ld r3, L..C1(r2) # target-flags(ppc-tprel) @global_int_nonzero
284 ; SMALL64-NEXT: lwax r3, r13, r3
285 ; SMALL64-NEXT: blr
286 ;
287 ; LARGE32-LABEL: load_global_int_nonzero:
288 ; LARGE32: # %bb.0: # %entry
289 ; LARGE32-NEXT: mflr r0
290 ; LARGE32-NEXT: stwu r1, -32(r1)
291 ; LARGE32-NEXT: stw r0, 40(r1)
292 ; LARGE32-NEXT: addis r3, L..C1@u(r2)
293 ; LARGE32-NEXT: lwz r4, L..C1@l(r3)
294 ; LARGE32-NEXT: bla .__get_tpointer[PR]
295 ; LARGE32-NEXT: lwzx r3, r3, r4
296 ; LARGE32-NEXT: addi r1, r1, 32
297 ; LARGE32-NEXT: lwz r0, 8(r1)
298 ; LARGE32-NEXT: mtlr r0
299 ; LARGE32-NEXT: blr
300 ;
301 ; SMALL32-LABEL: load_global_int_nonzero:
302 ; SMALL32: # %bb.0: # %entry
303 ; SMALL32-NEXT: mflr r0
304 ; SMALL32-NEXT: stwu r1, -32(r1)
305 ; SMALL32-NEXT: lwz r4, L..C1(r2) # target-flags(ppc-tprel) @global_int_nonzero
306 ; SMALL32-NEXT: stw r0, 40(r1)
307 ; SMALL32-NEXT: bla .__get_tpointer[PR]
308 ; SMALL32-NEXT: lwzx r3, r3, r4
309 ; SMALL32-NEXT: addi r1, r1, 32
310 ; SMALL32-NEXT: lwz r0, 8(r1)
311 ; SMALL32-NEXT: mtlr r0
312 ; SMALL32-NEXT: blr
313 entry:
314 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_int_nonzero)
315 %val = load i32, ptr %addr, align 4
316 ret i32 %val
317 }
319 define signext i32 @load_intern_int_zero() {
320 ; LARGE64-LABEL: load_intern_int_zero:
321 ; LARGE64: # %bb.0: # %entry
322 ; LARGE64-NEXT: addis r3, L..C2@u(r2)
323 ; LARGE64-NEXT: ld r3, L..C2@l(r3)
324 ; LARGE64-NEXT: lwax r3, r13, r3
325 ; LARGE64-NEXT: blr
326 ;
327 ; SMALL64-LABEL: load_intern_int_zero:
328 ; SMALL64: # %bb.0: # %entry
329 ; SMALL64-NEXT: ld r3, L..C2(r2) # target-flags(ppc-tprel) @intern_int_zero
330 ; SMALL64-NEXT: lwax r3, r13, r3
331 ; SMALL64-NEXT: blr
332 ;
333 ; LARGE32-LABEL: load_intern_int_zero:
334 ; LARGE32: # %bb.0: # %entry
335 ; LARGE32-NEXT: mflr r0
336 ; LARGE32-NEXT: stwu r1, -32(r1)
337 ; LARGE32-NEXT: stw r0, 40(r1)
338 ; LARGE32-NEXT: addis r3, L..C2@u(r2)
339 ; LARGE32-NEXT: lwz r4, L..C2@l(r3)
340 ; LARGE32-NEXT: bla .__get_tpointer[PR]
341 ; LARGE32-NEXT: lwzx r3, r3, r4
342 ; LARGE32-NEXT: addi r1, r1, 32
343 ; LARGE32-NEXT: lwz r0, 8(r1)
344 ; LARGE32-NEXT: mtlr r0
345 ; LARGE32-NEXT: blr
346 ;
347 ; SMALL32-LABEL: load_intern_int_zero:
348 ; SMALL32: # %bb.0: # %entry
349 ; SMALL32-NEXT: mflr r0
350 ; SMALL32-NEXT: stwu r1, -32(r1)
351 ; SMALL32-NEXT: lwz r4, L..C2(r2) # target-flags(ppc-tprel) @intern_int_zero
352 ; SMALL32-NEXT: stw r0, 40(r1)
353 ; SMALL32-NEXT: bla .__get_tpointer[PR]
354 ; SMALL32-NEXT: lwzx r3, r3, r4
355 ; SMALL32-NEXT: addi r1, r1, 32
356 ; SMALL32-NEXT: lwz r0, 8(r1)
357 ; SMALL32-NEXT: mtlr r0
358 ; SMALL32-NEXT: blr
359 entry:
360 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_int_zero)
361 %val = load i32, ptr %addr, align 4
362 ret i32 %val
363 }
365 define signext i32 @load_intern_int_nonzero() {
366 ; LARGE64-LABEL: load_intern_int_nonzero:
367 ; LARGE64: # %bb.0: # %entry
368 ; LARGE64-NEXT: addis r3, L..C3@u(r2)
369 ; LARGE64-NEXT: ld r3, L..C3@l(r3)
370 ; LARGE64-NEXT: lwax r3, r13, r3
371 ; LARGE64-NEXT: blr
372 ;
373 ; SMALL64-LABEL: load_intern_int_nonzero:
374 ; SMALL64: # %bb.0: # %entry
375 ; SMALL64-NEXT: ld r3, L..C3(r2) # target-flags(ppc-tprel) @intern_int_nonzero
376 ; SMALL64-NEXT: lwax r3, r13, r3
377 ; SMALL64-NEXT: blr
378 ;
379 ; LARGE32-LABEL: load_intern_int_nonzero:
380 ; LARGE32: # %bb.0: # %entry
381 ; LARGE32-NEXT: mflr r0
382 ; LARGE32-NEXT: stwu r1, -32(r1)
383 ; LARGE32-NEXT: stw r0, 40(r1)
384 ; LARGE32-NEXT: addis r3, L..C3@u(r2)
385 ; LARGE32-NEXT: lwz r4, L..C3@l(r3)
386 ; LARGE32-NEXT: bla .__get_tpointer[PR]
387 ; LARGE32-NEXT: lwzx r3, r3, r4
388 ; LARGE32-NEXT: addi r1, r1, 32
389 ; LARGE32-NEXT: lwz r0, 8(r1)
390 ; LARGE32-NEXT: mtlr r0
391 ; LARGE32-NEXT: blr
392 ;
393 ; SMALL32-LABEL: load_intern_int_nonzero:
394 ; SMALL32: # %bb.0: # %entry
395 ; SMALL32-NEXT: mflr r0
396 ; SMALL32-NEXT: stwu r1, -32(r1)
397 ; SMALL32-NEXT: lwz r4, L..C3(r2) # target-flags(ppc-tprel) @intern_int_nonzero
398 ; SMALL32-NEXT: stw r0, 40(r1)
399 ; SMALL32-NEXT: bla .__get_tpointer[PR]
400 ; SMALL32-NEXT: lwzx r3, r3, r4
401 ; SMALL32-NEXT: addi r1, r1, 32
402 ; SMALL32-NEXT: lwz r0, 8(r1)
403 ; SMALL32-NEXT: mtlr r0
404 ; SMALL32-NEXT: blr
405 entry:
406 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_int_nonzero)
407 %val = load i32, ptr %addr, align 4
408 ret i32 %val
409 }
411 define void @store_global_long_zero(i64 noundef %i) {
412 ; LARGE64-LABEL: store_global_long_zero:
413 ; LARGE64: # %bb.0: # %entry
414 ; LARGE64-NEXT: addis r4, L..C4@u(r2)
415 ; LARGE64-NEXT: ld r4, L..C4@l(r4)
416 ; LARGE64-NEXT: stdx r3, r13, r4
417 ; LARGE64-NEXT: blr
418 ;
419 ; SMALL64-LABEL: store_global_long_zero:
420 ; SMALL64: # %bb.0: # %entry
421 ; SMALL64-NEXT: ld r4, L..C4(r2) # target-flags(ppc-tprel) @global_long_zero
422 ; SMALL64-NEXT: stdx r3, r13, r4
423 ; SMALL64-NEXT: blr
424 ;
425 ; LARGE32-LABEL: store_global_long_zero:
426 ; LARGE32: # %bb.0: # %entry
427 ; LARGE32-NEXT: mflr r0
428 ; LARGE32-NEXT: stwu r1, -32(r1)
429 ; LARGE32-NEXT: stw r0, 40(r1)
430 ; LARGE32-NEXT: mr r5, r3
431 ; LARGE32-NEXT: addis r3, L..C4@u(r2)
432 ; LARGE32-NEXT: lwz r6, L..C4@l(r3)
433 ; LARGE32-NEXT: bla .__get_tpointer[PR]
434 ; LARGE32-NEXT: add r3, r3, r6
435 ; LARGE32-NEXT: stw r4, 4(r3)
436 ; LARGE32-NEXT: stw r5, 0(r3)
437 ; LARGE32-NEXT: addi r1, r1, 32
438 ; LARGE32-NEXT: lwz r0, 8(r1)
439 ; LARGE32-NEXT: mtlr r0
440 ; LARGE32-NEXT: blr
441 ;
442 ; SMALL32-LABEL: store_global_long_zero:
443 ; SMALL32: # %bb.0: # %entry
444 ; SMALL32-NEXT: mflr r0
445 ; SMALL32-NEXT: stwu r1, -32(r1)
446 ; SMALL32-NEXT: lwz r6, L..C4(r2) # target-flags(ppc-tprel) @global_long_zero
447 ; SMALL32-NEXT: mr r5, r3
448 ; SMALL32-NEXT: bla .__get_tpointer[PR]
449 ; SMALL32-NEXT: stw r0, 40(r1)
450 ; SMALL32-NEXT: add r3, r3, r6
451 ; SMALL32-NEXT: stw r4, 4(r3)
452 ; SMALL32-NEXT: stw r5, 0(r3)
453 ; SMALL32-NEXT: addi r1, r1, 32
454 ; SMALL32-NEXT: lwz r0, 8(r1)
455 ; SMALL32-NEXT: mtlr r0
456 ; SMALL32-NEXT: blr
457 entry:
458 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_long_zero)
459 store i64 %i, ptr %addr, align 8
460 ret void
461 }
463 define void @store_global_long_nonzero(i64 noundef %i) {
464 ; LARGE64-LABEL: store_global_long_nonzero:
465 ; LARGE64: # %bb.0: # %entry
466 ; LARGE64-NEXT: addis r4, L..C5@u(r2)
467 ; LARGE64-NEXT: ld r4, L..C5@l(r4)
468 ; LARGE64-NEXT: stdx r3, r13, r4
469 ; LARGE64-NEXT: blr
470 ;
471 ; SMALL64-LABEL: store_global_long_nonzero:
472 ; SMALL64: # %bb.0: # %entry
473 ; SMALL64-NEXT: ld r4, L..C5(r2) # target-flags(ppc-tprel) @global_long_nonzero
474 ; SMALL64-NEXT: stdx r3, r13, r4
475 ; SMALL64-NEXT: blr
476 ;
477 ; LARGE32-LABEL: store_global_long_nonzero:
478 ; LARGE32: # %bb.0: # %entry
479 ; LARGE32-NEXT: mflr r0
480 ; LARGE32-NEXT: stwu r1, -32(r1)
481 ; LARGE32-NEXT: stw r0, 40(r1)
482 ; LARGE32-NEXT: mr r5, r3
483 ; LARGE32-NEXT: addis r3, L..C5@u(r2)
484 ; LARGE32-NEXT: lwz r6, L..C5@l(r3)
485 ; LARGE32-NEXT: bla .__get_tpointer[PR]
486 ; LARGE32-NEXT: add r3, r3, r6
487 ; LARGE32-NEXT: stw r4, 4(r3)
488 ; LARGE32-NEXT: stw r5, 0(r3)
489 ; LARGE32-NEXT: addi r1, r1, 32
490 ; LARGE32-NEXT: lwz r0, 8(r1)
491 ; LARGE32-NEXT: mtlr r0
492 ; LARGE32-NEXT: blr
493 ;
494 ; SMALL32-LABEL: store_global_long_nonzero:
495 ; SMALL32: # %bb.0: # %entry
496 ; SMALL32-NEXT: mflr r0
497 ; SMALL32-NEXT: stwu r1, -32(r1)
498 ; SMALL32-NEXT: lwz r6, L..C5(r2) # target-flags(ppc-tprel) @global_long_nonzero
499 ; SMALL32-NEXT: mr r5, r3
500 ; SMALL32-NEXT: bla .__get_tpointer[PR]
501 ; SMALL32-NEXT: stw r0, 40(r1)
502 ; SMALL32-NEXT: add r3, r3, r6
503 ; SMALL32-NEXT: stw r4, 4(r3)
504 ; SMALL32-NEXT: stw r5, 0(r3)
505 ; SMALL32-NEXT: addi r1, r1, 32
506 ; SMALL32-NEXT: lwz r0, 8(r1)
507 ; SMALL32-NEXT: mtlr r0
508 ; SMALL32-NEXT: blr
509 entry:
510 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_long_nonzero)
511 store i64 %i, ptr %addr, align 8
512 ret void
513 }
515 define void @store_intern_long_zero(i64 noundef %i) {
516 ; LARGE64-LABEL: store_intern_long_zero:
517 ; LARGE64: # %bb.0: # %entry
518 ; LARGE64-NEXT: addis r4, L..C6@u(r2)
519 ; LARGE64-NEXT: ld r4, L..C6@l(r4)
520 ; LARGE64-NEXT: stdx r3, r13, r4
521 ; LARGE64-NEXT: blr
522 ;
523 ; SMALL64-LABEL: store_intern_long_zero:
524 ; SMALL64: # %bb.0: # %entry
525 ; SMALL64-NEXT: ld r4, L..C6(r2) # target-flags(ppc-tprel) @intern_long_zero
526 ; SMALL64-NEXT: stdx r3, r13, r4
527 ; SMALL64-NEXT: blr
528 ;
529 ; LARGE32-LABEL: store_intern_long_zero:
530 ; LARGE32: # %bb.0: # %entry
531 ; LARGE32-NEXT: mflr r0
532 ; LARGE32-NEXT: stwu r1, -32(r1)
533 ; LARGE32-NEXT: stw r0, 40(r1)
534 ; LARGE32-NEXT: mr r5, r3
535 ; LARGE32-NEXT: addis r3, L..C6@u(r2)
536 ; LARGE32-NEXT: lwz r6, L..C6@l(r3)
537 ; LARGE32-NEXT: bla .__get_tpointer[PR]
538 ; LARGE32-NEXT: add r3, r3, r6
539 ; LARGE32-NEXT: stw r4, 4(r3)
540 ; LARGE32-NEXT: stw r5, 0(r3)
541 ; LARGE32-NEXT: addi r1, r1, 32
542 ; LARGE32-NEXT: lwz r0, 8(r1)
543 ; LARGE32-NEXT: mtlr r0
544 ; LARGE32-NEXT: blr
545 ;
546 ; SMALL32-LABEL: store_intern_long_zero:
547 ; SMALL32: # %bb.0: # %entry
548 ; SMALL32-NEXT: mflr r0
549 ; SMALL32-NEXT: stwu r1, -32(r1)
550 ; SMALL32-NEXT: lwz r6, L..C6(r2) # target-flags(ppc-tprel) @intern_long_zero
551 ; SMALL32-NEXT: mr r5, r3
552 ; SMALL32-NEXT: bla .__get_tpointer[PR]
553 ; SMALL32-NEXT: stw r0, 40(r1)
554 ; SMALL32-NEXT: add r3, r3, r6
555 ; SMALL32-NEXT: stw r4, 4(r3)
556 ; SMALL32-NEXT: stw r5, 0(r3)
557 ; SMALL32-NEXT: addi r1, r1, 32
558 ; SMALL32-NEXT: lwz r0, 8(r1)
559 ; SMALL32-NEXT: mtlr r0
560 ; SMALL32-NEXT: blr
561 entry:
562 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_long_zero)
563 store i64 %i, ptr %addr, align 8
564 ret void
565 }
567 define void @store_intern_long_nonzero(i64 noundef %i) {
568 ; LARGE64-LABEL: store_intern_long_nonzero:
569 ; LARGE64: # %bb.0: # %entry
570 ; LARGE64-NEXT: addis r4, L..C7@u(r2)
571 ; LARGE64-NEXT: ld r4, L..C7@l(r4)
572 ; LARGE64-NEXT: stdx r3, r13, r4
573 ; LARGE64-NEXT: blr
574 ;
575 ; SMALL64-LABEL: store_intern_long_nonzero:
576 ; SMALL64: # %bb.0: # %entry
577 ; SMALL64-NEXT: ld r4, L..C7(r2) # target-flags(ppc-tprel) @intern_long_nonzero
578 ; SMALL64-NEXT: stdx r3, r13, r4
579 ; SMALL64-NEXT: blr
580 ;
581 ; LARGE32-LABEL: store_intern_long_nonzero:
582 ; LARGE32: # %bb.0: # %entry
583 ; LARGE32-NEXT: mflr r0
584 ; LARGE32-NEXT: stwu r1, -32(r1)
585 ; LARGE32-NEXT: stw r0, 40(r1)
586 ; LARGE32-NEXT: mr r5, r3
587 ; LARGE32-NEXT: addis r3, L..C7@u(r2)
588 ; LARGE32-NEXT: lwz r6, L..C7@l(r3)
589 ; LARGE32-NEXT: bla .__get_tpointer[PR]
590 ; LARGE32-NEXT: add r3, r3, r6
591 ; LARGE32-NEXT: stw r4, 4(r3)
592 ; LARGE32-NEXT: stw r5, 0(r3)
593 ; LARGE32-NEXT: addi r1, r1, 32
594 ; LARGE32-NEXT: lwz r0, 8(r1)
595 ; LARGE32-NEXT: mtlr r0
596 ; LARGE32-NEXT: blr
597 ;
598 ; SMALL32-LABEL: store_intern_long_nonzero:
599 ; SMALL32: # %bb.0: # %entry
600 ; SMALL32-NEXT: mflr r0
601 ; SMALL32-NEXT: stwu r1, -32(r1)
602 ; SMALL32-NEXT: lwz r6, L..C7(r2) # target-flags(ppc-tprel) @intern_long_nonzero
603 ; SMALL32-NEXT: mr r5, r3
604 ; SMALL32-NEXT: bla .__get_tpointer[PR]
605 ; SMALL32-NEXT: stw r0, 40(r1)
606 ; SMALL32-NEXT: add r3, r3, r6
607 ; SMALL32-NEXT: stw r4, 4(r3)
608 ; SMALL32-NEXT: stw r5, 0(r3)
609 ; SMALL32-NEXT: addi r1, r1, 32
610 ; SMALL32-NEXT: lwz r0, 8(r1)
611 ; SMALL32-NEXT: mtlr r0
612 ; SMALL32-NEXT: blr
613 entry:
614 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_long_nonzero)
615 store i64 %i, ptr %addr, align 8
616 ret void
617 }
619 define i64 @load_global_long_zero() {
620 ; LARGE64-LABEL: load_global_long_zero:
621 ; LARGE64: # %bb.0: # %entry
622 ; LARGE64-NEXT: addis r3, L..C4@u(r2)
623 ; LARGE64-NEXT: ld r3, L..C4@l(r3)
624 ; LARGE64-NEXT: ldx r3, r13, r3
625 ; LARGE64-NEXT: blr
626 ;
627 ; SMALL64-LABEL: load_global_long_zero:
628 ; SMALL64: # %bb.0: # %entry
629 ; SMALL64-NEXT: ld r3, L..C4(r2) # target-flags(ppc-tprel) @global_long_zero
630 ; SMALL64-NEXT: ldx r3, r13, r3
631 ; SMALL64-NEXT: blr
632 ;
633 ; LARGE32-LABEL: load_global_long_zero:
634 ; LARGE32: # %bb.0: # %entry
635 ; LARGE32-NEXT: mflr r0
636 ; LARGE32-NEXT: stwu r1, -32(r1)
637 ; LARGE32-NEXT: stw r0, 40(r1)
638 ; LARGE32-NEXT: addis r3, L..C4@u(r2)
639 ; LARGE32-NEXT: lwz r4, L..C4@l(r3)
640 ; LARGE32-NEXT: bla .__get_tpointer[PR]
641 ; LARGE32-NEXT: add r4, r3, r4
642 ; LARGE32-NEXT: lwz r3, 0(r4)
643 ; LARGE32-NEXT: lwz r4, 4(r4)
644 ; LARGE32-NEXT: addi r1, r1, 32
645 ; LARGE32-NEXT: lwz r0, 8(r1)
646 ; LARGE32-NEXT: mtlr r0
647 ; LARGE32-NEXT: blr
648 ;
649 ; SMALL32-LABEL: load_global_long_zero:
650 ; SMALL32: # %bb.0: # %entry
651 ; SMALL32-NEXT: mflr r0
652 ; SMALL32-NEXT: stwu r1, -32(r1)
653 ; SMALL32-NEXT: lwz r4, L..C4(r2) # target-flags(ppc-tprel) @global_long_zero
654 ; SMALL32-NEXT: bla .__get_tpointer[PR]
655 ; SMALL32-NEXT: stw r0, 40(r1)
656 ; SMALL32-NEXT: add r4, r3, r4
657 ; SMALL32-NEXT: lwz r3, 0(r4)
658 ; SMALL32-NEXT: lwz r4, 4(r4)
659 ; SMALL32-NEXT: addi r1, r1, 32
660 ; SMALL32-NEXT: lwz r0, 8(r1)
661 ; SMALL32-NEXT: mtlr r0
662 ; SMALL32-NEXT: blr
663 entry:
664 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_long_zero)
665 %val = load i64, ptr %addr, align 8
666 ret i64 %val
667 }
669 define i64 @load_global_long_nonzero() {
670 ; LARGE64-LABEL: load_global_long_nonzero:
671 ; LARGE64: # %bb.0: # %entry
672 ; LARGE64-NEXT: addis r3, L..C5@u(r2)
673 ; LARGE64-NEXT: ld r3, L..C5@l(r3)
674 ; LARGE64-NEXT: ldx r3, r13, r3
675 ; LARGE64-NEXT: blr
676 ;
677 ; SMALL64-LABEL: load_global_long_nonzero:
678 ; SMALL64: # %bb.0: # %entry
679 ; SMALL64-NEXT: ld r3, L..C5(r2) # target-flags(ppc-tprel) @global_long_nonzero
680 ; SMALL64-NEXT: ldx r3, r13, r3
681 ; SMALL64-NEXT: blr
682 ;
683 ; LARGE32-LABEL: load_global_long_nonzero:
684 ; LARGE32: # %bb.0: # %entry
685 ; LARGE32-NEXT: mflr r0
686 ; LARGE32-NEXT: stwu r1, -32(r1)
687 ; LARGE32-NEXT: stw r0, 40(r1)
688 ; LARGE32-NEXT: addis r3, L..C5@u(r2)
689 ; LARGE32-NEXT: lwz r4, L..C5@l(r3)
690 ; LARGE32-NEXT: bla .__get_tpointer[PR]
691 ; LARGE32-NEXT: add r4, r3, r4
692 ; LARGE32-NEXT: lwz r3, 0(r4)
693 ; LARGE32-NEXT: lwz r4, 4(r4)
694 ; LARGE32-NEXT: addi r1, r1, 32
695 ; LARGE32-NEXT: lwz r0, 8(r1)
696 ; LARGE32-NEXT: mtlr r0
697 ; LARGE32-NEXT: blr
698 ;
699 ; SMALL32-LABEL: load_global_long_nonzero:
700 ; SMALL32: # %bb.0: # %entry
701 ; SMALL32-NEXT: mflr r0
702 ; SMALL32-NEXT: stwu r1, -32(r1)
703 ; SMALL32-NEXT: lwz r4, L..C5(r2) # target-flags(ppc-tprel) @global_long_nonzero
704 ; SMALL32-NEXT: bla .__get_tpointer[PR]
705 ; SMALL32-NEXT: stw r0, 40(r1)
706 ; SMALL32-NEXT: add r4, r3, r4
707 ; SMALL32-NEXT: lwz r3, 0(r4)
708 ; SMALL32-NEXT: lwz r4, 4(r4)
709 ; SMALL32-NEXT: addi r1, r1, 32
710 ; SMALL32-NEXT: lwz r0, 8(r1)
711 ; SMALL32-NEXT: mtlr r0
712 ; SMALL32-NEXT: blr
713 entry:
714 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_long_nonzero)
715 %val = load i64, ptr %addr, align 8
716 ret i64 %val
717 }
719 define i64 @load_intern_long_zero() {
720 ; LARGE64-LABEL: load_intern_long_zero:
721 ; LARGE64: # %bb.0: # %entry
722 ; LARGE64-NEXT: addis r3, L..C6@u(r2)
723 ; LARGE64-NEXT: ld r3, L..C6@l(r3)
724 ; LARGE64-NEXT: ldx r3, r13, r3
725 ; LARGE64-NEXT: blr
726 ;
727 ; SMALL64-LABEL: load_intern_long_zero:
728 ; SMALL64: # %bb.0: # %entry
729 ; SMALL64-NEXT: ld r3, L..C6(r2) # target-flags(ppc-tprel) @intern_long_zero
730 ; SMALL64-NEXT: ldx r3, r13, r3
731 ; SMALL64-NEXT: blr
732 ;
733 ; LARGE32-LABEL: load_intern_long_zero:
734 ; LARGE32: # %bb.0: # %entry
735 ; LARGE32-NEXT: mflr r0
736 ; LARGE32-NEXT: stwu r1, -32(r1)
737 ; LARGE32-NEXT: stw r0, 40(r1)
738 ; LARGE32-NEXT: addis r3, L..C6@u(r2)
739 ; LARGE32-NEXT: lwz r4, L..C6@l(r3)
740 ; LARGE32-NEXT: bla .__get_tpointer[PR]
741 ; LARGE32-NEXT: add r4, r3, r4
742 ; LARGE32-NEXT: lwz r3, 0(r4)
743 ; LARGE32-NEXT: lwz r4, 4(r4)
744 ; LARGE32-NEXT: addi r1, r1, 32
745 ; LARGE32-NEXT: lwz r0, 8(r1)
746 ; LARGE32-NEXT: mtlr r0
747 ; LARGE32-NEXT: blr
748 ;
749 ; SMALL32-LABEL: load_intern_long_zero:
750 ; SMALL32: # %bb.0: # %entry
751 ; SMALL32-NEXT: mflr r0
752 ; SMALL32-NEXT: stwu r1, -32(r1)
753 ; SMALL32-NEXT: lwz r4, L..C6(r2) # target-flags(ppc-tprel) @intern_long_zero
754 ; SMALL32-NEXT: bla .__get_tpointer[PR]
755 ; SMALL32-NEXT: stw r0, 40(r1)
756 ; SMALL32-NEXT: add r4, r3, r4
757 ; SMALL32-NEXT: lwz r3, 0(r4)
758 ; SMALL32-NEXT: lwz r4, 4(r4)
759 ; SMALL32-NEXT: addi r1, r1, 32
760 ; SMALL32-NEXT: lwz r0, 8(r1)
761 ; SMALL32-NEXT: mtlr r0
762 ; SMALL32-NEXT: blr
763 entry:
764 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_long_zero)
765 %val = load i64, ptr %addr, align 8
766 ret i64 %val
767 }
769 define i64 @load_intern_long_nonzero() {
770 ; LARGE64-LABEL: load_intern_long_nonzero:
771 ; LARGE64: # %bb.0: # %entry
772 ; LARGE64-NEXT: addis r3, L..C7@u(r2)
773 ; LARGE64-NEXT: ld r3, L..C7@l(r3)
774 ; LARGE64-NEXT: ldx r3, r13, r3
775 ; LARGE64-NEXT: blr
776 ;
777 ; SMALL64-LABEL: load_intern_long_nonzero:
778 ; SMALL64: # %bb.0: # %entry
779 ; SMALL64-NEXT: ld r3, L..C7(r2) # target-flags(ppc-tprel) @intern_long_nonzero
780 ; SMALL64-NEXT: ldx r3, r13, r3
781 ; SMALL64-NEXT: blr
782 ;
783 ; LARGE32-LABEL: load_intern_long_nonzero:
784 ; LARGE32: # %bb.0: # %entry
785 ; LARGE32-NEXT: mflr r0
786 ; LARGE32-NEXT: stwu r1, -32(r1)
787 ; LARGE32-NEXT: stw r0, 40(r1)
788 ; LARGE32-NEXT: addis r3, L..C7@u(r2)
789 ; LARGE32-NEXT: lwz r4, L..C7@l(r3)
790 ; LARGE32-NEXT: bla .__get_tpointer[PR]
791 ; LARGE32-NEXT: add r4, r3, r4
792 ; LARGE32-NEXT: lwz r3, 0(r4)
793 ; LARGE32-NEXT: lwz r4, 4(r4)
794 ; LARGE32-NEXT: addi r1, r1, 32
795 ; LARGE32-NEXT: lwz r0, 8(r1)
796 ; LARGE32-NEXT: mtlr r0
797 ; LARGE32-NEXT: blr
798 ;
799 ; SMALL32-LABEL: load_intern_long_nonzero:
800 ; SMALL32: # %bb.0: # %entry
801 ; SMALL32-NEXT: mflr r0
802 ; SMALL32-NEXT: stwu r1, -32(r1)
803 ; SMALL32-NEXT: lwz r4, L..C7(r2) # target-flags(ppc-tprel) @intern_long_nonzero
804 ; SMALL32-NEXT: bla .__get_tpointer[PR]
805 ; SMALL32-NEXT: stw r0, 40(r1)
806 ; SMALL32-NEXT: add r4, r3, r4
807 ; SMALL32-NEXT: lwz r3, 0(r4)
808 ; SMALL32-NEXT: lwz r4, 4(r4)
809 ; SMALL32-NEXT: addi r1, r1, 32
810 ; SMALL32-NEXT: lwz r0, 8(r1)
811 ; SMALL32-NEXT: mtlr r0
812 ; SMALL32-NEXT: blr
813 entry:
814 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_long_nonzero)
815 %val = load i64, ptr %addr, align 8
816 ret i64 %val
817 }
819 define void @store_global_float_zero(float noundef %i) {
820 ; LARGE64-LABEL: store_global_float_zero:
821 ; LARGE64: # %bb.0: # %entry
822 ; LARGE64-NEXT: addis r3, L..C8@u(r2)
823 ; LARGE64-NEXT: ld r3, L..C8@l(r3)
824 ; LARGE64-NEXT: stfsx f1, r13, r3
825 ; LARGE64-NEXT: blr
826 ;
827 ; SMALL64-LABEL: store_global_float_zero:
828 ; SMALL64: # %bb.0: # %entry
829 ; SMALL64-NEXT: ld r3, L..C8(r2) # target-flags(ppc-tprel) @global_float_zero
830 ; SMALL64-NEXT: stfsx f1, r13, r3
831 ; SMALL64-NEXT: blr
832 ;
833 ; LARGE32-LABEL: store_global_float_zero:
834 ; LARGE32: # %bb.0: # %entry
835 ; LARGE32-NEXT: mflr r0
836 ; LARGE32-NEXT: stwu r1, -32(r1)
837 ; LARGE32-NEXT: stw r0, 40(r1)
838 ; LARGE32-NEXT: addis r3, L..C8@u(r2)
839 ; LARGE32-NEXT: lwz r4, L..C8@l(r3)
840 ; LARGE32-NEXT: bla .__get_tpointer[PR]
841 ; LARGE32-NEXT: stfsx f1, r3, r4
842 ; LARGE32-NEXT: addi r1, r1, 32
843 ; LARGE32-NEXT: lwz r0, 8(r1)
844 ; LARGE32-NEXT: mtlr r0
845 ; LARGE32-NEXT: blr
846 ;
847 ; SMALL32-LABEL: store_global_float_zero:
848 ; SMALL32: # %bb.0: # %entry
849 ; SMALL32-NEXT: mflr r0
850 ; SMALL32-NEXT: stwu r1, -32(r1)
851 ; SMALL32-NEXT: lwz r4, L..C8(r2) # target-flags(ppc-tprel) @global_float_zero
852 ; SMALL32-NEXT: bla .__get_tpointer[PR]
853 ; SMALL32-NEXT: stw r0, 40(r1)
854 ; SMALL32-NEXT: stfsx f1, r3, r4
855 ; SMALL32-NEXT: addi r1, r1, 32
856 ; SMALL32-NEXT: lwz r0, 8(r1)
857 ; SMALL32-NEXT: mtlr r0
858 ; SMALL32-NEXT: blr
859 entry:
860 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_float_zero)
861 store float %i, ptr %addr, align 4
862 ret void
863 }
865 define void @store_global_float_nonzero(float noundef %i) {
866 ; LARGE64-LABEL: store_global_float_nonzero:
867 ; LARGE64: # %bb.0: # %entry
868 ; LARGE64-NEXT: addis r3, L..C9@u(r2)
869 ; LARGE64-NEXT: ld r3, L..C9@l(r3)
870 ; LARGE64-NEXT: stfsx f1, r13, r3
871 ; LARGE64-NEXT: blr
872 ;
873 ; SMALL64-LABEL: store_global_float_nonzero:
874 ; SMALL64: # %bb.0: # %entry
875 ; SMALL64-NEXT: ld r3, L..C9(r2) # target-flags(ppc-tprel) @global_float_nonzero
876 ; SMALL64-NEXT: stfsx f1, r13, r3
877 ; SMALL64-NEXT: blr
878 ;
879 ; LARGE32-LABEL: store_global_float_nonzero:
880 ; LARGE32: # %bb.0: # %entry
881 ; LARGE32-NEXT: mflr r0
882 ; LARGE32-NEXT: stwu r1, -32(r1)
883 ; LARGE32-NEXT: stw r0, 40(r1)
884 ; LARGE32-NEXT: addis r3, L..C9@u(r2)
885 ; LARGE32-NEXT: lwz r4, L..C9@l(r3)
886 ; LARGE32-NEXT: bla .__get_tpointer[PR]
887 ; LARGE32-NEXT: stfsx f1, r3, r4
888 ; LARGE32-NEXT: addi r1, r1, 32
889 ; LARGE32-NEXT: lwz r0, 8(r1)
890 ; LARGE32-NEXT: mtlr r0
891 ; LARGE32-NEXT: blr
892 ;
893 ; SMALL32-LABEL: store_global_float_nonzero:
894 ; SMALL32: # %bb.0: # %entry
895 ; SMALL32-NEXT: mflr r0
896 ; SMALL32-NEXT: stwu r1, -32(r1)
897 ; SMALL32-NEXT: lwz r4, L..C9(r2) # target-flags(ppc-tprel) @global_float_nonzero
898 ; SMALL32-NEXT: bla .__get_tpointer[PR]
899 ; SMALL32-NEXT: stw r0, 40(r1)
900 ; SMALL32-NEXT: stfsx f1, r3, r4
901 ; SMALL32-NEXT: addi r1, r1, 32
902 ; SMALL32-NEXT: lwz r0, 8(r1)
903 ; SMALL32-NEXT: mtlr r0
904 ; SMALL32-NEXT: blr
905 entry:
906 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_float_nonzero)
907 store float %i, ptr %addr, align 4
908 ret void
909 }
911 define void @store_intern_float_zero(float noundef %i) {
912 ; LARGE64-LABEL: store_intern_float_zero:
913 ; LARGE64: # %bb.0: # %entry
914 ; LARGE64-NEXT: addis r3, L..C10@u(r2)
915 ; LARGE64-NEXT: ld r3, L..C10@l(r3)
916 ; LARGE64-NEXT: stfsx f1, r13, r3
917 ; LARGE64-NEXT: blr
918 ;
919 ; SMALL64-LABEL: store_intern_float_zero:
920 ; SMALL64: # %bb.0: # %entry
921 ; SMALL64-NEXT: ld r3, L..C10(r2) # target-flags(ppc-tprel) @intern_float_zero
922 ; SMALL64-NEXT: stfsx f1, r13, r3
923 ; SMALL64-NEXT: blr
924 ;
925 ; LARGE32-LABEL: store_intern_float_zero:
926 ; LARGE32: # %bb.0: # %entry
927 ; LARGE32-NEXT: mflr r0
928 ; LARGE32-NEXT: stwu r1, -32(r1)
929 ; LARGE32-NEXT: stw r0, 40(r1)
930 ; LARGE32-NEXT: addis r3, L..C10@u(r2)
931 ; LARGE32-NEXT: lwz r4, L..C10@l(r3)
932 ; LARGE32-NEXT: bla .__get_tpointer[PR]
933 ; LARGE32-NEXT: stfsx f1, r3, r4
934 ; LARGE32-NEXT: addi r1, r1, 32
935 ; LARGE32-NEXT: lwz r0, 8(r1)
936 ; LARGE32-NEXT: mtlr r0
937 ; LARGE32-NEXT: blr
938 ;
939 ; SMALL32-LABEL: store_intern_float_zero:
940 ; SMALL32: # %bb.0: # %entry
941 ; SMALL32-NEXT: mflr r0
942 ; SMALL32-NEXT: stwu r1, -32(r1)
943 ; SMALL32-NEXT: lwz r4, L..C10(r2) # target-flags(ppc-tprel) @intern_float_zero
944 ; SMALL32-NEXT: bla .__get_tpointer[PR]
945 ; SMALL32-NEXT: stw r0, 40(r1)
946 ; SMALL32-NEXT: stfsx f1, r3, r4
947 ; SMALL32-NEXT: addi r1, r1, 32
948 ; SMALL32-NEXT: lwz r0, 8(r1)
949 ; SMALL32-NEXT: mtlr r0
950 ; SMALL32-NEXT: blr
951 entry:
952 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_float_zero)
953 store float %i, ptr %addr, align 4
954 ret void
955 }
957 define void @store_intern_float_nonzero(float noundef %i) {
958 ; LARGE64-LABEL: store_intern_float_nonzero:
959 ; LARGE64: # %bb.0: # %entry
960 ; LARGE64-NEXT: addis r3, L..C11@u(r2)
961 ; LARGE64-NEXT: ld r3, L..C11@l(r3)
962 ; LARGE64-NEXT: stfsx f1, r13, r3
963 ; LARGE64-NEXT: blr
964 ;
965 ; SMALL64-LABEL: store_intern_float_nonzero:
966 ; SMALL64: # %bb.0: # %entry
967 ; SMALL64-NEXT: ld r3, L..C11(r2) # target-flags(ppc-tprel) @intern_float_nonzero
968 ; SMALL64-NEXT: stfsx f1, r13, r3
969 ; SMALL64-NEXT: blr
970 ;
971 ; LARGE32-LABEL: store_intern_float_nonzero:
972 ; LARGE32: # %bb.0: # %entry
973 ; LARGE32-NEXT: mflr r0
974 ; LARGE32-NEXT: stwu r1, -32(r1)
975 ; LARGE32-NEXT: stw r0, 40(r1)
976 ; LARGE32-NEXT: addis r3, L..C11@u(r2)
977 ; LARGE32-NEXT: lwz r4, L..C11@l(r3)
978 ; LARGE32-NEXT: bla .__get_tpointer[PR]
979 ; LARGE32-NEXT: stfsx f1, r3, r4
980 ; LARGE32-NEXT: addi r1, r1, 32
981 ; LARGE32-NEXT: lwz r0, 8(r1)
982 ; LARGE32-NEXT: mtlr r0
983 ; LARGE32-NEXT: blr
984 ;
985 ; SMALL32-LABEL: store_intern_float_nonzero:
986 ; SMALL32: # %bb.0: # %entry
987 ; SMALL32-NEXT: mflr r0
988 ; SMALL32-NEXT: stwu r1, -32(r1)
989 ; SMALL32-NEXT: lwz r4, L..C11(r2) # target-flags(ppc-tprel) @intern_float_nonzero
990 ; SMALL32-NEXT: bla .__get_tpointer[PR]
991 ; SMALL32-NEXT: stw r0, 40(r1)
992 ; SMALL32-NEXT: stfsx f1, r3, r4
993 ; SMALL32-NEXT: addi r1, r1, 32
994 ; SMALL32-NEXT: lwz r0, 8(r1)
995 ; SMALL32-NEXT: mtlr r0
996 ; SMALL32-NEXT: blr
997 entry:
998 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_float_nonzero)
999 store float %i, ptr %addr, align 4
1000 ret void
1001 }
1003 define float @load_global_float_zero() {
1004 ; LARGE64-LABEL: load_global_float_zero:
1005 ; LARGE64: # %bb.0: # %entry
1006 ; LARGE64-NEXT: addis r3, L..C8@u(r2)
1007 ; LARGE64-NEXT: ld r3, L..C8@l(r3)
1008 ; LARGE64-NEXT: lfsx f1, r13, r3
1009 ; LARGE64-NEXT: blr
1010 ;
1011 ; SMALL64-LABEL: load_global_float_zero:
1012 ; SMALL64: # %bb.0: # %entry
1013 ; SMALL64-NEXT: ld r3, L..C8(r2) # target-flags(ppc-tprel) @global_float_zero
1014 ; SMALL64-NEXT: lfsx f1, r13, r3
1015 ; SMALL64-NEXT: blr
1016 ;
1017 ; LARGE32-LABEL: load_global_float_zero:
1018 ; LARGE32: # %bb.0: # %entry
1019 ; LARGE32-NEXT: mflr r0
1020 ; LARGE32-NEXT: stwu r1, -32(r1)
1021 ; LARGE32-NEXT: stw r0, 40(r1)
1022 ; LARGE32-NEXT: addis r3, L..C8@u(r2)
1023 ; LARGE32-NEXT: lwz r4, L..C8@l(r3)
1024 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1025 ; LARGE32-NEXT: lfsx f1, r3, r4
1026 ; LARGE32-NEXT: addi r1, r1, 32
1027 ; LARGE32-NEXT: lwz r0, 8(r1)
1028 ; LARGE32-NEXT: mtlr r0
1029 ; LARGE32-NEXT: blr
1030 ;
1031 ; SMALL32-LABEL: load_global_float_zero:
1032 ; SMALL32: # %bb.0: # %entry
1033 ; SMALL32-NEXT: mflr r0
1034 ; SMALL32-NEXT: stwu r1, -32(r1)
1035 ; SMALL32-NEXT: lwz r4, L..C8(r2) # target-flags(ppc-tprel) @global_float_zero
1036 ; SMALL32-NEXT: stw r0, 40(r1)
1037 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1038 ; SMALL32-NEXT: lfsx f1, r3, r4
1039 ; SMALL32-NEXT: addi r1, r1, 32
1040 ; SMALL32-NEXT: lwz r0, 8(r1)
1041 ; SMALL32-NEXT: mtlr r0
1042 ; SMALL32-NEXT: blr
1043 entry:
1044 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_float_zero)
1045 %val = load float, ptr %addr, align 4
1046 ret float %val
1047 }
1049 define float @load_global_float_nonzero() {
1050 ; LARGE64-LABEL: load_global_float_nonzero:
1051 ; LARGE64: # %bb.0: # %entry
1052 ; LARGE64-NEXT: addis r3, L..C9@u(r2)
1053 ; LARGE64-NEXT: ld r3, L..C9@l(r3)
1054 ; LARGE64-NEXT: lfsx f1, r13, r3
1055 ; LARGE64-NEXT: blr
1056 ;
1057 ; SMALL64-LABEL: load_global_float_nonzero:
1058 ; SMALL64: # %bb.0: # %entry
1059 ; SMALL64-NEXT: ld r3, L..C9(r2) # target-flags(ppc-tprel) @global_float_nonzero
1060 ; SMALL64-NEXT: lfsx f1, r13, r3
1061 ; SMALL64-NEXT: blr
1062 ;
1063 ; LARGE32-LABEL: load_global_float_nonzero:
1064 ; LARGE32: # %bb.0: # %entry
1065 ; LARGE32-NEXT: mflr r0
1066 ; LARGE32-NEXT: stwu r1, -32(r1)
1067 ; LARGE32-NEXT: stw r0, 40(r1)
1068 ; LARGE32-NEXT: addis r3, L..C9@u(r2)
1069 ; LARGE32-NEXT: lwz r4, L..C9@l(r3)
1070 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1071 ; LARGE32-NEXT: lfsx f1, r3, r4
1072 ; LARGE32-NEXT: addi r1, r1, 32
1073 ; LARGE32-NEXT: lwz r0, 8(r1)
1074 ; LARGE32-NEXT: mtlr r0
1075 ; LARGE32-NEXT: blr
1076 ;
1077 ; SMALL32-LABEL: load_global_float_nonzero:
1078 ; SMALL32: # %bb.0: # %entry
1079 ; SMALL32-NEXT: mflr r0
1080 ; SMALL32-NEXT: stwu r1, -32(r1)
1081 ; SMALL32-NEXT: lwz r4, L..C9(r2) # target-flags(ppc-tprel) @global_float_nonzero
1082 ; SMALL32-NEXT: stw r0, 40(r1)
1083 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1084 ; SMALL32-NEXT: lfsx f1, r3, r4
1085 ; SMALL32-NEXT: addi r1, r1, 32
1086 ; SMALL32-NEXT: lwz r0, 8(r1)
1087 ; SMALL32-NEXT: mtlr r0
1088 ; SMALL32-NEXT: blr
1089 entry:
1090 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @global_float_nonzero)
1091 %val = load float, ptr %addr, align 4
1092 ret float %val
1093 }
1095 define float @load_intern_float_zero() {
1096 ; LARGE64-LABEL: load_intern_float_zero:
1097 ; LARGE64: # %bb.0: # %entry
1098 ; LARGE64-NEXT: addis r3, L..C10@u(r2)
1099 ; LARGE64-NEXT: ld r3, L..C10@l(r3)
1100 ; LARGE64-NEXT: lfsx f1, r13, r3
1101 ; LARGE64-NEXT: blr
1102 ;
1103 ; SMALL64-LABEL: load_intern_float_zero:
1104 ; SMALL64: # %bb.0: # %entry
1105 ; SMALL64-NEXT: ld r3, L..C10(r2) # target-flags(ppc-tprel) @intern_float_zero
1106 ; SMALL64-NEXT: lfsx f1, r13, r3
1107 ; SMALL64-NEXT: blr
1108 ;
1109 ; LARGE32-LABEL: load_intern_float_zero:
1110 ; LARGE32: # %bb.0: # %entry
1111 ; LARGE32-NEXT: mflr r0
1112 ; LARGE32-NEXT: stwu r1, -32(r1)
1113 ; LARGE32-NEXT: stw r0, 40(r1)
1114 ; LARGE32-NEXT: addis r3, L..C10@u(r2)
1115 ; LARGE32-NEXT: lwz r4, L..C10@l(r3)
1116 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1117 ; LARGE32-NEXT: lfsx f1, r3, r4
1118 ; LARGE32-NEXT: addi r1, r1, 32
1119 ; LARGE32-NEXT: lwz r0, 8(r1)
1120 ; LARGE32-NEXT: mtlr r0
1121 ; LARGE32-NEXT: blr
1122 ;
1123 ; SMALL32-LABEL: load_intern_float_zero:
1124 ; SMALL32: # %bb.0: # %entry
1125 ; SMALL32-NEXT: mflr r0
1126 ; SMALL32-NEXT: stwu r1, -32(r1)
1127 ; SMALL32-NEXT: lwz r4, L..C10(r2) # target-flags(ppc-tprel) @intern_float_zero
1128 ; SMALL32-NEXT: stw r0, 40(r1)
1129 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1130 ; SMALL32-NEXT: lfsx f1, r3, r4
1131 ; SMALL32-NEXT: addi r1, r1, 32
1132 ; SMALL32-NEXT: lwz r0, 8(r1)
1133 ; SMALL32-NEXT: mtlr r0
1134 ; SMALL32-NEXT: blr
1135 entry:
1136 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_float_zero)
1137 %val = load float, ptr %addr, align 4
1138 ret float %val
1139 }
1141 define float @load_intern_float_nonzero() {
1142 ; LARGE64-LABEL: load_intern_float_nonzero:
1143 ; LARGE64: # %bb.0: # %entry
1144 ; LARGE64-NEXT: addis r3, L..C11@u(r2)
1145 ; LARGE64-NEXT: ld r3, L..C11@l(r3)
1146 ; LARGE64-NEXT: lfsx f1, r13, r3
1147 ; LARGE64-NEXT: blr
1148 ;
1149 ; SMALL64-LABEL: load_intern_float_nonzero:
1150 ; SMALL64: # %bb.0: # %entry
1151 ; SMALL64-NEXT: ld r3, L..C11(r2) # target-flags(ppc-tprel) @intern_float_nonzero
1152 ; SMALL64-NEXT: lfsx f1, r13, r3
1153 ; SMALL64-NEXT: blr
1154 ;
1155 ; LARGE32-LABEL: load_intern_float_nonzero:
1156 ; LARGE32: # %bb.0: # %entry
1157 ; LARGE32-NEXT: mflr r0
1158 ; LARGE32-NEXT: stwu r1, -32(r1)
1159 ; LARGE32-NEXT: stw r0, 40(r1)
1160 ; LARGE32-NEXT: addis r3, L..C11@u(r2)
1161 ; LARGE32-NEXT: lwz r4, L..C11@l(r3)
1162 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1163 ; LARGE32-NEXT: lfsx f1, r3, r4
1164 ; LARGE32-NEXT: addi r1, r1, 32
1165 ; LARGE32-NEXT: lwz r0, 8(r1)
1166 ; LARGE32-NEXT: mtlr r0
1167 ; LARGE32-NEXT: blr
1168 ;
1169 ; SMALL32-LABEL: load_intern_float_nonzero:
1170 ; SMALL32: # %bb.0: # %entry
1171 ; SMALL32-NEXT: mflr r0
1172 ; SMALL32-NEXT: stwu r1, -32(r1)
1173 ; SMALL32-NEXT: lwz r4, L..C11(r2) # target-flags(ppc-tprel) @intern_float_nonzero
1174 ; SMALL32-NEXT: stw r0, 40(r1)
1175 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1176 ; SMALL32-NEXT: lfsx f1, r3, r4
1177 ; SMALL32-NEXT: addi r1, r1, 32
1178 ; SMALL32-NEXT: lwz r0, 8(r1)
1179 ; SMALL32-NEXT: mtlr r0
1180 ; SMALL32-NEXT: blr
1181 entry:
1182 %addr = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @intern_float_nonzero)
1183 %val = load float, ptr %addr, align 4
1184 ret float %val
1185 }
1187 define void @store_global_double_zero(double noundef %i) {
1188 ; LARGE64-LABEL: store_global_double_zero:
1189 ; LARGE64: # %bb.0: # %entry
1190 ; LARGE64-NEXT: addis r3, L..C12@u(r2)
1191 ; LARGE64-NEXT: ld r3, L..C12@l(r3)
1192 ; LARGE64-NEXT: stfdx f1, r13, r3
1193 ; LARGE64-NEXT: blr
1194 ;
1195 ; SMALL64-LABEL: store_global_double_zero:
1196 ; SMALL64: # %bb.0: # %entry
1197 ; SMALL64-NEXT: ld r3, L..C12(r2) # target-flags(ppc-tprel) @global_double_zero
1198 ; SMALL64-NEXT: stfdx f1, r13, r3
1199 ; SMALL64-NEXT: blr
1200 ;
1201 ; LARGE32-LABEL: store_global_double_zero:
1202 ; LARGE32: # %bb.0: # %entry
1203 ; LARGE32-NEXT: mflr r0
1204 ; LARGE32-NEXT: stwu r1, -32(r1)
1205 ; LARGE32-NEXT: stw r0, 40(r1)
1206 ; LARGE32-NEXT: addis r3, L..C12@u(r2)
1207 ; LARGE32-NEXT: lwz r4, L..C12@l(r3)
1208 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1209 ; LARGE32-NEXT: stfdx f1, r3, r4
1210 ; LARGE32-NEXT: addi r1, r1, 32
1211 ; LARGE32-NEXT: lwz r0, 8(r1)
1212 ; LARGE32-NEXT: mtlr r0
1213 ; LARGE32-NEXT: blr
1214 ;
1215 ; SMALL32-LABEL: store_global_double_zero:
1216 ; SMALL32: # %bb.0: # %entry
1217 ; SMALL32-NEXT: mflr r0
1218 ; SMALL32-NEXT: stwu r1, -32(r1)
1219 ; SMALL32-NEXT: lwz r4, L..C12(r2) # target-flags(ppc-tprel) @global_double_zero
1220 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1221 ; SMALL32-NEXT: stw r0, 40(r1)
1222 ; SMALL32-NEXT: stfdx f1, r3, r4
1223 ; SMALL32-NEXT: addi r1, r1, 32
1224 ; SMALL32-NEXT: lwz r0, 8(r1)
1225 ; SMALL32-NEXT: mtlr r0
1226 ; SMALL32-NEXT: blr
1227 entry:
1228 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_double_zero)
1229 store double %i, ptr %addr, align 8
1230 ret void
1231 }
1233 define void @store_global_double_nonzero(double noundef %i) {
1234 ; LARGE64-LABEL: store_global_double_nonzero:
1235 ; LARGE64: # %bb.0: # %entry
1236 ; LARGE64-NEXT: addis r3, L..C13@u(r2)
1237 ; LARGE64-NEXT: ld r3, L..C13@l(r3)
1238 ; LARGE64-NEXT: stfdx f1, r13, r3
1239 ; LARGE64-NEXT: blr
1240 ;
1241 ; SMALL64-LABEL: store_global_double_nonzero:
1242 ; SMALL64: # %bb.0: # %entry
1243 ; SMALL64-NEXT: ld r3, L..C13(r2) # target-flags(ppc-tprel) @global_double_nonzero
1244 ; SMALL64-NEXT: stfdx f1, r13, r3
1245 ; SMALL64-NEXT: blr
1246 ;
1247 ; LARGE32-LABEL: store_global_double_nonzero:
1248 ; LARGE32: # %bb.0: # %entry
1249 ; LARGE32-NEXT: mflr r0
1250 ; LARGE32-NEXT: stwu r1, -32(r1)
1251 ; LARGE32-NEXT: stw r0, 40(r1)
1252 ; LARGE32-NEXT: addis r3, L..C13@u(r2)
1253 ; LARGE32-NEXT: lwz r4, L..C13@l(r3)
1254 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1255 ; LARGE32-NEXT: stfdx f1, r3, r4
1256 ; LARGE32-NEXT: addi r1, r1, 32
1257 ; LARGE32-NEXT: lwz r0, 8(r1)
1258 ; LARGE32-NEXT: mtlr r0
1259 ; LARGE32-NEXT: blr
1260 ;
1261 ; SMALL32-LABEL: store_global_double_nonzero:
1262 ; SMALL32: # %bb.0: # %entry
1263 ; SMALL32-NEXT: mflr r0
1264 ; SMALL32-NEXT: stwu r1, -32(r1)
1265 ; SMALL32-NEXT: lwz r4, L..C13(r2) # target-flags(ppc-tprel) @global_double_nonzero
1266 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1267 ; SMALL32-NEXT: stw r0, 40(r1)
1268 ; SMALL32-NEXT: stfdx f1, r3, r4
1269 ; SMALL32-NEXT: addi r1, r1, 32
1270 ; SMALL32-NEXT: lwz r0, 8(r1)
1271 ; SMALL32-NEXT: mtlr r0
1272 ; SMALL32-NEXT: blr
1273 entry:
1274 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_double_nonzero)
1275 store double %i, ptr %addr, align 8
1276 ret void
1277 }
1279 define void @store_intern_double_zero(double noundef %i) {
1280 ; LARGE64-LABEL: store_intern_double_zero:
1281 ; LARGE64: # %bb.0: # %entry
1282 ; LARGE64-NEXT: addis r3, L..C14@u(r2)
1283 ; LARGE64-NEXT: ld r3, L..C14@l(r3)
1284 ; LARGE64-NEXT: stfdx f1, r13, r3
1285 ; LARGE64-NEXT: blr
1286 ;
1287 ; SMALL64-LABEL: store_intern_double_zero:
1288 ; SMALL64: # %bb.0: # %entry
1289 ; SMALL64-NEXT: ld r3, L..C14(r2) # target-flags(ppc-tprel) @intern_double_zero
1290 ; SMALL64-NEXT: stfdx f1, r13, r3
1291 ; SMALL64-NEXT: blr
1292 ;
1293 ; LARGE32-LABEL: store_intern_double_zero:
1294 ; LARGE32: # %bb.0: # %entry
1295 ; LARGE32-NEXT: mflr r0
1296 ; LARGE32-NEXT: stwu r1, -32(r1)
1297 ; LARGE32-NEXT: stw r0, 40(r1)
1298 ; LARGE32-NEXT: addis r3, L..C14@u(r2)
1299 ; LARGE32-NEXT: lwz r4, L..C14@l(r3)
1300 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1301 ; LARGE32-NEXT: stfdx f1, r3, r4
1302 ; LARGE32-NEXT: addi r1, r1, 32
1303 ; LARGE32-NEXT: lwz r0, 8(r1)
1304 ; LARGE32-NEXT: mtlr r0
1305 ; LARGE32-NEXT: blr
1306 ;
1307 ; SMALL32-LABEL: store_intern_double_zero:
1308 ; SMALL32: # %bb.0: # %entry
1309 ; SMALL32-NEXT: mflr r0
1310 ; SMALL32-NEXT: stwu r1, -32(r1)
1311 ; SMALL32-NEXT: lwz r4, L..C14(r2) # target-flags(ppc-tprel) @intern_double_zero
1312 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1313 ; SMALL32-NEXT: stw r0, 40(r1)
1314 ; SMALL32-NEXT: stfdx f1, r3, r4
1315 ; SMALL32-NEXT: addi r1, r1, 32
1316 ; SMALL32-NEXT: lwz r0, 8(r1)
1317 ; SMALL32-NEXT: mtlr r0
1318 ; SMALL32-NEXT: blr
1319 entry:
1320 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_double_zero)
1321 store double %i, ptr %addr, align 8
1322 ret void
1323 }
1325 define void @store_intern_double_nonzero(double noundef %i) {
1326 ; LARGE64-LABEL: store_intern_double_nonzero:
1327 ; LARGE64: # %bb.0: # %entry
1328 ; LARGE64-NEXT: addis r3, L..C15@u(r2)
1329 ; LARGE64-NEXT: ld r3, L..C15@l(r3)
1330 ; LARGE64-NEXT: stfdx f1, r13, r3
1331 ; LARGE64-NEXT: blr
1332 ;
1333 ; SMALL64-LABEL: store_intern_double_nonzero:
1334 ; SMALL64: # %bb.0: # %entry
1335 ; SMALL64-NEXT: ld r3, L..C15(r2) # target-flags(ppc-tprel) @intern_double_nonzero
1336 ; SMALL64-NEXT: stfdx f1, r13, r3
1337 ; SMALL64-NEXT: blr
1338 ;
1339 ; LARGE32-LABEL: store_intern_double_nonzero:
1340 ; LARGE32: # %bb.0: # %entry
1341 ; LARGE32-NEXT: mflr r0
1342 ; LARGE32-NEXT: stwu r1, -32(r1)
1343 ; LARGE32-NEXT: stw r0, 40(r1)
1344 ; LARGE32-NEXT: addis r3, L..C15@u(r2)
1345 ; LARGE32-NEXT: lwz r4, L..C15@l(r3)
1346 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1347 ; LARGE32-NEXT: stfdx f1, r3, r4
1348 ; LARGE32-NEXT: addi r1, r1, 32
1349 ; LARGE32-NEXT: lwz r0, 8(r1)
1350 ; LARGE32-NEXT: mtlr r0
1351 ; LARGE32-NEXT: blr
1352 ;
1353 ; SMALL32-LABEL: store_intern_double_nonzero:
1354 ; SMALL32: # %bb.0: # %entry
1355 ; SMALL32-NEXT: mflr r0
1356 ; SMALL32-NEXT: stwu r1, -32(r1)
1357 ; SMALL32-NEXT: lwz r4, L..C15(r2) # target-flags(ppc-tprel) @intern_double_nonzero
1358 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1359 ; SMALL32-NEXT: stw r0, 40(r1)
1360 ; SMALL32-NEXT: stfdx f1, r3, r4
1361 ; SMALL32-NEXT: addi r1, r1, 32
1362 ; SMALL32-NEXT: lwz r0, 8(r1)
1363 ; SMALL32-NEXT: mtlr r0
1364 ; SMALL32-NEXT: blr
1365 entry:
1366 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_double_nonzero)
1367 store double %i, ptr %addr, align 8
1368 ret void
1369 }
1371 define double @load_global_double_zero() {
1372 ; LARGE64-LABEL: load_global_double_zero:
1373 ; LARGE64: # %bb.0: # %entry
1374 ; LARGE64-NEXT: addis r3, L..C12@u(r2)
1375 ; LARGE64-NEXT: ld r3, L..C12@l(r3)
1376 ; LARGE64-NEXT: lfdx f1, r13, r3
1377 ; LARGE64-NEXT: blr
1378 ;
1379 ; SMALL64-LABEL: load_global_double_zero:
1380 ; SMALL64: # %bb.0: # %entry
1381 ; SMALL64-NEXT: ld r3, L..C12(r2) # target-flags(ppc-tprel) @global_double_zero
1382 ; SMALL64-NEXT: lfdx f1, r13, r3
1383 ; SMALL64-NEXT: blr
1384 ;
1385 ; LARGE32-LABEL: load_global_double_zero:
1386 ; LARGE32: # %bb.0: # %entry
1387 ; LARGE32-NEXT: mflr r0
1388 ; LARGE32-NEXT: stwu r1, -32(r1)
1389 ; LARGE32-NEXT: stw r0, 40(r1)
1390 ; LARGE32-NEXT: addis r3, L..C12@u(r2)
1391 ; LARGE32-NEXT: lwz r4, L..C12@l(r3)
1392 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1393 ; LARGE32-NEXT: lfdx f1, r3, r4
1394 ; LARGE32-NEXT: addi r1, r1, 32
1395 ; LARGE32-NEXT: lwz r0, 8(r1)
1396 ; LARGE32-NEXT: mtlr r0
1397 ; LARGE32-NEXT: blr
1398 ;
1399 ; SMALL32-LABEL: load_global_double_zero:
1400 ; SMALL32: # %bb.0: # %entry
1401 ; SMALL32-NEXT: mflr r0
1402 ; SMALL32-NEXT: stwu r1, -32(r1)
1403 ; SMALL32-NEXT: lwz r4, L..C12(r2) # target-flags(ppc-tprel) @global_double_zero
1404 ; SMALL32-NEXT: stw r0, 40(r1)
1405 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1406 ; SMALL32-NEXT: lfdx f1, r3, r4
1407 ; SMALL32-NEXT: addi r1, r1, 32
1408 ; SMALL32-NEXT: lwz r0, 8(r1)
1409 ; SMALL32-NEXT: mtlr r0
1410 ; SMALL32-NEXT: blr
1411 entry:
1412 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_double_zero)
1413 %val = load double, ptr %addr, align 8
1414 ret double %val
1415 }
1417 define double @load_global_double_nonzero() {
1418 ; LARGE64-LABEL: load_global_double_nonzero:
1419 ; LARGE64: # %bb.0: # %entry
1420 ; LARGE64-NEXT: addis r3, L..C13@u(r2)
1421 ; LARGE64-NEXT: ld r3, L..C13@l(r3)
1422 ; LARGE64-NEXT: lfdx f1, r13, r3
1423 ; LARGE64-NEXT: blr
1424 ;
1425 ; SMALL64-LABEL: load_global_double_nonzero:
1426 ; SMALL64: # %bb.0: # %entry
1427 ; SMALL64-NEXT: ld r3, L..C13(r2) # target-flags(ppc-tprel) @global_double_nonzero
1428 ; SMALL64-NEXT: lfdx f1, r13, r3
1429 ; SMALL64-NEXT: blr
1430 ;
1431 ; LARGE32-LABEL: load_global_double_nonzero:
1432 ; LARGE32: # %bb.0: # %entry
1433 ; LARGE32-NEXT: mflr r0
1434 ; LARGE32-NEXT: stwu r1, -32(r1)
1435 ; LARGE32-NEXT: stw r0, 40(r1)
1436 ; LARGE32-NEXT: addis r3, L..C13@u(r2)
1437 ; LARGE32-NEXT: lwz r4, L..C13@l(r3)
1438 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1439 ; LARGE32-NEXT: lfdx f1, r3, r4
1440 ; LARGE32-NEXT: addi r1, r1, 32
1441 ; LARGE32-NEXT: lwz r0, 8(r1)
1442 ; LARGE32-NEXT: mtlr r0
1443 ; LARGE32-NEXT: blr
1444 ;
1445 ; SMALL32-LABEL: load_global_double_nonzero:
1446 ; SMALL32: # %bb.0: # %entry
1447 ; SMALL32-NEXT: mflr r0
1448 ; SMALL32-NEXT: stwu r1, -32(r1)
1449 ; SMALL32-NEXT: lwz r4, L..C13(r2) # target-flags(ppc-tprel) @global_double_nonzero
1450 ; SMALL32-NEXT: stw r0, 40(r1)
1451 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1452 ; SMALL32-NEXT: lfdx f1, r3, r4
1453 ; SMALL32-NEXT: addi r1, r1, 32
1454 ; SMALL32-NEXT: lwz r0, 8(r1)
1455 ; SMALL32-NEXT: mtlr r0
1456 ; SMALL32-NEXT: blr
1457 entry:
1458 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @global_double_nonzero)
1459 %val = load double, ptr %addr, align 8
1460 ret double %val
1461 }
1463 define double @load_intern_double_zero() {
1464 ; LARGE64-LABEL: load_intern_double_zero:
1465 ; LARGE64: # %bb.0: # %entry
1466 ; LARGE64-NEXT: addis r3, L..C14@u(r2)
1467 ; LARGE64-NEXT: ld r3, L..C14@l(r3)
1468 ; LARGE64-NEXT: lfdx f1, r13, r3
1469 ; LARGE64-NEXT: blr
1470 ;
1471 ; SMALL64-LABEL: load_intern_double_zero:
1472 ; SMALL64: # %bb.0: # %entry
1473 ; SMALL64-NEXT: ld r3, L..C14(r2) # target-flags(ppc-tprel) @intern_double_zero
1474 ; SMALL64-NEXT: lfdx f1, r13, r3
1475 ; SMALL64-NEXT: blr
1476 ;
1477 ; LARGE32-LABEL: load_intern_double_zero:
1478 ; LARGE32: # %bb.0: # %entry
1479 ; LARGE32-NEXT: mflr r0
1480 ; LARGE32-NEXT: stwu r1, -32(r1)
1481 ; LARGE32-NEXT: stw r0, 40(r1)
1482 ; LARGE32-NEXT: addis r3, L..C14@u(r2)
1483 ; LARGE32-NEXT: lwz r4, L..C14@l(r3)
1484 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1485 ; LARGE32-NEXT: lfdx f1, r3, r4
1486 ; LARGE32-NEXT: addi r1, r1, 32
1487 ; LARGE32-NEXT: lwz r0, 8(r1)
1488 ; LARGE32-NEXT: mtlr r0
1489 ; LARGE32-NEXT: blr
1490 ;
1491 ; SMALL32-LABEL: load_intern_double_zero:
1492 ; SMALL32: # %bb.0: # %entry
1493 ; SMALL32-NEXT: mflr r0
1494 ; SMALL32-NEXT: stwu r1, -32(r1)
1495 ; SMALL32-NEXT: lwz r4, L..C14(r2) # target-flags(ppc-tprel) @intern_double_zero
1496 ; SMALL32-NEXT: stw r0, 40(r1)
1497 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1498 ; SMALL32-NEXT: lfdx f1, r3, r4
1499 ; SMALL32-NEXT: addi r1, r1, 32
1500 ; SMALL32-NEXT: lwz r0, 8(r1)
1501 ; SMALL32-NEXT: mtlr r0
1502 ; SMALL32-NEXT: blr
1503 entry:
1504 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_double_zero)
1505 %val = load double, ptr %addr, align 8
1506 ret double %val
1507 }
1509 define double @load_intern_double_nonzero() {
1510 ; LARGE64-LABEL: load_intern_double_nonzero:
1511 ; LARGE64: # %bb.0: # %entry
1512 ; LARGE64-NEXT: addis r3, L..C15@u(r2)
1513 ; LARGE64-NEXT: ld r3, L..C15@l(r3)
1514 ; LARGE64-NEXT: lfdx f1, r13, r3
1515 ; LARGE64-NEXT: blr
1516 ;
1517 ; SMALL64-LABEL: load_intern_double_nonzero:
1518 ; SMALL64: # %bb.0: # %entry
1519 ; SMALL64-NEXT: ld r3, L..C15(r2) # target-flags(ppc-tprel) @intern_double_nonzero
1520 ; SMALL64-NEXT: lfdx f1, r13, r3
1521 ; SMALL64-NEXT: blr
1522 ;
1523 ; LARGE32-LABEL: load_intern_double_nonzero:
1524 ; LARGE32: # %bb.0: # %entry
1525 ; LARGE32-NEXT: mflr r0
1526 ; LARGE32-NEXT: stwu r1, -32(r1)
1527 ; LARGE32-NEXT: stw r0, 40(r1)
1528 ; LARGE32-NEXT: addis r3, L..C15@u(r2)
1529 ; LARGE32-NEXT: lwz r4, L..C15@l(r3)
1530 ; LARGE32-NEXT: bla .__get_tpointer[PR]
1531 ; LARGE32-NEXT: lfdx f1, r3, r4
1532 ; LARGE32-NEXT: addi r1, r1, 32
1533 ; LARGE32-NEXT: lwz r0, 8(r1)
1534 ; LARGE32-NEXT: mtlr r0
1535 ; LARGE32-NEXT: blr
1536 ;
1537 ; SMALL32-LABEL: load_intern_double_nonzero:
1538 ; SMALL32: # %bb.0: # %entry
1539 ; SMALL32-NEXT: mflr r0
1540 ; SMALL32-NEXT: stwu r1, -32(r1)
1541 ; SMALL32-NEXT: lwz r4, L..C15(r2) # target-flags(ppc-tprel) @intern_double_nonzero
1542 ; SMALL32-NEXT: stw r0, 40(r1)
1543 ; SMALL32-NEXT: bla .__get_tpointer[PR]
1544 ; SMALL32-NEXT: lfdx f1, r3, r4
1545 ; SMALL32-NEXT: addi r1, r1, 32
1546 ; SMALL32-NEXT: lwz r0, 8(r1)
1547 ; SMALL32-NEXT: mtlr r0
1548 ; SMALL32-NEXT: blr
1549 entry:
1550 %addr = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @intern_double_nonzero)
1551 %val = load double, ptr %addr, align 8
1552 ret double %val
1553 }
1555 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
1557 ; Lines below check if the symbols have correct suffix for TLS model, not
1558 ; generated by test update script, but kept well after updates.
1560 ; LARGE64: L..C0:
1561 ; LARGE64-NEXT: .tc global_int_zero[TE],global_int_zero[TL]@ie
1562 ; LARGE64-NEXT: L..C1:
1563 ; LARGE64-NEXT: .tc global_int_nonzero[TE],global_int_nonzero[TL]@ie
1564 ; LARGE64-NEXT: L..C2:
1565 ; LARGE64-NEXT: .tc intern_int_zero[TE],intern_int_zero[UL]@ie
1566 ; LARGE64-NEXT: L..C3:
1567 ; LARGE64-NEXT: .tc intern_int_nonzero[TE],intern_int_nonzero[TL]@ie
1568 ; LARGE64-NEXT: L..C4:
1569 ; LARGE64-NEXT: .tc global_long_zero[TE],global_long_zero[TL]@ie
1570 ; LARGE64-NEXT: L..C5:
1571 ; LARGE64-NEXT: .tc global_long_nonzero[TE],global_long_nonzero[TL]@ie
1572 ; LARGE64-NEXT: L..C6:
1573 ; LARGE64-NEXT: .tc intern_long_zero[TE],intern_long_zero[UL]@ie
1574 ; LARGE64-NEXT: L..C7:
1575 ; LARGE64-NEXT: .tc intern_long_nonzero[TE],intern_long_nonzero[TL]@ie
1576 ; LARGE64-NEXT: L..C8:
1577 ; LARGE64-NEXT: .tc global_float_zero[TE],global_float_zero[TL]@ie
1578 ; LARGE64-NEXT: L..C9:
1579 ; LARGE64-NEXT: .tc global_float_nonzero[TE],global_float_nonzero[TL]@ie
1580 ; LARGE64-NEXT: L..C10:
1581 ; LARGE64-NEXT: .tc intern_float_zero[TE],intern_float_zero[UL]@ie
1582 ; LARGE64-NEXT: L..C11:
1583 ; LARGE64-NEXT: .tc intern_float_nonzero[TE],intern_float_nonzero[TL]@ie
1584 ; LARGE64-NEXT: L..C12:
1585 ; LARGE64-NEXT: .tc global_double_zero[TE],global_double_zero[TL]@ie
1586 ; LARGE64-NEXT: L..C13:
1587 ; LARGE64-NEXT: .tc global_double_nonzero[TE],global_double_nonzero[TL]@ie
1588 ; LARGE64-NEXT: L..C14:
1589 ; LARGE64-NEXT: .tc intern_double_zero[TE],intern_double_zero[UL]@ie
1590 ; LARGE64-NEXT: L..C15:
1591 ; LARGE64-NEXT: .tc intern_double_nonzero[TE],intern_double_nonzero[TL]@ie
1593 ; SMALL64: L..C0:
1594 ; SMALL64-NEXT: .tc global_int_zero[TC],global_int_zero[TL]@ie
1595 ; SMALL64-NEXT: L..C1:
1596 ; SMALL64-NEXT: .tc global_int_nonzero[TC],global_int_nonzero[TL]@ie
1597 ; SMALL64-NEXT: L..C2:
1598 ; SMALL64-NEXT: .tc intern_int_zero[TC],intern_int_zero[UL]@ie
1599 ; SMALL64-NEXT: L..C3:
1600 ; SMALL64-NEXT: .tc intern_int_nonzero[TC],intern_int_nonzero[TL]@ie
1601 ; SMALL64-NEXT: L..C4:
1602 ; SMALL64-NEXT: .tc global_long_zero[TC],global_long_zero[TL]@ie
1603 ; SMALL64-NEXT: L..C5:
1604 ; SMALL64-NEXT: .tc global_long_nonzero[TC],global_long_nonzero[TL]@ie
1605 ; SMALL64-NEXT: L..C6:
1606 ; SMALL64-NEXT: .tc intern_long_zero[TC],intern_long_zero[UL]@ie
1607 ; SMALL64-NEXT: L..C7:
1608 ; SMALL64-NEXT: .tc intern_long_nonzero[TC],intern_long_nonzero[TL]@ie
1609 ; SMALL64-NEXT: L..C8:
1610 ; SMALL64-NEXT: .tc global_float_zero[TC],global_float_zero[TL]@ie
1611 ; SMALL64-NEXT: L..C9:
1612 ; SMALL64-NEXT: .tc global_float_nonzero[TC],global_float_nonzero[TL]@ie
1613 ; SMALL64-NEXT: L..C10:
1614 ; SMALL64-NEXT: .tc intern_float_zero[TC],intern_float_zero[UL]@ie
1615 ; SMALL64-NEXT: L..C11:
1616 ; SMALL64-NEXT: .tc intern_float_nonzero[TC],intern_float_nonzero[TL]@ie
1617 ; SMALL64-NEXT: L..C12:
1618 ; SMALL64-NEXT: .tc global_double_zero[TC],global_double_zero[TL]@ie
1619 ; SMALL64-NEXT: L..C13:
1620 ; SMALL64-NEXT: .tc global_double_nonzero[TC],global_double_nonzero[TL]@ie
1621 ; SMALL64-NEXT: L..C14:
1622 ; SMALL64-NEXT: .tc intern_double_zero[TC],intern_double_zero[UL]@ie
1623 ; SMALL64-NEXT: L..C15:
1624 ; SMALL64-NEXT: .tc intern_double_nonzero[TC],intern_double_nonzero[TL]@ie
1626 ; LARGE32: L..C0:
1627 ; LARGE32-NEXT: .tc global_int_zero[TE],global_int_zero[TL]@ie
1628 ; LARGE32-NEXT: L..C1:
1629 ; LARGE32-NEXT: .tc global_int_nonzero[TE],global_int_nonzero[TL]@ie
1630 ; LARGE32-NEXT: L..C2:
1631 ; LARGE32-NEXT: .tc intern_int_zero[TE],intern_int_zero[UL]@ie
1632 ; LARGE32-NEXT: L..C3:
1633 ; LARGE32-NEXT: .tc intern_int_nonzero[TE],intern_int_nonzero[TL]@ie
1634 ; LARGE32-NEXT: L..C4:
1635 ; LARGE32-NEXT: .tc global_long_zero[TE],global_long_zero[TL]@ie
1636 ; LARGE32-NEXT: L..C5:
1637 ; LARGE32-NEXT: .tc global_long_nonzero[TE],global_long_nonzero[TL]@ie
1638 ; LARGE32-NEXT: L..C6:
1639 ; LARGE32-NEXT: .tc intern_long_zero[TE],intern_long_zero[UL]@ie
1640 ; LARGE32-NEXT: L..C7:
1641 ; LARGE32-NEXT: .tc intern_long_nonzero[TE],intern_long_nonzero[TL]@ie
1642 ; LARGE32-NEXT: L..C8:
1643 ; LARGE32-NEXT: .tc global_float_zero[TE],global_float_zero[TL]@ie
1644 ; LARGE32-NEXT: L..C9:
1645 ; LARGE32-NEXT: .tc global_float_nonzero[TE],global_float_nonzero[TL]@ie
1646 ; LARGE32-NEXT: L..C10:
1647 ; LARGE32-NEXT: .tc intern_float_zero[TE],intern_float_zero[UL]@ie
1648 ; LARGE32-NEXT: L..C11:
1649 ; LARGE32-NEXT: .tc intern_float_nonzero[TE],intern_float_nonzero[TL]@ie
1650 ; LARGE32-NEXT: L..C12:
1651 ; LARGE32-NEXT: .tc global_double_zero[TE],global_double_zero[TL]@ie
1652 ; LARGE32-NEXT: L..C13:
1653 ; LARGE32-NEXT: .tc global_double_nonzero[TE],global_double_nonzero[TL]@ie
1654 ; LARGE32-NEXT: L..C14:
1655 ; LARGE32-NEXT: .tc intern_double_zero[TE],intern_double_zero[UL]@ie
1656 ; LARGE32-NEXT: L..C15:
1657 ; LARGE32-NEXT: .tc intern_double_nonzero[TE],intern_double_nonzero[TL]@ie
1659 ; SMALL32: L..C0:
1660 ; SMALL32-NEXT: .tc global_int_zero[TC],global_int_zero[TL]@ie
1661 ; SMALL32-NEXT: L..C1:
1662 ; SMALL32-NEXT: .tc global_int_nonzero[TC],global_int_nonzero[TL]@ie
1663 ; SMALL32-NEXT: L..C2:
1664 ; SMALL32-NEXT: .tc intern_int_zero[TC],intern_int_zero[UL]@ie
1665 ; SMALL32-NEXT: L..C3:
1666 ; SMALL32-NEXT: .tc intern_int_nonzero[TC],intern_int_nonzero[TL]@ie
1667 ; SMALL32-NEXT: L..C4:
1668 ; SMALL32-NEXT: .tc global_long_zero[TC],global_long_zero[TL]@ie
1669 ; SMALL32-NEXT: L..C5:
1670 ; SMALL32-NEXT: .tc global_long_nonzero[TC],global_long_nonzero[TL]@ie
1671 ; SMALL32-NEXT: L..C6:
1672 ; SMALL32-NEXT: .tc intern_long_zero[TC],intern_long_zero[UL]@ie
1673 ; SMALL32-NEXT: L..C7:
1674 ; SMALL32-NEXT: .tc intern_long_nonzero[TC],intern_long_nonzero[TL]@ie
1675 ; SMALL32-NEXT: L..C8:
1676 ; SMALL32-NEXT: .tc global_float_zero[TC],global_float_zero[TL]@ie
1677 ; SMALL32-NEXT: L..C9:
1678 ; SMALL32-NEXT: .tc global_float_nonzero[TC],global_float_nonzero[TL]@ie
1679 ; SMALL32-NEXT: L..C10:
1680 ; SMALL32-NEXT: .tc intern_float_zero[TC],intern_float_zero[UL]@ie
1681 ; SMALL32-NEXT: L..C11:
1682 ; SMALL32-NEXT: .tc intern_float_nonzero[TC],intern_float_nonzero[TL]@ie
1683 ; SMALL32-NEXT: L..C12:
1684 ; SMALL32-NEXT: .tc global_double_zero[TC],global_double_zero[TL]@ie
1685 ; SMALL32-NEXT: L..C13:
1686 ; SMALL32-NEXT: .tc global_double_nonzero[TC],global_double_nonzero[TL]@ie
1687 ; SMALL32-NEXT: L..C14:
1688 ; SMALL32-NEXT: .tc intern_double_zero[TC],intern_double_zero[UL]@ie
1689 ; SMALL32-NEXT: L..C15:
1690 ; SMALL32-NEXT: .tc intern_double_nonzero[TC],intern_double_nonzero[TL]@ie