| blob | 69d52fda79baee78f6c93bda47553e81bd0c76c8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CHECK-OPT %s
4 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
5 ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CHECK-O0 %s
6 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
7 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-BE,CHECK-BE-OPT
8 ; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-BE,CHECK-BE-O0
11 ; The following testcases take one halfword element from the second vector and
12 ; inserts it at various locations in the first vector
13 define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) {
14 ; CHECK-LABEL: shuffle_vector_halfword_0_8:
15 ; CHECK: # %bb.0: # %entry
16 ; CHECK-NEXT: vsldoi 3, 3, 3, 8
17 ; CHECK-NEXT: vinserth 2, 3, 14
18 ; CHECK-NEXT: blr
19 ;
20 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_8:
21 ; CHECK-BE: # %bb.0: # %entry
22 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 10
23 ; CHECK-BE-NEXT: vinserth 2, 3, 0
24 ; CHECK-BE-NEXT: blr
25 entry:
26 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
27 ret <8 x i16> %vecins
28 }
30 define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) {
31 ; CHECK-LABEL: shuffle_vector_halfword_1_15:
32 ; CHECK: # %bb.0: # %entry
33 ; CHECK-NEXT: vsldoi 3, 3, 3, 10
34 ; CHECK-NEXT: vinserth 2, 3, 12
35 ; CHECK-NEXT: blr
36 ;
37 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_15:
38 ; CHECK-BE: # %bb.0: # %entry
39 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 8
40 ; CHECK-BE-NEXT: vinserth 2, 3, 2
41 ; CHECK-BE-NEXT: blr
42 entry:
43 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
44 ret <8 x i16> %vecins
45 }
47 define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) {
48 ; CHECK-LABEL: shuffle_vector_halfword_2_9:
49 ; CHECK: # %bb.0: # %entry
50 ; CHECK-NEXT: vsldoi 3, 3, 3, 6
51 ; CHECK-NEXT: vinserth 2, 3, 10
52 ; CHECK-NEXT: blr
53 ;
54 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_9:
55 ; CHECK-BE: # %bb.0: # %entry
56 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 12
57 ; CHECK-BE-NEXT: vinserth 2, 3, 4
58 ; CHECK-BE-NEXT: blr
59 entry:
60 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>
61 ret <8 x i16> %vecins
62 }
64 define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) {
65 ; CHECK-LABEL: shuffle_vector_halfword_3_13:
66 ; CHECK: # %bb.0: # %entry
67 ; CHECK-NEXT: vsldoi 3, 3, 3, 14
68 ; CHECK-NEXT: vinserth 2, 3, 8
69 ; CHECK-NEXT: blr
70 ;
71 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_13:
72 ; CHECK-BE: # %bb.0: # %entry
73 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 4
74 ; CHECK-BE-NEXT: vinserth 2, 3, 6
75 ; CHECK-BE-NEXT: blr
76 entry:
77 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>
78 ret <8 x i16> %vecins
79 }
81 define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) {
82 ; CHECK-LABEL: shuffle_vector_halfword_4_10:
83 ; CHECK: # %bb.0: # %entry
84 ; CHECK-NEXT: vsldoi 3, 3, 3, 4
85 ; CHECK-NEXT: vinserth 2, 3, 6
86 ; CHECK-NEXT: blr
87 ;
88 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_10:
89 ; CHECK-BE: # %bb.0: # %entry
90 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 14
91 ; CHECK-BE-NEXT: vinserth 2, 3, 8
92 ; CHECK-BE-NEXT: blr
93 entry:
94 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7>
95 ret <8 x i16> %vecins
96 }
98 define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) {
99 ; CHECK-LABEL: shuffle_vector_halfword_5_14:
100 ; CHECK: # %bb.0: # %entry
101 ; CHECK-NEXT: vsldoi 3, 3, 3, 12
102 ; CHECK-NEXT: vinserth 2, 3, 4
103 ; CHECK-NEXT: blr
104 ;
105 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_14:
106 ; CHECK-BE: # %bb.0: # %entry
107 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 6
108 ; CHECK-BE-NEXT: vinserth 2, 3, 10
109 ; CHECK-BE-NEXT: blr
110 entry:
111 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7>
112 ret <8 x i16> %vecins
113 }
115 define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) {
116 ; CHECK-LABEL: shuffle_vector_halfword_6_11:
117 ; CHECK: # %bb.0: # %entry
118 ; CHECK-NEXT: vsldoi 3, 3, 3, 2
119 ; CHECK-NEXT: vinserth 2, 3, 2
120 ; CHECK-NEXT: blr
121 ;
122 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_11:
123 ; CHECK-BE: # %bb.0: # %entry
124 ; CHECK-BE-NEXT: vinserth 2, 3, 12
125 ; CHECK-BE-NEXT: blr
126 entry:
127 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7>
128 ret <8 x i16> %vecins
129 }
131 define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) {
132 ; CHECK-LABEL: shuffle_vector_halfword_7_12:
133 ; CHECK: # %bb.0: # %entry
134 ; CHECK-NEXT: vinserth 2, 3, 0
135 ; CHECK-NEXT: blr
136 ;
137 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_12:
138 ; CHECK-BE: # %bb.0: # %entry
139 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 2
140 ; CHECK-BE-NEXT: vinserth 2, 3, 14
141 ; CHECK-BE-NEXT: blr
142 entry:
143 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12>
144 ret <8 x i16> %vecins
145 }
147 define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {
148 ; CHECK-OPT-LABEL: shuffle_vector_halfword_8_1:
149 ; CHECK-OPT: # %bb.0: # %entry
150 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 6
151 ; CHECK-OPT-NEXT: vinserth 3, 2, 14
152 ; CHECK-OPT-NEXT: vmr 2, 3
153 ; CHECK-OPT-NEXT: blr
154 ;
155 ; CHECK-O0-LABEL: shuffle_vector_halfword_8_1:
156 ; CHECK-O0: # %bb.0: # %entry
157 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
158 ; CHECK-O0-NEXT: vmr 3, 2
159 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
160 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 6
161 ; CHECK-O0-NEXT: vinserth 2, 3, 14
162 ; CHECK-O0-NEXT: blr
163 ;
164 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_8_1:
165 ; CHECK-BE-OPT: # %bb.0: # %entry
166 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 12
167 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 0
168 ; CHECK-BE-OPT-NEXT: vmr 2, 3
169 ; CHECK-BE-OPT-NEXT: blr
170 ;
171 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_8_1:
172 ; CHECK-BE-O0: # %bb.0: # %entry
173 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
174 ; CHECK-BE-O0-NEXT: vmr 3, 2
175 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
176 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 12
177 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 0
178 ; CHECK-BE-O0-NEXT: blr
179 entry:
180 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
181 ret <8 x i16> %vecins
182 }
184 ; The following testcases take one halfword element from the first vector and
185 ; inserts it at various locations in the second vector
186 define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {
187 ; CHECK-OPT-LABEL: shuffle_vector_halfword_9_7:
188 ; CHECK-OPT: # %bb.0: # %entry
189 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 10
190 ; CHECK-OPT-NEXT: vinserth 3, 2, 12
191 ; CHECK-OPT-NEXT: vmr 2, 3
192 ; CHECK-OPT-NEXT: blr
193 ;
194 ; CHECK-O0-LABEL: shuffle_vector_halfword_9_7:
195 ; CHECK-O0: # %bb.0: # %entry
196 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
197 ; CHECK-O0-NEXT: vmr 3, 2
198 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
199 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 10
200 ; CHECK-O0-NEXT: vinserth 2, 3, 12
201 ; CHECK-O0-NEXT: blr
202 ;
203 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_9_7:
204 ; CHECK-BE-OPT: # %bb.0: # %entry
205 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 8
206 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 2
207 ; CHECK-BE-OPT-NEXT: vmr 2, 3
208 ; CHECK-BE-OPT-NEXT: blr
209 ;
210 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_9_7:
211 ; CHECK-BE-O0: # %bb.0: # %entry
212 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
213 ; CHECK-BE-O0-NEXT: vmr 3, 2
214 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
215 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 8
216 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 2
217 ; CHECK-BE-O0-NEXT: blr
218 entry:
219 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
220 ret <8 x i16> %vecins
221 }
223 define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) {
224 ; CHECK-OPT-LABEL: shuffle_vector_halfword_10_4:
225 ; CHECK-OPT: # %bb.0: # %entry
226 ; CHECK-OPT-NEXT: vinserth 3, 2, 10
227 ; CHECK-OPT-NEXT: vmr 2, 3
228 ; CHECK-OPT-NEXT: blr
229 ;
230 ; CHECK-O0-LABEL: shuffle_vector_halfword_10_4:
231 ; CHECK-O0: # %bb.0: # %entry
232 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
233 ; CHECK-O0-NEXT: vmr 3, 2
234 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
235 ; CHECK-O0-NEXT: vinserth 2, 3, 10
236 ; CHECK-O0-NEXT: blr
237 ;
238 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_10_4:
239 ; CHECK-BE-OPT: # %bb.0: # %entry
240 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 2
241 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 4
242 ; CHECK-BE-OPT-NEXT: vmr 2, 3
243 ; CHECK-BE-OPT-NEXT: blr
244 ;
245 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_10_4:
246 ; CHECK-BE-O0: # %bb.0: # %entry
247 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
248 ; CHECK-BE-O0-NEXT: vmr 3, 2
249 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
250 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 2
251 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 4
252 ; CHECK-BE-O0-NEXT: blr
253 entry:
254 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>
255 ret <8 x i16> %vecins
256 }
258 define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {
259 ; CHECK-OPT-LABEL: shuffle_vector_halfword_11_2:
260 ; CHECK-OPT: # %bb.0: # %entry
261 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 4
262 ; CHECK-OPT-NEXT: vinserth 3, 2, 8
263 ; CHECK-OPT-NEXT: vmr 2, 3
264 ; CHECK-OPT-NEXT: blr
265 ;
266 ; CHECK-O0-LABEL: shuffle_vector_halfword_11_2:
267 ; CHECK-O0: # %bb.0: # %entry
268 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
269 ; CHECK-O0-NEXT: vmr 3, 2
270 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
271 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 4
272 ; CHECK-O0-NEXT: vinserth 2, 3, 8
273 ; CHECK-O0-NEXT: blr
274 ;
275 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_11_2:
276 ; CHECK-BE-OPT: # %bb.0: # %entry
277 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 14
278 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 6
279 ; CHECK-BE-OPT-NEXT: vmr 2, 3
280 ; CHECK-BE-OPT-NEXT: blr
281 ;
282 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_11_2:
283 ; CHECK-BE-O0: # %bb.0: # %entry
284 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
285 ; CHECK-BE-O0-NEXT: vmr 3, 2
286 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
287 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 14
288 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 6
289 ; CHECK-BE-O0-NEXT: blr
290 entry:
291 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>
292 ret <8 x i16> %vecins
293 }
295 define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {
296 ; CHECK-OPT-LABEL: shuffle_vector_halfword_12_6:
297 ; CHECK-OPT: # %bb.0: # %entry
298 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 12
299 ; CHECK-OPT-NEXT: vinserth 3, 2, 6
300 ; CHECK-OPT-NEXT: vmr 2, 3
301 ; CHECK-OPT-NEXT: blr
302 ;
303 ; CHECK-O0-LABEL: shuffle_vector_halfword_12_6:
304 ; CHECK-O0: # %bb.0: # %entry
305 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
306 ; CHECK-O0-NEXT: vmr 3, 2
307 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
308 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 12
309 ; CHECK-O0-NEXT: vinserth 2, 3, 6
310 ; CHECK-O0-NEXT: blr
311 ;
312 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_12_6:
313 ; CHECK-BE-OPT: # %bb.0: # %entry
314 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 6
315 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 8
316 ; CHECK-BE-OPT-NEXT: vmr 2, 3
317 ; CHECK-BE-OPT-NEXT: blr
318 ;
319 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_12_6:
320 ; CHECK-BE-O0: # %bb.0: # %entry
321 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
322 ; CHECK-BE-O0-NEXT: vmr 3, 2
323 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
324 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 6
325 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 8
326 ; CHECK-BE-O0-NEXT: blr
327 entry:
328 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>
329 ret <8 x i16> %vecins
330 }
332 define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {
333 ; CHECK-OPT-LABEL: shuffle_vector_halfword_13_3:
334 ; CHECK-OPT: # %bb.0: # %entry
335 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 2
336 ; CHECK-OPT-NEXT: vinserth 3, 2, 4
337 ; CHECK-OPT-NEXT: vmr 2, 3
338 ; CHECK-OPT-NEXT: blr
339 ;
340 ; CHECK-O0-LABEL: shuffle_vector_halfword_13_3:
341 ; CHECK-O0: # %bb.0: # %entry
342 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
343 ; CHECK-O0-NEXT: vmr 3, 2
344 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
345 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 2
346 ; CHECK-O0-NEXT: vinserth 2, 3, 4
347 ; CHECK-O0-NEXT: blr
348 ;
349 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_13_3:
350 ; CHECK-BE-OPT: # %bb.0: # %entry
351 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 10
352 ; CHECK-BE-OPT-NEXT: vmr 2, 3
353 ; CHECK-BE-OPT-NEXT: blr
354 ;
355 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_13_3:
356 ; CHECK-BE-O0: # %bb.0: # %entry
357 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
358 ; CHECK-BE-O0-NEXT: vmr 3, 2
359 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
360 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 10
361 ; CHECK-BE-O0-NEXT: blr
362 entry:
363 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15>
364 ret <8 x i16> %vecins
365 }
367 define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {
368 ; CHECK-OPT-LABEL: shuffle_vector_halfword_14_5:
369 ; CHECK-OPT: # %bb.0: # %entry
370 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 14
371 ; CHECK-OPT-NEXT: vinserth 3, 2, 2
372 ; CHECK-OPT-NEXT: vmr 2, 3
373 ; CHECK-OPT-NEXT: blr
374 ;
375 ; CHECK-O0-LABEL: shuffle_vector_halfword_14_5:
376 ; CHECK-O0: # %bb.0: # %entry
377 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
378 ; CHECK-O0-NEXT: vmr 3, 2
379 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
380 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 14
381 ; CHECK-O0-NEXT: vinserth 2, 3, 2
382 ; CHECK-O0-NEXT: blr
383 ;
384 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_14_5:
385 ; CHECK-BE-OPT: # %bb.0: # %entry
386 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 4
387 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 12
388 ; CHECK-BE-OPT-NEXT: vmr 2, 3
389 ; CHECK-BE-OPT-NEXT: blr
390 ;
391 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_14_5:
392 ; CHECK-BE-O0: # %bb.0: # %entry
393 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
394 ; CHECK-BE-O0-NEXT: vmr 3, 2
395 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
396 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 4
397 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 12
398 ; CHECK-BE-O0-NEXT: blr
399 entry:
400 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>
401 ret <8 x i16> %vecins
402 }
404 define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {
405 ; CHECK-OPT-LABEL: shuffle_vector_halfword_15_0:
406 ; CHECK-OPT: # %bb.0: # %entry
407 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 8
408 ; CHECK-OPT-NEXT: vinserth 3, 2, 0
409 ; CHECK-OPT-NEXT: vmr 2, 3
410 ; CHECK-OPT-NEXT: blr
411 ;
412 ; CHECK-O0-LABEL: shuffle_vector_halfword_15_0:
413 ; CHECK-O0: # %bb.0: # %entry
414 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
415 ; CHECK-O0-NEXT: vmr 3, 2
416 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
417 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 8
418 ; CHECK-O0-NEXT: vinserth 2, 3, 0
419 ; CHECK-O0-NEXT: blr
420 ;
421 ; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_15_0:
422 ; CHECK-BE-OPT: # %bb.0: # %entry
423 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 10
424 ; CHECK-BE-OPT-NEXT: vinserth 3, 2, 14
425 ; CHECK-BE-OPT-NEXT: vmr 2, 3
426 ; CHECK-BE-OPT-NEXT: blr
427 ;
428 ; CHECK-BE-O0-LABEL: shuffle_vector_halfword_15_0:
429 ; CHECK-BE-O0: # %bb.0: # %entry
430 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
431 ; CHECK-BE-O0-NEXT: vmr 3, 2
432 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
433 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 10
434 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 14
435 ; CHECK-BE-O0-NEXT: blr
436 entry:
437 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
438 ret <8 x i16> %vecins
439 }
441 ; The following testcases use the same vector in both arguments of the
442 ; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one
443 ; we're attempting to insert, then we can use the vector insert instruction
444 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
445 ; CHECK-LABEL: shuffle_vector_halfword_0_4:
446 ; CHECK: # %bb.0: # %entry
447 ; CHECK-NEXT: vinserth 2, 2, 14
448 ; CHECK-NEXT: blr
449 ;
450 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
451 ; CHECK-BE: # %bb.0: # %entry
452 ; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha
453 ; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l
454 ; CHECK-BE-NEXT: lxv 0, 0(3)
455 ; CHECK-BE-NEXT: xxperm 34, 34, 0
456 ; CHECK-BE-NEXT: blr
457 entry:
458 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
459 ret <8 x i16> %vecins
460 }
462 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
463 ; CHECK-LABEL: shuffle_vector_halfword_1_3:
464 ; CHECK: # %bb.0: # %entry
465 ; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha
466 ; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l
467 ; CHECK-NEXT: lxv 0, 0(3)
468 ; CHECK-NEXT: xxperm 34, 34, 0
469 ; CHECK-NEXT: blr
470 ;
471 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
472 ; CHECK-BE: # %bb.0: # %entry
473 ; CHECK-BE-NEXT: vinserth 2, 2, 2
474 ; CHECK-BE-NEXT: blr
475 entry:
476 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
477 ret <8 x i16> %vecins
478 }
480 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
481 ; CHECK-LABEL: shuffle_vector_halfword_2_3:
482 ; CHECK: # %bb.0: # %entry
483 ; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha
484 ; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l
485 ; CHECK-NEXT: lxv 0, 0(3)
486 ; CHECK-NEXT: xxperm 34, 34, 0
487 ; CHECK-NEXT: blr
488 ;
489 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
490 ; CHECK-BE: # %bb.0: # %entry
491 ; CHECK-BE-NEXT: vinserth 2, 2, 4
492 ; CHECK-BE-NEXT: blr
493 entry:
494 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
495 ret <8 x i16> %vecins
496 }
498 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
499 ; CHECK-LABEL: shuffle_vector_halfword_3_4:
500 ; CHECK: # %bb.0: # %entry
501 ; CHECK-NEXT: vinserth 2, 2, 8
502 ; CHECK-NEXT: blr
503 ;
504 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
505 ; CHECK-BE: # %bb.0: # %entry
506 ; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha
507 ; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l
508 ; CHECK-BE-NEXT: lxv 0, 0(3)
509 ; CHECK-BE-NEXT: xxperm 34, 34, 0
510 ; CHECK-BE-NEXT: blr
511 entry:
512 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
513 ret <8 x i16> %vecins
514 }
516 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
517 ; CHECK-LABEL: shuffle_vector_halfword_4_3:
518 ; CHECK: # %bb.0: # %entry
519 ; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha
520 ; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l
521 ; CHECK-NEXT: lxv 0, 0(3)
522 ; CHECK-NEXT: xxperm 34, 34, 0
523 ; CHECK-NEXT: blr
524 ;
525 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
526 ; CHECK-BE: # %bb.0: # %entry
527 ; CHECK-BE-NEXT: vinserth 2, 2, 8
528 ; CHECK-BE-NEXT: blr
529 entry:
530 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
531 ret <8 x i16> %vecins
532 }
534 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
535 ; CHECK-LABEL: shuffle_vector_halfword_5_3:
536 ; CHECK: # %bb.0: # %entry
537 ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha
538 ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
539 ; CHECK-NEXT: lxv 0, 0(3)
540 ; CHECK-NEXT: xxperm 34, 34, 0
541 ; CHECK-NEXT: blr
542 ;
543 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
544 ; CHECK-BE: # %bb.0: # %entry
545 ; CHECK-BE-NEXT: vinserth 2, 2, 10
546 ; CHECK-BE-NEXT: blr
547 entry:
548 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
549 ret <8 x i16> %vecins
550 }
552 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
553 ; CHECK-LABEL: shuffle_vector_halfword_6_4:
554 ; CHECK: # %bb.0: # %entry
555 ; CHECK-NEXT: vinserth 2, 2, 2
556 ; CHECK-NEXT: blr
557 ;
558 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
559 ; CHECK-BE: # %bb.0: # %entry
560 ; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha
561 ; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l
562 ; CHECK-BE-NEXT: lxv 0, 0(3)
563 ; CHECK-BE-NEXT: xxperm 34, 34, 0
564 ; CHECK-BE-NEXT: blr
565 entry:
566 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
567 ret <8 x i16> %vecins
568 }
570 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
571 ; CHECK-LABEL: shuffle_vector_halfword_7_4:
572 ; CHECK: # %bb.0: # %entry
573 ; CHECK-NEXT: vinserth 2, 2, 0
574 ; CHECK-NEXT: blr
575 ;
576 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
577 ; CHECK-BE: # %bb.0: # %entry
578 ; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha
579 ; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l
580 ; CHECK-BE-NEXT: lxv 0, 0(3)
581 ; CHECK-BE-NEXT: xxperm 34, 34, 0
582 ; CHECK-BE-NEXT: blr
583 entry:
584 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
585 ret <8 x i16> %vecins
586 }
588 ; The following testcases take one byte element from the second vector and
589 ; inserts it at various locations in the first vector
590 define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {
591 ; CHECK-LABEL: shuffle_vector_byte_0_16:
592 ; CHECK: # %bb.0: # %entry
593 ; CHECK-NEXT: vsldoi 3, 3, 3, 8
594 ; CHECK-NEXT: vinsertb 2, 3, 15
595 ; CHECK-NEXT: blr
596 ;
597 ; CHECK-BE-LABEL: shuffle_vector_byte_0_16:
598 ; CHECK-BE: # %bb.0: # %entry
599 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 9
600 ; CHECK-BE-NEXT: vinsertb 2, 3, 0
601 ; CHECK-BE-NEXT: blr
602 entry:
603 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
604 ret <16 x i8> %vecins
605 }
607 define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {
608 ; CHECK-LABEL: shuffle_vector_byte_1_25:
609 ; CHECK: # %bb.0: # %entry
610 ; CHECK-NEXT: vsldoi 3, 3, 3, 15
611 ; CHECK-NEXT: vinsertb 2, 3, 14
612 ; CHECK-NEXT: blr
613 ;
614 ; CHECK-BE-LABEL: shuffle_vector_byte_1_25:
615 ; CHECK-BE: # %bb.0: # %entry
616 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 2
617 ; CHECK-BE-NEXT: vinsertb 2, 3, 1
618 ; CHECK-BE-NEXT: blr
619 entry:
620 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
621 ret <16 x i8> %vecins
622 }
624 define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {
625 ; CHECK-LABEL: shuffle_vector_byte_2_18:
626 ; CHECK: # %bb.0: # %entry
627 ; CHECK-NEXT: vsldoi 3, 3, 3, 6
628 ; CHECK-NEXT: vinsertb 2, 3, 13
629 ; CHECK-NEXT: blr
630 ;
631 ; CHECK-BE-LABEL: shuffle_vector_byte_2_18:
632 ; CHECK-BE: # %bb.0: # %entry
633 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 11
634 ; CHECK-BE-NEXT: vinsertb 2, 3, 2
635 ; CHECK-BE-NEXT: blr
636 entry:
637 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
638 ret <16 x i8> %vecins
639 }
641 define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {
642 ; CHECK-LABEL: shuffle_vector_byte_3_27:
643 ; CHECK: # %bb.0: # %entry
644 ; CHECK-NEXT: vsldoi 3, 3, 3, 13
645 ; CHECK-NEXT: vinsertb 2, 3, 12
646 ; CHECK-NEXT: blr
647 ;
648 ; CHECK-BE-LABEL: shuffle_vector_byte_3_27:
649 ; CHECK-BE: # %bb.0: # %entry
650 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 4
651 ; CHECK-BE-NEXT: vinsertb 2, 3, 3
652 ; CHECK-BE-NEXT: blr
653 entry:
654 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
655 ret <16 x i8> %vecins
656 }
658 define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {
659 ; CHECK-LABEL: shuffle_vector_byte_4_20:
660 ; CHECK: # %bb.0: # %entry
661 ; CHECK-NEXT: vsldoi 3, 3, 3, 4
662 ; CHECK-NEXT: vinsertb 2, 3, 11
663 ; CHECK-NEXT: blr
664 ;
665 ; CHECK-BE-LABEL: shuffle_vector_byte_4_20:
666 ; CHECK-BE: # %bb.0: # %entry
667 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 13
668 ; CHECK-BE-NEXT: vinsertb 2, 3, 4
669 ; CHECK-BE-NEXT: blr
670 entry:
671 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
672 ret <16 x i8> %vecins
673 }
675 define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {
676 ; CHECK-LABEL: shuffle_vector_byte_5_29:
677 ; CHECK: # %bb.0: # %entry
678 ; CHECK-NEXT: vsldoi 3, 3, 3, 11
679 ; CHECK-NEXT: vinsertb 2, 3, 10
680 ; CHECK-NEXT: blr
681 ;
682 ; CHECK-BE-LABEL: shuffle_vector_byte_5_29:
683 ; CHECK-BE: # %bb.0: # %entry
684 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 6
685 ; CHECK-BE-NEXT: vinsertb 2, 3, 5
686 ; CHECK-BE-NEXT: blr
687 entry:
688 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
689 ret <16 x i8> %vecins
690 }
692 define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {
693 ; CHECK-LABEL: shuffle_vector_byte_6_22:
694 ; CHECK: # %bb.0: # %entry
695 ; CHECK-NEXT: vsldoi 3, 3, 3, 2
696 ; CHECK-NEXT: vinsertb 2, 3, 9
697 ; CHECK-NEXT: blr
698 ;
699 ; CHECK-BE-LABEL: shuffle_vector_byte_6_22:
700 ; CHECK-BE: # %bb.0: # %entry
701 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 15
702 ; CHECK-BE-NEXT: vinsertb 2, 3, 6
703 ; CHECK-BE-NEXT: blr
704 entry:
705 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
706 ret <16 x i8> %vecins
707 }
709 define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {
710 ; CHECK-LABEL: shuffle_vector_byte_7_31:
711 ; CHECK: # %bb.0: # %entry
712 ; CHECK-NEXT: vsldoi 3, 3, 3, 9
713 ; CHECK-NEXT: vinsertb 2, 3, 8
714 ; CHECK-NEXT: blr
715 ;
716 ; CHECK-BE-LABEL: shuffle_vector_byte_7_31:
717 ; CHECK-BE: # %bb.0: # %entry
718 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 8
719 ; CHECK-BE-NEXT: vinsertb 2, 3, 7
720 ; CHECK-BE-NEXT: blr
721 entry:
722 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
723 ret <16 x i8> %vecins
724 }
726 define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {
727 ; CHECK-LABEL: shuffle_vector_byte_8_24:
728 ; CHECK: # %bb.0: # %entry
729 ; CHECK-NEXT: vinsertb 2, 3, 7
730 ; CHECK-NEXT: blr
731 ;
732 ; CHECK-BE-LABEL: shuffle_vector_byte_8_24:
733 ; CHECK-BE: # %bb.0: # %entry
734 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 1
735 ; CHECK-BE-NEXT: vinsertb 2, 3, 8
736 ; CHECK-BE-NEXT: blr
737 entry:
738 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
739 ret <16 x i8> %vecins
740 }
742 define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {
743 ; CHECK-LABEL: shuffle_vector_byte_9_17:
744 ; CHECK: # %bb.0: # %entry
745 ; CHECK-NEXT: vsldoi 3, 3, 3, 7
746 ; CHECK-NEXT: vinsertb 2, 3, 6
747 ; CHECK-NEXT: blr
748 ;
749 ; CHECK-BE-LABEL: shuffle_vector_byte_9_17:
750 ; CHECK-BE: # %bb.0: # %entry
751 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 10
752 ; CHECK-BE-NEXT: vinsertb 2, 3, 9
753 ; CHECK-BE-NEXT: blr
754 entry:
755 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
756 ret <16 x i8> %vecins
757 }
759 define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {
760 ; CHECK-LABEL: shuffle_vector_byte_10_26:
761 ; CHECK: # %bb.0: # %entry
762 ; CHECK-NEXT: vsldoi 3, 3, 3, 14
763 ; CHECK-NEXT: vinsertb 2, 3, 5
764 ; CHECK-NEXT: blr
765 ;
766 ; CHECK-BE-LABEL: shuffle_vector_byte_10_26:
767 ; CHECK-BE: # %bb.0: # %entry
768 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 3
769 ; CHECK-BE-NEXT: vinsertb 2, 3, 10
770 ; CHECK-BE-NEXT: blr
771 entry:
772 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>
773 ret <16 x i8> %vecins
774 }
776 define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {
777 ; CHECK-LABEL: shuffle_vector_byte_11_19:
778 ; CHECK: # %bb.0: # %entry
779 ; CHECK-NEXT: vsldoi 3, 3, 3, 5
780 ; CHECK-NEXT: vinsertb 2, 3, 4
781 ; CHECK-NEXT: blr
782 ;
783 ; CHECK-BE-LABEL: shuffle_vector_byte_11_19:
784 ; CHECK-BE: # %bb.0: # %entry
785 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 12
786 ; CHECK-BE-NEXT: vinsertb 2, 3, 11
787 ; CHECK-BE-NEXT: blr
788 entry:
789 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15>
790 ret <16 x i8> %vecins
791 }
793 define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {
794 ; CHECK-LABEL: shuffle_vector_byte_12_28:
795 ; CHECK: # %bb.0: # %entry
796 ; CHECK-NEXT: vsldoi 3, 3, 3, 12
797 ; CHECK-NEXT: vinsertb 2, 3, 3
798 ; CHECK-NEXT: blr
799 ;
800 ; CHECK-BE-LABEL: shuffle_vector_byte_12_28:
801 ; CHECK-BE: # %bb.0: # %entry
802 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 5
803 ; CHECK-BE-NEXT: vinsertb 2, 3, 12
804 ; CHECK-BE-NEXT: blr
805 entry:
806 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15>
807 ret <16 x i8> %vecins
808 }
810 define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {
811 ; CHECK-LABEL: shuffle_vector_byte_13_21:
812 ; CHECK: # %bb.0: # %entry
813 ; CHECK-NEXT: vsldoi 3, 3, 3, 3
814 ; CHECK-NEXT: vinsertb 2, 3, 2
815 ; CHECK-NEXT: blr
816 ;
817 ; CHECK-BE-LABEL: shuffle_vector_byte_13_21:
818 ; CHECK-BE: # %bb.0: # %entry
819 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 14
820 ; CHECK-BE-NEXT: vinsertb 2, 3, 13
821 ; CHECK-BE-NEXT: blr
822 entry:
823 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15>
824 ret <16 x i8> %vecins
825 }
827 define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {
828 ; CHECK-LABEL: shuffle_vector_byte_14_30:
829 ; CHECK: # %bb.0: # %entry
830 ; CHECK-NEXT: vsldoi 3, 3, 3, 10
831 ; CHECK-NEXT: vinsertb 2, 3, 1
832 ; CHECK-NEXT: blr
833 ;
834 ; CHECK-BE-LABEL: shuffle_vector_byte_14_30:
835 ; CHECK-BE: # %bb.0: # %entry
836 ; CHECK-BE-NEXT: vsldoi 3, 3, 3, 7
837 ; CHECK-BE-NEXT: vinsertb 2, 3, 14
838 ; CHECK-BE-NEXT: blr
839 entry:
840 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>
841 ret <16 x i8> %vecins
842 }
844 define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {
845 ; CHECK-LABEL: shuffle_vector_byte_15_23:
846 ; CHECK: # %bb.0: # %entry
847 ; CHECK-NEXT: vsldoi 3, 3, 3, 1
848 ; CHECK-NEXT: vinsertb 2, 3, 0
849 ; CHECK-NEXT: blr
850 ;
851 ; CHECK-BE-LABEL: shuffle_vector_byte_15_23:
852 ; CHECK-BE: # %bb.0: # %entry
853 ; CHECK-BE-NEXT: vinsertb 2, 3, 15
854 ; CHECK-BE-NEXT: blr
855 entry:
856 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23>
857 ret <16 x i8> %vecins
858 }
860 ; The following testcases take one byte element from the first vector and
861 ; inserts it at various locations in the second vector
862 define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) {
863 ; CHECK-OPT-LABEL: shuffle_vector_byte_16_8:
864 ; CHECK-OPT: # %bb.0: # %entry
865 ; CHECK-OPT-NEXT: vinsertb 3, 2, 15
866 ; CHECK-OPT-NEXT: vmr 2, 3
867 ; CHECK-OPT-NEXT: blr
868 ;
869 ; CHECK-O0-LABEL: shuffle_vector_byte_16_8:
870 ; CHECK-O0: # %bb.0: # %entry
871 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
872 ; CHECK-O0-NEXT: vmr 3, 2
873 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
874 ; CHECK-O0-NEXT: vinsertb 2, 3, 15
875 ; CHECK-O0-NEXT: blr
876 ;
877 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_16_8:
878 ; CHECK-BE-OPT: # %bb.0: # %entry
879 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 1
880 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 0
881 ; CHECK-BE-OPT-NEXT: vmr 2, 3
882 ; CHECK-BE-OPT-NEXT: blr
883 ;
884 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_16_8:
885 ; CHECK-BE-O0: # %bb.0: # %entry
886 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
887 ; CHECK-BE-O0-NEXT: vmr 3, 2
888 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
889 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 1
890 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 0
891 ; CHECK-BE-O0-NEXT: blr
892 entry:
893 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
894 ret <16 x i8> %vecins
895 }
897 define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) {
898 ; CHECK-OPT-LABEL: shuffle_vector_byte_17_1:
899 ; CHECK-OPT: # %bb.0: # %entry
900 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 7
901 ; CHECK-OPT-NEXT: vinsertb 3, 2, 14
902 ; CHECK-OPT-NEXT: vmr 2, 3
903 ; CHECK-OPT-NEXT: blr
904 ;
905 ; CHECK-O0-LABEL: shuffle_vector_byte_17_1:
906 ; CHECK-O0: # %bb.0: # %entry
907 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
908 ; CHECK-O0-NEXT: vmr 3, 2
909 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
910 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 7
911 ; CHECK-O0-NEXT: vinsertb 2, 3, 14
912 ; CHECK-O0-NEXT: blr
913 ;
914 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_17_1:
915 ; CHECK-BE-OPT: # %bb.0: # %entry
916 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 10
917 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 1
918 ; CHECK-BE-OPT-NEXT: vmr 2, 3
919 ; CHECK-BE-OPT-NEXT: blr
920 ;
921 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_17_1:
922 ; CHECK-BE-O0: # %bb.0: # %entry
923 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
924 ; CHECK-BE-O0-NEXT: vmr 3, 2
925 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
926 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 10
927 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 1
928 ; CHECK-BE-O0-NEXT: blr
929 entry:
930 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
931 ret <16 x i8> %vecins
932 }
934 define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) {
935 ; CHECK-OPT-LABEL: shuffle_vector_byte_18_10:
936 ; CHECK-OPT: # %bb.0: # %entry
937 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 14
938 ; CHECK-OPT-NEXT: vinsertb 3, 2, 13
939 ; CHECK-OPT-NEXT: vmr 2, 3
940 ; CHECK-OPT-NEXT: blr
941 ;
942 ; CHECK-O0-LABEL: shuffle_vector_byte_18_10:
943 ; CHECK-O0: # %bb.0: # %entry
944 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
945 ; CHECK-O0-NEXT: vmr 3, 2
946 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
947 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 14
948 ; CHECK-O0-NEXT: vinsertb 2, 3, 13
949 ; CHECK-O0-NEXT: blr
950 ;
951 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_18_10:
952 ; CHECK-BE-OPT: # %bb.0: # %entry
953 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 3
954 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 2
955 ; CHECK-BE-OPT-NEXT: vmr 2, 3
956 ; CHECK-BE-OPT-NEXT: blr
957 ;
958 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_18_10:
959 ; CHECK-BE-O0: # %bb.0: # %entry
960 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
961 ; CHECK-BE-O0-NEXT: vmr 3, 2
962 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
963 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 3
964 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 2
965 ; CHECK-BE-O0-NEXT: blr
966 entry:
967 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
968 ret <16 x i8> %vecins
969 }
971 define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) {
972 ; CHECK-OPT-LABEL: shuffle_vector_byte_19_3:
973 ; CHECK-OPT: # %bb.0: # %entry
974 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 5
975 ; CHECK-OPT-NEXT: vinsertb 3, 2, 12
976 ; CHECK-OPT-NEXT: vmr 2, 3
977 ; CHECK-OPT-NEXT: blr
978 ;
979 ; CHECK-O0-LABEL: shuffle_vector_byte_19_3:
980 ; CHECK-O0: # %bb.0: # %entry
981 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
982 ; CHECK-O0-NEXT: vmr 3, 2
983 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
984 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 5
985 ; CHECK-O0-NEXT: vinsertb 2, 3, 12
986 ; CHECK-O0-NEXT: blr
987 ;
988 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_19_3:
989 ; CHECK-BE-OPT: # %bb.0: # %entry
990 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 12
991 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 3
992 ; CHECK-BE-OPT-NEXT: vmr 2, 3
993 ; CHECK-BE-OPT-NEXT: blr
994 ;
995 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_19_3:
996 ; CHECK-BE-O0: # %bb.0: # %entry
997 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
998 ; CHECK-BE-O0-NEXT: vmr 3, 2
999 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1000 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 12
1001 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 3
1002 ; CHECK-BE-O0-NEXT: blr
1003 entry:
1004 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1005 ret <16 x i8> %vecins
1006 }
1008 define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) {
1009 ; CHECK-OPT-LABEL: shuffle_vector_byte_20_12:
1010 ; CHECK-OPT: # %bb.0: # %entry
1011 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 12
1012 ; CHECK-OPT-NEXT: vinsertb 3, 2, 11
1013 ; CHECK-OPT-NEXT: vmr 2, 3
1014 ; CHECK-OPT-NEXT: blr
1015 ;
1016 ; CHECK-O0-LABEL: shuffle_vector_byte_20_12:
1017 ; CHECK-O0: # %bb.0: # %entry
1018 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1019 ; CHECK-O0-NEXT: vmr 3, 2
1020 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1021 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 12
1022 ; CHECK-O0-NEXT: vinsertb 2, 3, 11
1023 ; CHECK-O0-NEXT: blr
1024 ;
1025 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_20_12:
1026 ; CHECK-BE-OPT: # %bb.0: # %entry
1027 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 5
1028 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 4
1029 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1030 ; CHECK-BE-OPT-NEXT: blr
1031 ;
1032 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_20_12:
1033 ; CHECK-BE-O0: # %bb.0: # %entry
1034 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1035 ; CHECK-BE-O0-NEXT: vmr 3, 2
1036 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1037 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 5
1038 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 4
1039 ; CHECK-BE-O0-NEXT: blr
1040 entry:
1041 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1042 ret <16 x i8> %vecins
1043 }
1045 define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) {
1046 ; CHECK-OPT-LABEL: shuffle_vector_byte_21_5:
1047 ; CHECK-OPT: # %bb.0: # %entry
1048 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 3
1049 ; CHECK-OPT-NEXT: vinsertb 3, 2, 10
1050 ; CHECK-OPT-NEXT: vmr 2, 3
1051 ; CHECK-OPT-NEXT: blr
1052 ;
1053 ; CHECK-O0-LABEL: shuffle_vector_byte_21_5:
1054 ; CHECK-O0: # %bb.0: # %entry
1055 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1056 ; CHECK-O0-NEXT: vmr 3, 2
1057 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1058 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 3
1059 ; CHECK-O0-NEXT: vinsertb 2, 3, 10
1060 ; CHECK-O0-NEXT: blr
1061 ;
1062 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_21_5:
1063 ; CHECK-BE-OPT: # %bb.0: # %entry
1064 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 14
1065 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 5
1066 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1067 ; CHECK-BE-OPT-NEXT: blr
1068 ;
1069 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_21_5:
1070 ; CHECK-BE-O0: # %bb.0: # %entry
1071 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1072 ; CHECK-BE-O0-NEXT: vmr 3, 2
1073 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1074 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 14
1075 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 5
1076 ; CHECK-BE-O0-NEXT: blr
1077 entry:
1078 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1079 ret <16 x i8> %vecins
1080 }
1082 define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) {
1083 ; CHECK-OPT-LABEL: shuffle_vector_byte_22_14:
1084 ; CHECK-OPT: # %bb.0: # %entry
1085 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 10
1086 ; CHECK-OPT-NEXT: vinsertb 3, 2, 9
1087 ; CHECK-OPT-NEXT: vmr 2, 3
1088 ; CHECK-OPT-NEXT: blr
1089 ;
1090 ; CHECK-O0-LABEL: shuffle_vector_byte_22_14:
1091 ; CHECK-O0: # %bb.0: # %entry
1092 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1093 ; CHECK-O0-NEXT: vmr 3, 2
1094 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1095 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 10
1096 ; CHECK-O0-NEXT: vinsertb 2, 3, 9
1097 ; CHECK-O0-NEXT: blr
1098 ;
1099 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_22_14:
1100 ; CHECK-BE-OPT: # %bb.0: # %entry
1101 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 7
1102 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 6
1103 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1104 ; CHECK-BE-OPT-NEXT: blr
1105 ;
1106 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_22_14:
1107 ; CHECK-BE-O0: # %bb.0: # %entry
1108 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1109 ; CHECK-BE-O0-NEXT: vmr 3, 2
1110 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1111 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 7
1112 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 6
1113 ; CHECK-BE-O0-NEXT: blr
1114 entry:
1115 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1116 ret <16 x i8> %vecins
1117 }
1119 define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) {
1120 ; CHECK-OPT-LABEL: shuffle_vector_byte_23_7:
1121 ; CHECK-OPT: # %bb.0: # %entry
1122 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 1
1123 ; CHECK-OPT-NEXT: vinsertb 3, 2, 8
1124 ; CHECK-OPT-NEXT: vmr 2, 3
1125 ; CHECK-OPT-NEXT: blr
1126 ;
1127 ; CHECK-O0-LABEL: shuffle_vector_byte_23_7:
1128 ; CHECK-O0: # %bb.0: # %entry
1129 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1130 ; CHECK-O0-NEXT: vmr 3, 2
1131 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1132 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 1
1133 ; CHECK-O0-NEXT: vinsertb 2, 3, 8
1134 ; CHECK-O0-NEXT: blr
1135 ;
1136 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_23_7:
1137 ; CHECK-BE-OPT: # %bb.0: # %entry
1138 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 7
1139 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1140 ; CHECK-BE-OPT-NEXT: blr
1141 ;
1142 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_23_7:
1143 ; CHECK-BE-O0: # %bb.0: # %entry
1144 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1145 ; CHECK-BE-O0-NEXT: vmr 3, 2
1146 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1147 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 7
1148 ; CHECK-BE-O0-NEXT: blr
1149 entry:
1150 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1151 ret <16 x i8> %vecins
1152 }
1154 define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) {
1155 ; CHECK-OPT-LABEL: shuffle_vector_byte_24_0:
1156 ; CHECK-OPT: # %bb.0: # %entry
1157 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 8
1158 ; CHECK-OPT-NEXT: vinsertb 3, 2, 7
1159 ; CHECK-OPT-NEXT: vmr 2, 3
1160 ; CHECK-OPT-NEXT: blr
1161 ;
1162 ; CHECK-O0-LABEL: shuffle_vector_byte_24_0:
1163 ; CHECK-O0: # %bb.0: # %entry
1164 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1165 ; CHECK-O0-NEXT: vmr 3, 2
1166 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1167 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 8
1168 ; CHECK-O0-NEXT: vinsertb 2, 3, 7
1169 ; CHECK-O0-NEXT: blr
1170 ;
1171 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_24_0:
1172 ; CHECK-BE-OPT: # %bb.0: # %entry
1173 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 9
1174 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 8
1175 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1176 ; CHECK-BE-OPT-NEXT: blr
1177 ;
1178 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_24_0:
1179 ; CHECK-BE-O0: # %bb.0: # %entry
1180 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1181 ; CHECK-BE-O0-NEXT: vmr 3, 2
1182 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1183 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 9
1184 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 8
1185 ; CHECK-BE-O0-NEXT: blr
1186 entry:
1187 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1188 ret <16 x i8> %vecins
1189 }
1191 define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) {
1192 ; CHECK-OPT-LABEL: shuffle_vector_byte_25_9:
1193 ; CHECK-OPT: # %bb.0: # %entry
1194 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 15
1195 ; CHECK-OPT-NEXT: vinsertb 3, 2, 6
1196 ; CHECK-OPT-NEXT: vmr 2, 3
1197 ; CHECK-OPT-NEXT: blr
1198 ;
1199 ; CHECK-O0-LABEL: shuffle_vector_byte_25_9:
1200 ; CHECK-O0: # %bb.0: # %entry
1201 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1202 ; CHECK-O0-NEXT: vmr 3, 2
1203 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1204 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 15
1205 ; CHECK-O0-NEXT: vinsertb 2, 3, 6
1206 ; CHECK-O0-NEXT: blr
1207 ;
1208 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_25_9:
1209 ; CHECK-BE-OPT: # %bb.0: # %entry
1210 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 2
1211 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 9
1212 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1213 ; CHECK-BE-OPT-NEXT: blr
1214 ;
1215 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_25_9:
1216 ; CHECK-BE-O0: # %bb.0: # %entry
1217 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1218 ; CHECK-BE-O0-NEXT: vmr 3, 2
1219 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1220 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 2
1221 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 9
1222 ; CHECK-BE-O0-NEXT: blr
1223 entry:
1224 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
1225 ret <16 x i8> %vecins
1226 }
1228 define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) {
1229 ; CHECK-OPT-LABEL: shuffle_vector_byte_26_2:
1230 ; CHECK-OPT: # %bb.0: # %entry
1231 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 6
1232 ; CHECK-OPT-NEXT: vinsertb 3, 2, 5
1233 ; CHECK-OPT-NEXT: vmr 2, 3
1234 ; CHECK-OPT-NEXT: blr
1235 ;
1236 ; CHECK-O0-LABEL: shuffle_vector_byte_26_2:
1237 ; CHECK-O0: # %bb.0: # %entry
1238 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1239 ; CHECK-O0-NEXT: vmr 3, 2
1240 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1241 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 6
1242 ; CHECK-O0-NEXT: vinsertb 2, 3, 5
1243 ; CHECK-O0-NEXT: blr
1244 ;
1245 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_26_2:
1246 ; CHECK-BE-OPT: # %bb.0: # %entry
1247 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 11
1248 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 10
1249 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1250 ; CHECK-BE-OPT-NEXT: blr
1251 ;
1252 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_26_2:
1253 ; CHECK-BE-O0: # %bb.0: # %entry
1254 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1255 ; CHECK-BE-O0-NEXT: vmr 3, 2
1256 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1257 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 11
1258 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 10
1259 ; CHECK-BE-O0-NEXT: blr
1260 entry:
1261 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31>
1262 ret <16 x i8> %vecins
1263 }
1265 define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) {
1266 ; CHECK-OPT-LABEL: shuffle_vector_byte_27_11:
1267 ; CHECK-OPT: # %bb.0: # %entry
1268 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 13
1269 ; CHECK-OPT-NEXT: vinsertb 3, 2, 4
1270 ; CHECK-OPT-NEXT: vmr 2, 3
1271 ; CHECK-OPT-NEXT: blr
1272 ;
1273 ; CHECK-O0-LABEL: shuffle_vector_byte_27_11:
1274 ; CHECK-O0: # %bb.0: # %entry
1275 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1276 ; CHECK-O0-NEXT: vmr 3, 2
1277 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1278 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 13
1279 ; CHECK-O0-NEXT: vinsertb 2, 3, 4
1280 ; CHECK-O0-NEXT: blr
1281 ;
1282 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_27_11:
1283 ; CHECK-BE-OPT: # %bb.0: # %entry
1284 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 4
1285 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 11
1286 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1287 ; CHECK-BE-OPT-NEXT: blr
1288 ;
1289 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_27_11:
1290 ; CHECK-BE-O0: # %bb.0: # %entry
1291 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1292 ; CHECK-BE-O0-NEXT: vmr 3, 2
1293 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1294 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 4
1295 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 11
1296 ; CHECK-BE-O0-NEXT: blr
1297 entry:
1298 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31>
1299 ret <16 x i8> %vecins
1300 }
1302 define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) {
1303 ; CHECK-OPT-LABEL: shuffle_vector_byte_28_4:
1304 ; CHECK-OPT: # %bb.0: # %entry
1305 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 4
1306 ; CHECK-OPT-NEXT: vinsertb 3, 2, 3
1307 ; CHECK-OPT-NEXT: vmr 2, 3
1308 ; CHECK-OPT-NEXT: blr
1309 ;
1310 ; CHECK-O0-LABEL: shuffle_vector_byte_28_4:
1311 ; CHECK-O0: # %bb.0: # %entry
1312 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1313 ; CHECK-O0-NEXT: vmr 3, 2
1314 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1315 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 4
1316 ; CHECK-O0-NEXT: vinsertb 2, 3, 3
1317 ; CHECK-O0-NEXT: blr
1318 ;
1319 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_28_4:
1320 ; CHECK-BE-OPT: # %bb.0: # %entry
1321 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 13
1322 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 12
1323 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1324 ; CHECK-BE-OPT-NEXT: blr
1325 ;
1326 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_28_4:
1327 ; CHECK-BE-O0: # %bb.0: # %entry
1328 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1329 ; CHECK-BE-O0-NEXT: vmr 3, 2
1330 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1331 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 13
1332 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 12
1333 ; CHECK-BE-O0-NEXT: blr
1334 entry:
1335 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31>
1336 ret <16 x i8> %vecins
1337 }
1339 define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) {
1340 ; CHECK-OPT-LABEL: shuffle_vector_byte_29_13:
1341 ; CHECK-OPT: # %bb.0: # %entry
1342 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 11
1343 ; CHECK-OPT-NEXT: vinsertb 3, 2, 2
1344 ; CHECK-OPT-NEXT: vmr 2, 3
1345 ; CHECK-OPT-NEXT: blr
1346 ;
1347 ; CHECK-O0-LABEL: shuffle_vector_byte_29_13:
1348 ; CHECK-O0: # %bb.0: # %entry
1349 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1350 ; CHECK-O0-NEXT: vmr 3, 2
1351 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1352 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 11
1353 ; CHECK-O0-NEXT: vinsertb 2, 3, 2
1354 ; CHECK-O0-NEXT: blr
1355 ;
1356 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_29_13:
1357 ; CHECK-BE-OPT: # %bb.0: # %entry
1358 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 6
1359 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 13
1360 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1361 ; CHECK-BE-OPT-NEXT: blr
1362 ;
1363 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_29_13:
1364 ; CHECK-BE-O0: # %bb.0: # %entry
1365 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1366 ; CHECK-BE-O0-NEXT: vmr 3, 2
1367 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1368 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 6
1369 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 13
1370 ; CHECK-BE-O0-NEXT: blr
1371 entry:
1372 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31>
1373 ret <16 x i8> %vecins
1374 }
1376 define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) {
1377 ; CHECK-OPT-LABEL: shuffle_vector_byte_30_6:
1378 ; CHECK-OPT: # %bb.0: # %entry
1379 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 2
1380 ; CHECK-OPT-NEXT: vinsertb 3, 2, 1
1381 ; CHECK-OPT-NEXT: vmr 2, 3
1382 ; CHECK-OPT-NEXT: blr
1383 ;
1384 ; CHECK-O0-LABEL: shuffle_vector_byte_30_6:
1385 ; CHECK-O0: # %bb.0: # %entry
1386 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1387 ; CHECK-O0-NEXT: vmr 3, 2
1388 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1389 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 2
1390 ; CHECK-O0-NEXT: vinsertb 2, 3, 1
1391 ; CHECK-O0-NEXT: blr
1392 ;
1393 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_30_6:
1394 ; CHECK-BE-OPT: # %bb.0: # %entry
1395 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 15
1396 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 14
1397 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1398 ; CHECK-BE-OPT-NEXT: blr
1399 ;
1400 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_30_6:
1401 ; CHECK-BE-O0: # %bb.0: # %entry
1402 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1403 ; CHECK-BE-O0-NEXT: vmr 3, 2
1404 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1405 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 15
1406 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 14
1407 ; CHECK-BE-O0-NEXT: blr
1408 entry:
1409 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31>
1410 ret <16 x i8> %vecins
1411 }
1413 define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) {
1414 ; CHECK-OPT-LABEL: shuffle_vector_byte_31_15:
1415 ; CHECK-OPT: # %bb.0: # %entry
1416 ; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 9
1417 ; CHECK-OPT-NEXT: vinsertb 3, 2, 0
1418 ; CHECK-OPT-NEXT: vmr 2, 3
1419 ; CHECK-OPT-NEXT: blr
1420 ;
1421 ; CHECK-O0-LABEL: shuffle_vector_byte_31_15:
1422 ; CHECK-O0: # %bb.0: # %entry
1423 ; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1424 ; CHECK-O0-NEXT: vmr 3, 2
1425 ; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1426 ; CHECK-O0-NEXT: vsldoi 3, 3, 3, 9
1427 ; CHECK-O0-NEXT: vinsertb 2, 3, 0
1428 ; CHECK-O0-NEXT: blr
1429 ;
1430 ; CHECK-BE-OPT-LABEL: shuffle_vector_byte_31_15:
1431 ; CHECK-BE-OPT: # %bb.0: # %entry
1432 ; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 8
1433 ; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 15
1434 ; CHECK-BE-OPT-NEXT: vmr 2, 3
1435 ; CHECK-BE-OPT-NEXT: blr
1436 ;
1437 ; CHECK-BE-O0-LABEL: shuffle_vector_byte_31_15:
1438 ; CHECK-BE-O0: # %bb.0: # %entry
1439 ; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill
1440 ; CHECK-BE-O0-NEXT: vmr 3, 2
1441 ; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload
1442 ; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 8
1443 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 15
1444 ; CHECK-BE-O0-NEXT: blr
1445 entry:
1446 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>
1447 ret <16 x i8> %vecins
1448 }
1450 ; The following testcases use the same vector in both arguments of the
1451 ; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one
1452 ; we're attempting to insert, then we can use the vector insert instruction
1453 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
1454 ; CHECK-LABEL: shuffle_vector_byte_0_7:
1455 ; CHECK: # %bb.0: # %entry
1456 ; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha
1457 ; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l
1458 ; CHECK-NEXT: lxv 0, 0(3)
1459 ; CHECK-NEXT: xxperm 34, 34, 0
1460 ; CHECK-NEXT: blr
1461 ;
1462 ; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
1463 ; CHECK-BE: # %bb.0: # %entry
1464 ; CHECK-BE-NEXT: vinsertb 2, 2, 0
1465 ; CHECK-BE-NEXT: blr
1466 entry:
1467 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1468 ret <16 x i8> %vecins
1469 }
1471 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
1472 ; CHECK-LABEL: shuffle_vector_byte_1_8:
1473 ; CHECK: # %bb.0: # %entry
1474 ; CHECK-NEXT: vinsertb 2, 2, 14
1475 ; CHECK-NEXT: blr
1476 ;
1477 ; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
1478 ; CHECK-BE: # %bb.0: # %entry
1479 ; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha
1480 ; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l
1481 ; CHECK-BE-NEXT: lxv 0, 0(3)
1482 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1483 ; CHECK-BE-NEXT: blr
1484 entry:
1485 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1486 ret <16 x i8> %vecins
1487 }
1489 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
1490 ; CHECK-LABEL: shuffle_vector_byte_2_8:
1491 ; CHECK: # %bb.0: # %entry
1492 ; CHECK-NEXT: vinsertb 2, 2, 13
1493 ; CHECK-NEXT: blr
1494 ;
1495 ; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
1496 ; CHECK-BE: # %bb.0: # %entry
1497 ; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha
1498 ; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l
1499 ; CHECK-BE-NEXT: lxv 0, 0(3)
1500 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1501 ; CHECK-BE-NEXT: blr
1502 entry:
1503 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1504 ret <16 x i8> %vecins
1505 }
1507 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
1508 ; CHECK-LABEL: shuffle_vector_byte_3_7:
1509 ; CHECK: # %bb.0: # %entry
1510 ; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha
1511 ; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l
1512 ; CHECK-NEXT: lxv 0, 0(3)
1513 ; CHECK-NEXT: xxperm 34, 34, 0
1514 ; CHECK-NEXT: blr
1515 ;
1516 ; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
1517 ; CHECK-BE: # %bb.0: # %entry
1518 ; CHECK-BE-NEXT: vinsertb 2, 2, 3
1519 ; CHECK-BE-NEXT: blr
1520 entry:
1521 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1522 ret <16 x i8> %vecins
1523 }
1525 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
1526 ; CHECK-LABEL: shuffle_vector_byte_4_7:
1527 ; CHECK: # %bb.0: # %entry
1528 ; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha
1529 ; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l
1530 ; CHECK-NEXT: lxv 0, 0(3)
1531 ; CHECK-NEXT: xxperm 34, 34, 0
1532 ; CHECK-NEXT: blr
1533 ;
1534 ; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
1535 ; CHECK-BE: # %bb.0: # %entry
1536 ; CHECK-BE-NEXT: vinsertb 2, 2, 4
1537 ; CHECK-BE-NEXT: blr
1538 entry:
1539 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1540 ret <16 x i8> %vecins
1541 }
1543 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
1544 ; CHECK-LABEL: shuffle_vector_byte_5_8:
1545 ; CHECK: # %bb.0: # %entry
1546 ; CHECK-NEXT: vinsertb 2, 2, 10
1547 ; CHECK-NEXT: blr
1548 ;
1549 ; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
1550 ; CHECK-BE: # %bb.0: # %entry
1551 ; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha
1552 ; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l
1553 ; CHECK-BE-NEXT: lxv 0, 0(3)
1554 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1555 ; CHECK-BE-NEXT: blr
1556 entry:
1557 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1558 ret <16 x i8> %vecins
1559 }
1561 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
1562 ; CHECK-LABEL: shuffle_vector_byte_6_8:
1563 ; CHECK: # %bb.0: # %entry
1564 ; CHECK-NEXT: vinsertb 2, 2, 9
1565 ; CHECK-NEXT: blr
1566 ;
1567 ; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
1568 ; CHECK-BE: # %bb.0: # %entry
1569 ; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha
1570 ; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l
1571 ; CHECK-BE-NEXT: lxv 0, 0(3)
1572 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1573 ; CHECK-BE-NEXT: blr
1574 entry:
1575 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1576 ret <16 x i8> %vecins
1577 }
1579 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
1580 ; CHECK-LABEL: shuffle_vector_byte_7_8:
1581 ; CHECK: # %bb.0: # %entry
1582 ; CHECK-NEXT: vinsertb 2, 2, 8
1583 ; CHECK-NEXT: blr
1584 ;
1585 ; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
1586 ; CHECK-BE: # %bb.0: # %entry
1587 ; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha
1588 ; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l
1589 ; CHECK-BE-NEXT: lxv 0, 0(3)
1590 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1591 ; CHECK-BE-NEXT: blr
1592 entry:
1593 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1594 ret <16 x i8> %vecins
1595 }
1597 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
1598 ; CHECK-LABEL: shuffle_vector_byte_8_7:
1599 ; CHECK: # %bb.0: # %entry
1600 ; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha
1601 ; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l
1602 ; CHECK-NEXT: lxv 0, 0(3)
1603 ; CHECK-NEXT: xxperm 34, 34, 0
1604 ; CHECK-NEXT: blr
1605 ;
1606 ; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
1607 ; CHECK-BE: # %bb.0: # %entry
1608 ; CHECK-BE-NEXT: vinsertb 2, 2, 8
1609 ; CHECK-BE-NEXT: blr
1610 entry:
1611 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1612 ret <16 x i8> %vecins
1613 }
1615 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
1616 ; CHECK-LABEL: shuffle_vector_byte_9_7:
1617 ; CHECK: # %bb.0: # %entry
1618 ; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha
1619 ; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l
1620 ; CHECK-NEXT: lxv 0, 0(3)
1621 ; CHECK-NEXT: xxperm 34, 34, 0
1622 ; CHECK-NEXT: blr
1623 ;
1624 ; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
1625 ; CHECK-BE: # %bb.0: # %entry
1626 ; CHECK-BE-NEXT: vinsertb 2, 2, 9
1627 ; CHECK-BE-NEXT: blr
1628 entry:
1629 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1630 ret <16 x i8> %vecins
1631 }
1633 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
1634 ; CHECK-LABEL: shuffle_vector_byte_10_7:
1635 ; CHECK: # %bb.0: # %entry
1636 ; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha
1637 ; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l
1638 ; CHECK-NEXT: lxv 0, 0(3)
1639 ; CHECK-NEXT: xxperm 34, 34, 0
1640 ; CHECK-NEXT: blr
1641 ;
1642 ; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
1643 ; CHECK-BE: # %bb.0: # %entry
1644 ; CHECK-BE-NEXT: vinsertb 2, 2, 10
1645 ; CHECK-BE-NEXT: blr
1646 entry:
1647 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
1648 ret <16 x i8> %vecins
1649 }
1651 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
1652 ; CHECK-LABEL: shuffle_vector_byte_11_8:
1653 ; CHECK: # %bb.0: # %entry
1654 ; CHECK-NEXT: vinsertb 2, 2, 4
1655 ; CHECK-NEXT: blr
1656 ;
1657 ; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
1658 ; CHECK-BE: # %bb.0: # %entry
1659 ; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha
1660 ; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l
1661 ; CHECK-BE-NEXT: lxv 0, 0(3)
1662 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1663 ; CHECK-BE-NEXT: blr
1664 entry:
1665 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
1666 ret <16 x i8> %vecins
1667 }
1669 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
1670 ; CHECK-LABEL: shuffle_vector_byte_12_8:
1671 ; CHECK: # %bb.0: # %entry
1672 ; CHECK-NEXT: vinsertb 2, 2, 3
1673 ; CHECK-NEXT: blr
1674 ;
1675 ; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
1676 ; CHECK-BE: # %bb.0: # %entry
1677 ; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha
1678 ; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l
1679 ; CHECK-BE-NEXT: lxv 0, 0(3)
1680 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1681 ; CHECK-BE-NEXT: blr
1682 entry:
1683 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
1684 ret <16 x i8> %vecins
1685 }
1687 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
1688 ; CHECK-LABEL: shuffle_vector_byte_13_7:
1689 ; CHECK: # %bb.0: # %entry
1690 ; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha
1691 ; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l
1692 ; CHECK-NEXT: lxv 0, 0(3)
1693 ; CHECK-NEXT: xxperm 34, 34, 0
1694 ; CHECK-NEXT: blr
1695 ;
1696 ; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
1697 ; CHECK-BE: # %bb.0: # %entry
1698 ; CHECK-BE-NEXT: vinsertb 2, 2, 13
1699 ; CHECK-BE-NEXT: blr
1700 entry:
1701 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
1702 ret <16 x i8> %vecins
1703 }
1705 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
1706 ; CHECK-LABEL: shuffle_vector_byte_14_7:
1707 ; CHECK: # %bb.0: # %entry
1708 ; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha
1709 ; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l
1710 ; CHECK-NEXT: lxv 0, 0(3)
1711 ; CHECK-NEXT: xxperm 34, 34, 0
1712 ; CHECK-NEXT: blr
1713 ;
1714 ; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
1715 ; CHECK-BE: # %bb.0: # %entry
1716 ; CHECK-BE-NEXT: vinsertb 2, 2, 14
1717 ; CHECK-BE-NEXT: blr
1718 entry:
1719 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
1720 ret <16 x i8> %vecins
1721 }
1723 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
1724 ; CHECK-LABEL: shuffle_vector_byte_15_8:
1725 ; CHECK: # %bb.0: # %entry
1726 ; CHECK-NEXT: vinsertb 2, 2, 0
1727 ; CHECK-NEXT: blr
1728 ;
1729 ; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
1730 ; CHECK-BE: # %bb.0: # %entry
1731 ; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha
1732 ; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l
1733 ; CHECK-BE-NEXT: lxv 0, 0(3)
1734 ; CHECK-BE-NEXT: xxperm 34, 34, 0
1735 ; CHECK-BE-NEXT: blr
1736 entry:
1737 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
1738 ret <16 x i8> %vecins
1739 }
1741 ; The following tests try to insert one halfword element into the vector. We
1742 ; should always be using the 'vinserth' instruction.
1743 define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) {
1744 ; CHECK-OPT-LABEL: insert_halfword_0:
1745 ; CHECK-OPT: # %bb.0: # %entry
1746 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1747 ; CHECK-OPT-NEXT: vinserth 2, 3, 14
1748 ; CHECK-OPT-NEXT: blr
1749 ;
1750 ; CHECK-O0-LABEL: insert_halfword_0:
1751 ; CHECK-O0: # %bb.0: # %entry
1752 ; CHECK-O0-NEXT: mr 3, 5
1753 ; CHECK-O0-NEXT: mtfprwz 0, 3
1754 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1755 ; CHECK-O0-NEXT: vinserth 2, 3, 14
1756 ; CHECK-O0-NEXT: blr
1757 ;
1758 ; CHECK-BE-OPT-LABEL: insert_halfword_0:
1759 ; CHECK-BE-OPT: # %bb.0: # %entry
1760 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1761 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 0
1762 ; CHECK-BE-OPT-NEXT: blr
1763 ;
1764 ; CHECK-BE-O0-LABEL: insert_halfword_0:
1765 ; CHECK-BE-O0: # %bb.0: # %entry
1766 ; CHECK-BE-O0-NEXT: mr 3, 5
1767 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1768 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
1769 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 0
1770 ; CHECK-BE-O0-NEXT: blr
1771 entry:
1772 %vecins = insertelement <8 x i16> %a, i16 %b, i32 0
1773 ret <8 x i16> %vecins
1774 }
1776 define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) {
1777 ; CHECK-OPT-LABEL: insert_halfword_1:
1778 ; CHECK-OPT: # %bb.0: # %entry
1779 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1780 ; CHECK-OPT-NEXT: vinserth 2, 3, 12
1781 ; CHECK-OPT-NEXT: blr
1782 ;
1783 ; CHECK-O0-LABEL: insert_halfword_1:
1784 ; CHECK-O0: # %bb.0: # %entry
1785 ; CHECK-O0-NEXT: mr 3, 5
1786 ; CHECK-O0-NEXT: mtfprwz 0, 3
1787 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1788 ; CHECK-O0-NEXT: vinserth 2, 3, 12
1789 ; CHECK-O0-NEXT: blr
1790 ;
1791 ; CHECK-BE-OPT-LABEL: insert_halfword_1:
1792 ; CHECK-BE-OPT: # %bb.0: # %entry
1793 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1794 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 2
1795 ; CHECK-BE-OPT-NEXT: blr
1796 ;
1797 ; CHECK-BE-O0-LABEL: insert_halfword_1:
1798 ; CHECK-BE-O0: # %bb.0: # %entry
1799 ; CHECK-BE-O0-NEXT: mr 3, 5
1800 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1801 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
1802 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 2
1803 ; CHECK-BE-O0-NEXT: blr
1804 entry:
1805 %vecins = insertelement <8 x i16> %a, i16 %b, i32 1
1806 ret <8 x i16> %vecins
1807 }
1809 define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) {
1810 ; CHECK-OPT-LABEL: insert_halfword_2:
1811 ; CHECK-OPT: # %bb.0: # %entry
1812 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1813 ; CHECK-OPT-NEXT: vinserth 2, 3, 10
1814 ; CHECK-OPT-NEXT: blr
1815 ;
1816 ; CHECK-O0-LABEL: insert_halfword_2:
1817 ; CHECK-O0: # %bb.0: # %entry
1818 ; CHECK-O0-NEXT: mr 3, 5
1819 ; CHECK-O0-NEXT: mtfprwz 0, 3
1820 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1821 ; CHECK-O0-NEXT: vinserth 2, 3, 10
1822 ; CHECK-O0-NEXT: blr
1823 ;
1824 ; CHECK-BE-OPT-LABEL: insert_halfword_2:
1825 ; CHECK-BE-OPT: # %bb.0: # %entry
1826 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1827 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 4
1828 ; CHECK-BE-OPT-NEXT: blr
1829 ;
1830 ; CHECK-BE-O0-LABEL: insert_halfword_2:
1831 ; CHECK-BE-O0: # %bb.0: # %entry
1832 ; CHECK-BE-O0-NEXT: mr 3, 5
1833 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1834 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
1835 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 4
1836 ; CHECK-BE-O0-NEXT: blr
1837 entry:
1838 %vecins = insertelement <8 x i16> %a, i16 %b, i32 2
1839 ret <8 x i16> %vecins
1840 }
1842 define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) {
1843 ; CHECK-OPT-LABEL: insert_halfword_3:
1844 ; CHECK-OPT: # %bb.0: # %entry
1845 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1846 ; CHECK-OPT-NEXT: vinserth 2, 3, 8
1847 ; CHECK-OPT-NEXT: blr
1848 ;
1849 ; CHECK-O0-LABEL: insert_halfword_3:
1850 ; CHECK-O0: # %bb.0: # %entry
1851 ; CHECK-O0-NEXT: mr 3, 5
1852 ; CHECK-O0-NEXT: mtfprwz 0, 3
1853 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1854 ; CHECK-O0-NEXT: vinserth 2, 3, 8
1855 ; CHECK-O0-NEXT: blr
1856 ;
1857 ; CHECK-BE-OPT-LABEL: insert_halfword_3:
1858 ; CHECK-BE-OPT: # %bb.0: # %entry
1859 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1860 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 6
1861 ; CHECK-BE-OPT-NEXT: blr
1862 ;
1863 ; CHECK-BE-O0-LABEL: insert_halfword_3:
1864 ; CHECK-BE-O0: # %bb.0: # %entry
1865 ; CHECK-BE-O0-NEXT: mr 3, 5
1866 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1867 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
1868 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 6
1869 ; CHECK-BE-O0-NEXT: blr
1870 entry:
1871 %vecins = insertelement <8 x i16> %a, i16 %b, i32 3
1872 ret <8 x i16> %vecins
1873 }
1875 define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) {
1876 ; CHECK-OPT-LABEL: insert_halfword_4:
1877 ; CHECK-OPT: # %bb.0: # %entry
1878 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1879 ; CHECK-OPT-NEXT: vinserth 2, 3, 6
1880 ; CHECK-OPT-NEXT: blr
1881 ;
1882 ; CHECK-O0-LABEL: insert_halfword_4:
1883 ; CHECK-O0: # %bb.0: # %entry
1884 ; CHECK-O0-NEXT: mr 3, 5
1885 ; CHECK-O0-NEXT: mtfprwz 0, 3
1886 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1887 ; CHECK-O0-NEXT: vinserth 2, 3, 6
1888 ; CHECK-O0-NEXT: blr
1889 ;
1890 ; CHECK-BE-OPT-LABEL: insert_halfword_4:
1891 ; CHECK-BE-OPT: # %bb.0: # %entry
1892 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1893 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 8
1894 ; CHECK-BE-OPT-NEXT: blr
1895 ;
1896 ; CHECK-BE-O0-LABEL: insert_halfword_4:
1897 ; CHECK-BE-O0: # %bb.0: # %entry
1898 ; CHECK-BE-O0-NEXT: mr 3, 5
1899 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1900 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
1901 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 8
1902 ; CHECK-BE-O0-NEXT: blr
1903 entry:
1904 %vecins = insertelement <8 x i16> %a, i16 %b, i32 4
1905 ret <8 x i16> %vecins
1906 }
1908 define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) {
1909 ; CHECK-OPT-LABEL: insert_halfword_5:
1910 ; CHECK-OPT: # %bb.0: # %entry
1911 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1912 ; CHECK-OPT-NEXT: vinserth 2, 3, 4
1913 ; CHECK-OPT-NEXT: blr
1914 ;
1915 ; CHECK-O0-LABEL: insert_halfword_5:
1916 ; CHECK-O0: # %bb.0: # %entry
1917 ; CHECK-O0-NEXT: mr 3, 5
1918 ; CHECK-O0-NEXT: mtfprwz 0, 3
1919 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1920 ; CHECK-O0-NEXT: vinserth 2, 3, 4
1921 ; CHECK-O0-NEXT: blr
1922 ;
1923 ; CHECK-BE-OPT-LABEL: insert_halfword_5:
1924 ; CHECK-BE-OPT: # %bb.0: # %entry
1925 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1926 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 10
1927 ; CHECK-BE-OPT-NEXT: blr
1928 ;
1929 ; CHECK-BE-O0-LABEL: insert_halfword_5:
1930 ; CHECK-BE-O0: # %bb.0: # %entry
1931 ; CHECK-BE-O0-NEXT: mr 3, 5
1932 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1933 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
1934 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 10
1935 ; CHECK-BE-O0-NEXT: blr
1936 entry:
1937 %vecins = insertelement <8 x i16> %a, i16 %b, i32 5
1938 ret <8 x i16> %vecins
1939 }
1941 define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) {
1942 ; CHECK-OPT-LABEL: insert_halfword_6:
1943 ; CHECK-OPT: # %bb.0: # %entry
1944 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1945 ; CHECK-OPT-NEXT: vinserth 2, 3, 2
1946 ; CHECK-OPT-NEXT: blr
1947 ;
1948 ; CHECK-O0-LABEL: insert_halfword_6:
1949 ; CHECK-O0: # %bb.0: # %entry
1950 ; CHECK-O0-NEXT: mr 3, 5
1951 ; CHECK-O0-NEXT: mtfprwz 0, 3
1952 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1953 ; CHECK-O0-NEXT: vinserth 2, 3, 2
1954 ; CHECK-O0-NEXT: blr
1955 ;
1956 ; CHECK-BE-OPT-LABEL: insert_halfword_6:
1957 ; CHECK-BE-OPT: # %bb.0: # %entry
1958 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1959 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 12
1960 ; CHECK-BE-OPT-NEXT: blr
1961 ;
1962 ; CHECK-BE-O0-LABEL: insert_halfword_6:
1963 ; CHECK-BE-O0: # %bb.0: # %entry
1964 ; CHECK-BE-O0-NEXT: mr 3, 5
1965 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1966 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
1967 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 12
1968 ; CHECK-BE-O0-NEXT: blr
1969 entry:
1970 %vecins = insertelement <8 x i16> %a, i16 %b, i32 6
1971 ret <8 x i16> %vecins
1972 }
1974 define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) {
1975 ; CHECK-OPT-LABEL: insert_halfword_7:
1976 ; CHECK-OPT: # %bb.0: # %entry
1977 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
1978 ; CHECK-OPT-NEXT: vinserth 2, 3, 0
1979 ; CHECK-OPT-NEXT: blr
1980 ;
1981 ; CHECK-O0-LABEL: insert_halfword_7:
1982 ; CHECK-O0: # %bb.0: # %entry
1983 ; CHECK-O0-NEXT: mr 3, 5
1984 ; CHECK-O0-NEXT: mtfprwz 0, 3
1985 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
1986 ; CHECK-O0-NEXT: vinserth 2, 3, 0
1987 ; CHECK-O0-NEXT: blr
1988 ;
1989 ; CHECK-BE-OPT-LABEL: insert_halfword_7:
1990 ; CHECK-BE-OPT: # %bb.0: # %entry
1991 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
1992 ; CHECK-BE-OPT-NEXT: vinserth 2, 3, 14
1993 ; CHECK-BE-OPT-NEXT: blr
1994 ;
1995 ; CHECK-BE-O0-LABEL: insert_halfword_7:
1996 ; CHECK-BE-O0: # %bb.0: # %entry
1997 ; CHECK-BE-O0-NEXT: mr 3, 5
1998 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
1999 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2000 ; CHECK-BE-O0-NEXT: vinserth 2, 3, 14
2001 ; CHECK-BE-O0-NEXT: blr
2002 entry:
2003 %vecins = insertelement <8 x i16> %a, i16 %b, i32 7
2004 ret <8 x i16> %vecins
2005 }
2007 ; The following tests try to insert one byte element into the vector. We
2008 ; should always be using the 'vinsertb' instruction.
2009 define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) {
2010 ; CHECK-OPT-LABEL: insert_byte_0:
2011 ; CHECK-OPT: # %bb.0: # %entry
2012 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2013 ; CHECK-OPT-NEXT: vinsertb 2, 3, 15
2014 ; CHECK-OPT-NEXT: blr
2015 ;
2016 ; CHECK-O0-LABEL: insert_byte_0:
2017 ; CHECK-O0: # %bb.0: # %entry
2018 ; CHECK-O0-NEXT: mr 3, 5
2019 ; CHECK-O0-NEXT: mtfprwz 0, 3
2020 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2021 ; CHECK-O0-NEXT: vinsertb 2, 3, 15
2022 ; CHECK-O0-NEXT: blr
2023 ;
2024 ; CHECK-BE-OPT-LABEL: insert_byte_0:
2025 ; CHECK-BE-OPT: # %bb.0: # %entry
2026 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2027 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 0
2028 ; CHECK-BE-OPT-NEXT: blr
2029 ;
2030 ; CHECK-BE-O0-LABEL: insert_byte_0:
2031 ; CHECK-BE-O0: # %bb.0: # %entry
2032 ; CHECK-BE-O0-NEXT: mr 3, 5
2033 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2034 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2035 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 0
2036 ; CHECK-BE-O0-NEXT: blr
2037 entry:
2038 %vecins = insertelement <16 x i8> %a, i8 %b, i32 0
2039 ret <16 x i8> %vecins
2040 }
2042 define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) {
2043 ; CHECK-OPT-LABEL: insert_byte_1:
2044 ; CHECK-OPT: # %bb.0: # %entry
2045 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2046 ; CHECK-OPT-NEXT: vinsertb 2, 3, 14
2047 ; CHECK-OPT-NEXT: blr
2048 ;
2049 ; CHECK-O0-LABEL: insert_byte_1:
2050 ; CHECK-O0: # %bb.0: # %entry
2051 ; CHECK-O0-NEXT: mr 3, 5
2052 ; CHECK-O0-NEXT: mtfprwz 0, 3
2053 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2054 ; CHECK-O0-NEXT: vinsertb 2, 3, 14
2055 ; CHECK-O0-NEXT: blr
2056 ;
2057 ; CHECK-BE-OPT-LABEL: insert_byte_1:
2058 ; CHECK-BE-OPT: # %bb.0: # %entry
2059 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2060 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 1
2061 ; CHECK-BE-OPT-NEXT: blr
2062 ;
2063 ; CHECK-BE-O0-LABEL: insert_byte_1:
2064 ; CHECK-BE-O0: # %bb.0: # %entry
2065 ; CHECK-BE-O0-NEXT: mr 3, 5
2066 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2067 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2068 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 1
2069 ; CHECK-BE-O0-NEXT: blr
2070 entry:
2071 %vecins = insertelement <16 x i8> %a, i8 %b, i32 1
2072 ret <16 x i8> %vecins
2073 }
2075 define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) {
2076 ; CHECK-OPT-LABEL: insert_byte_2:
2077 ; CHECK-OPT: # %bb.0: # %entry
2078 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2079 ; CHECK-OPT-NEXT: vinsertb 2, 3, 13
2080 ; CHECK-OPT-NEXT: blr
2081 ;
2082 ; CHECK-O0-LABEL: insert_byte_2:
2083 ; CHECK-O0: # %bb.0: # %entry
2084 ; CHECK-O0-NEXT: mr 3, 5
2085 ; CHECK-O0-NEXT: mtfprwz 0, 3
2086 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2087 ; CHECK-O0-NEXT: vinsertb 2, 3, 13
2088 ; CHECK-O0-NEXT: blr
2089 ;
2090 ; CHECK-BE-OPT-LABEL: insert_byte_2:
2091 ; CHECK-BE-OPT: # %bb.0: # %entry
2092 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2093 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 2
2094 ; CHECK-BE-OPT-NEXT: blr
2095 ;
2096 ; CHECK-BE-O0-LABEL: insert_byte_2:
2097 ; CHECK-BE-O0: # %bb.0: # %entry
2098 ; CHECK-BE-O0-NEXT: mr 3, 5
2099 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2100 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2101 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 2
2102 ; CHECK-BE-O0-NEXT: blr
2103 entry:
2104 %vecins = insertelement <16 x i8> %a, i8 %b, i32 2
2105 ret <16 x i8> %vecins
2106 }
2108 define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) {
2109 ; CHECK-OPT-LABEL: insert_byte_3:
2110 ; CHECK-OPT: # %bb.0: # %entry
2111 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2112 ; CHECK-OPT-NEXT: vinsertb 2, 3, 12
2113 ; CHECK-OPT-NEXT: blr
2114 ;
2115 ; CHECK-O0-LABEL: insert_byte_3:
2116 ; CHECK-O0: # %bb.0: # %entry
2117 ; CHECK-O0-NEXT: mr 3, 5
2118 ; CHECK-O0-NEXT: mtfprwz 0, 3
2119 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2120 ; CHECK-O0-NEXT: vinsertb 2, 3, 12
2121 ; CHECK-O0-NEXT: blr
2122 ;
2123 ; CHECK-BE-OPT-LABEL: insert_byte_3:
2124 ; CHECK-BE-OPT: # %bb.0: # %entry
2125 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2126 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 3
2127 ; CHECK-BE-OPT-NEXT: blr
2128 ;
2129 ; CHECK-BE-O0-LABEL: insert_byte_3:
2130 ; CHECK-BE-O0: # %bb.0: # %entry
2131 ; CHECK-BE-O0-NEXT: mr 3, 5
2132 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2133 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2134 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 3
2135 ; CHECK-BE-O0-NEXT: blr
2136 entry:
2137 %vecins = insertelement <16 x i8> %a, i8 %b, i32 3
2138 ret <16 x i8> %vecins
2139 }
2141 define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) {
2142 ; CHECK-OPT-LABEL: insert_byte_4:
2143 ; CHECK-OPT: # %bb.0: # %entry
2144 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2145 ; CHECK-OPT-NEXT: vinsertb 2, 3, 11
2146 ; CHECK-OPT-NEXT: blr
2147 ;
2148 ; CHECK-O0-LABEL: insert_byte_4:
2149 ; CHECK-O0: # %bb.0: # %entry
2150 ; CHECK-O0-NEXT: mr 3, 5
2151 ; CHECK-O0-NEXT: mtfprwz 0, 3
2152 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2153 ; CHECK-O0-NEXT: vinsertb 2, 3, 11
2154 ; CHECK-O0-NEXT: blr
2155 ;
2156 ; CHECK-BE-OPT-LABEL: insert_byte_4:
2157 ; CHECK-BE-OPT: # %bb.0: # %entry
2158 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2159 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 4
2160 ; CHECK-BE-OPT-NEXT: blr
2161 ;
2162 ; CHECK-BE-O0-LABEL: insert_byte_4:
2163 ; CHECK-BE-O0: # %bb.0: # %entry
2164 ; CHECK-BE-O0-NEXT: mr 3, 5
2165 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2166 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2167 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 4
2168 ; CHECK-BE-O0-NEXT: blr
2169 entry:
2170 %vecins = insertelement <16 x i8> %a, i8 %b, i32 4
2171 ret <16 x i8> %vecins
2172 }
2174 define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) {
2175 ; CHECK-OPT-LABEL: insert_byte_5:
2176 ; CHECK-OPT: # %bb.0: # %entry
2177 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2178 ; CHECK-OPT-NEXT: vinsertb 2, 3, 10
2179 ; CHECK-OPT-NEXT: blr
2180 ;
2181 ; CHECK-O0-LABEL: insert_byte_5:
2182 ; CHECK-O0: # %bb.0: # %entry
2183 ; CHECK-O0-NEXT: mr 3, 5
2184 ; CHECK-O0-NEXT: mtfprwz 0, 3
2185 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2186 ; CHECK-O0-NEXT: vinsertb 2, 3, 10
2187 ; CHECK-O0-NEXT: blr
2188 ;
2189 ; CHECK-BE-OPT-LABEL: insert_byte_5:
2190 ; CHECK-BE-OPT: # %bb.0: # %entry
2191 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2192 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 5
2193 ; CHECK-BE-OPT-NEXT: blr
2194 ;
2195 ; CHECK-BE-O0-LABEL: insert_byte_5:
2196 ; CHECK-BE-O0: # %bb.0: # %entry
2197 ; CHECK-BE-O0-NEXT: mr 3, 5
2198 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2199 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2200 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 5
2201 ; CHECK-BE-O0-NEXT: blr
2202 entry:
2203 %vecins = insertelement <16 x i8> %a, i8 %b, i32 5
2204 ret <16 x i8> %vecins
2205 }
2207 define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) {
2208 ; CHECK-OPT-LABEL: insert_byte_6:
2209 ; CHECK-OPT: # %bb.0: # %entry
2210 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2211 ; CHECK-OPT-NEXT: vinsertb 2, 3, 9
2212 ; CHECK-OPT-NEXT: blr
2213 ;
2214 ; CHECK-O0-LABEL: insert_byte_6:
2215 ; CHECK-O0: # %bb.0: # %entry
2216 ; CHECK-O0-NEXT: mr 3, 5
2217 ; CHECK-O0-NEXT: mtfprwz 0, 3
2218 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2219 ; CHECK-O0-NEXT: vinsertb 2, 3, 9
2220 ; CHECK-O0-NEXT: blr
2221 ;
2222 ; CHECK-BE-OPT-LABEL: insert_byte_6:
2223 ; CHECK-BE-OPT: # %bb.0: # %entry
2224 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2225 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 6
2226 ; CHECK-BE-OPT-NEXT: blr
2227 ;
2228 ; CHECK-BE-O0-LABEL: insert_byte_6:
2229 ; CHECK-BE-O0: # %bb.0: # %entry
2230 ; CHECK-BE-O0-NEXT: mr 3, 5
2231 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2232 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2233 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 6
2234 ; CHECK-BE-O0-NEXT: blr
2235 entry:
2236 %vecins = insertelement <16 x i8> %a, i8 %b, i32 6
2237 ret <16 x i8> %vecins
2238 }
2240 define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) {
2241 ; CHECK-OPT-LABEL: insert_byte_7:
2242 ; CHECK-OPT: # %bb.0: # %entry
2243 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2244 ; CHECK-OPT-NEXT: vinsertb 2, 3, 8
2245 ; CHECK-OPT-NEXT: blr
2246 ;
2247 ; CHECK-O0-LABEL: insert_byte_7:
2248 ; CHECK-O0: # %bb.0: # %entry
2249 ; CHECK-O0-NEXT: mr 3, 5
2250 ; CHECK-O0-NEXT: mtfprwz 0, 3
2251 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2252 ; CHECK-O0-NEXT: vinsertb 2, 3, 8
2253 ; CHECK-O0-NEXT: blr
2254 ;
2255 ; CHECK-BE-OPT-LABEL: insert_byte_7:
2256 ; CHECK-BE-OPT: # %bb.0: # %entry
2257 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2258 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 7
2259 ; CHECK-BE-OPT-NEXT: blr
2260 ;
2261 ; CHECK-BE-O0-LABEL: insert_byte_7:
2262 ; CHECK-BE-O0: # %bb.0: # %entry
2263 ; CHECK-BE-O0-NEXT: mr 3, 5
2264 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2265 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2266 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 7
2267 ; CHECK-BE-O0-NEXT: blr
2268 entry:
2269 %vecins = insertelement <16 x i8> %a, i8 %b, i32 7
2270 ret <16 x i8> %vecins
2271 }
2273 define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) {
2274 ; CHECK-OPT-LABEL: insert_byte_8:
2275 ; CHECK-OPT: # %bb.0: # %entry
2276 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2277 ; CHECK-OPT-NEXT: vinsertb 2, 3, 7
2278 ; CHECK-OPT-NEXT: blr
2279 ;
2280 ; CHECK-O0-LABEL: insert_byte_8:
2281 ; CHECK-O0: # %bb.0: # %entry
2282 ; CHECK-O0-NEXT: mr 3, 5
2283 ; CHECK-O0-NEXT: mtfprwz 0, 3
2284 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2285 ; CHECK-O0-NEXT: vinsertb 2, 3, 7
2286 ; CHECK-O0-NEXT: blr
2287 ;
2288 ; CHECK-BE-OPT-LABEL: insert_byte_8:
2289 ; CHECK-BE-OPT: # %bb.0: # %entry
2290 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2291 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 8
2292 ; CHECK-BE-OPT-NEXT: blr
2293 ;
2294 ; CHECK-BE-O0-LABEL: insert_byte_8:
2295 ; CHECK-BE-O0: # %bb.0: # %entry
2296 ; CHECK-BE-O0-NEXT: mr 3, 5
2297 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2298 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2299 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 8
2300 ; CHECK-BE-O0-NEXT: blr
2301 entry:
2302 %vecins = insertelement <16 x i8> %a, i8 %b, i32 8
2303 ret <16 x i8> %vecins
2304 }
2306 define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) {
2307 ; CHECK-OPT-LABEL: insert_byte_9:
2308 ; CHECK-OPT: # %bb.0: # %entry
2309 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2310 ; CHECK-OPT-NEXT: vinsertb 2, 3, 6
2311 ; CHECK-OPT-NEXT: blr
2312 ;
2313 ; CHECK-O0-LABEL: insert_byte_9:
2314 ; CHECK-O0: # %bb.0: # %entry
2315 ; CHECK-O0-NEXT: mr 3, 5
2316 ; CHECK-O0-NEXT: mtfprwz 0, 3
2317 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2318 ; CHECK-O0-NEXT: vinsertb 2, 3, 6
2319 ; CHECK-O0-NEXT: blr
2320 ;
2321 ; CHECK-BE-OPT-LABEL: insert_byte_9:
2322 ; CHECK-BE-OPT: # %bb.0: # %entry
2323 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2324 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 9
2325 ; CHECK-BE-OPT-NEXT: blr
2326 ;
2327 ; CHECK-BE-O0-LABEL: insert_byte_9:
2328 ; CHECK-BE-O0: # %bb.0: # %entry
2329 ; CHECK-BE-O0-NEXT: mr 3, 5
2330 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2331 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2332 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 9
2333 ; CHECK-BE-O0-NEXT: blr
2334 entry:
2335 %vecins = insertelement <16 x i8> %a, i8 %b, i32 9
2336 ret <16 x i8> %vecins
2337 }
2339 define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) {
2340 ; CHECK-OPT-LABEL: insert_byte_10:
2341 ; CHECK-OPT: # %bb.0: # %entry
2342 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2343 ; CHECK-OPT-NEXT: vinsertb 2, 3, 5
2344 ; CHECK-OPT-NEXT: blr
2345 ;
2346 ; CHECK-O0-LABEL: insert_byte_10:
2347 ; CHECK-O0: # %bb.0: # %entry
2348 ; CHECK-O0-NEXT: mr 3, 5
2349 ; CHECK-O0-NEXT: mtfprwz 0, 3
2350 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2351 ; CHECK-O0-NEXT: vinsertb 2, 3, 5
2352 ; CHECK-O0-NEXT: blr
2353 ;
2354 ; CHECK-BE-OPT-LABEL: insert_byte_10:
2355 ; CHECK-BE-OPT: # %bb.0: # %entry
2356 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2357 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 10
2358 ; CHECK-BE-OPT-NEXT: blr
2359 ;
2360 ; CHECK-BE-O0-LABEL: insert_byte_10:
2361 ; CHECK-BE-O0: # %bb.0: # %entry
2362 ; CHECK-BE-O0-NEXT: mr 3, 5
2363 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2364 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2365 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 10
2366 ; CHECK-BE-O0-NEXT: blr
2367 entry:
2368 %vecins = insertelement <16 x i8> %a, i8 %b, i32 10
2369 ret <16 x i8> %vecins
2370 }
2372 define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) {
2373 ; CHECK-OPT-LABEL: insert_byte_11:
2374 ; CHECK-OPT: # %bb.0: # %entry
2375 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2376 ; CHECK-OPT-NEXT: vinsertb 2, 3, 4
2377 ; CHECK-OPT-NEXT: blr
2378 ;
2379 ; CHECK-O0-LABEL: insert_byte_11:
2380 ; CHECK-O0: # %bb.0: # %entry
2381 ; CHECK-O0-NEXT: mr 3, 5
2382 ; CHECK-O0-NEXT: mtfprwz 0, 3
2383 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2384 ; CHECK-O0-NEXT: vinsertb 2, 3, 4
2385 ; CHECK-O0-NEXT: blr
2386 ;
2387 ; CHECK-BE-OPT-LABEL: insert_byte_11:
2388 ; CHECK-BE-OPT: # %bb.0: # %entry
2389 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2390 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 11
2391 ; CHECK-BE-OPT-NEXT: blr
2392 ;
2393 ; CHECK-BE-O0-LABEL: insert_byte_11:
2394 ; CHECK-BE-O0: # %bb.0: # %entry
2395 ; CHECK-BE-O0-NEXT: mr 3, 5
2396 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2397 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2398 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 11
2399 ; CHECK-BE-O0-NEXT: blr
2400 entry:
2401 %vecins = insertelement <16 x i8> %a, i8 %b, i32 11
2402 ret <16 x i8> %vecins
2403 }
2405 define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) {
2406 ; CHECK-OPT-LABEL: insert_byte_12:
2407 ; CHECK-OPT: # %bb.0: # %entry
2408 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2409 ; CHECK-OPT-NEXT: vinsertb 2, 3, 3
2410 ; CHECK-OPT-NEXT: blr
2411 ;
2412 ; CHECK-O0-LABEL: insert_byte_12:
2413 ; CHECK-O0: # %bb.0: # %entry
2414 ; CHECK-O0-NEXT: mr 3, 5
2415 ; CHECK-O0-NEXT: mtfprwz 0, 3
2416 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2417 ; CHECK-O0-NEXT: vinsertb 2, 3, 3
2418 ; CHECK-O0-NEXT: blr
2419 ;
2420 ; CHECK-BE-OPT-LABEL: insert_byte_12:
2421 ; CHECK-BE-OPT: # %bb.0: # %entry
2422 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2423 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 12
2424 ; CHECK-BE-OPT-NEXT: blr
2425 ;
2426 ; CHECK-BE-O0-LABEL: insert_byte_12:
2427 ; CHECK-BE-O0: # %bb.0: # %entry
2428 ; CHECK-BE-O0-NEXT: mr 3, 5
2429 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2430 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2431 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 12
2432 ; CHECK-BE-O0-NEXT: blr
2433 entry:
2434 %vecins = insertelement <16 x i8> %a, i8 %b, i32 12
2435 ret <16 x i8> %vecins
2436 }
2438 define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) {
2439 ; CHECK-OPT-LABEL: insert_byte_13:
2440 ; CHECK-OPT: # %bb.0: # %entry
2441 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2442 ; CHECK-OPT-NEXT: vinsertb 2, 3, 2
2443 ; CHECK-OPT-NEXT: blr
2444 ;
2445 ; CHECK-O0-LABEL: insert_byte_13:
2446 ; CHECK-O0: # %bb.0: # %entry
2447 ; CHECK-O0-NEXT: mr 3, 5
2448 ; CHECK-O0-NEXT: mtfprwz 0, 3
2449 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2450 ; CHECK-O0-NEXT: vinsertb 2, 3, 2
2451 ; CHECK-O0-NEXT: blr
2452 ;
2453 ; CHECK-BE-OPT-LABEL: insert_byte_13:
2454 ; CHECK-BE-OPT: # %bb.0: # %entry
2455 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2456 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 13
2457 ; CHECK-BE-OPT-NEXT: blr
2458 ;
2459 ; CHECK-BE-O0-LABEL: insert_byte_13:
2460 ; CHECK-BE-O0: # %bb.0: # %entry
2461 ; CHECK-BE-O0-NEXT: mr 3, 5
2462 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2463 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2464 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 13
2465 ; CHECK-BE-O0-NEXT: blr
2466 entry:
2467 %vecins = insertelement <16 x i8> %a, i8 %b, i32 13
2468 ret <16 x i8> %vecins
2469 }
2471 define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) {
2472 ; CHECK-OPT-LABEL: insert_byte_14:
2473 ; CHECK-OPT: # %bb.0: # %entry
2474 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2475 ; CHECK-OPT-NEXT: vinsertb 2, 3, 1
2476 ; CHECK-OPT-NEXT: blr
2477 ;
2478 ; CHECK-O0-LABEL: insert_byte_14:
2479 ; CHECK-O0: # %bb.0: # %entry
2480 ; CHECK-O0-NEXT: mr 3, 5
2481 ; CHECK-O0-NEXT: mtfprwz 0, 3
2482 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2483 ; CHECK-O0-NEXT: vinsertb 2, 3, 1
2484 ; CHECK-O0-NEXT: blr
2485 ;
2486 ; CHECK-BE-OPT-LABEL: insert_byte_14:
2487 ; CHECK-BE-OPT: # %bb.0: # %entry
2488 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2489 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 14
2490 ; CHECK-BE-OPT-NEXT: blr
2491 ;
2492 ; CHECK-BE-O0-LABEL: insert_byte_14:
2493 ; CHECK-BE-O0: # %bb.0: # %entry
2494 ; CHECK-BE-O0-NEXT: mr 3, 5
2495 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2496 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2497 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 14
2498 ; CHECK-BE-O0-NEXT: blr
2499 entry:
2500 %vecins = insertelement <16 x i8> %a, i8 %b, i32 14
2501 ret <16 x i8> %vecins
2502 }
2504 define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) {
2505 ; CHECK-OPT-LABEL: insert_byte_15:
2506 ; CHECK-OPT: # %bb.0: # %entry
2507 ; CHECK-OPT-NEXT: mtvsrwz 35, 5
2508 ; CHECK-OPT-NEXT: vinsertb 2, 3, 0
2509 ; CHECK-OPT-NEXT: blr
2510 ;
2511 ; CHECK-O0-LABEL: insert_byte_15:
2512 ; CHECK-O0: # %bb.0: # %entry
2513 ; CHECK-O0-NEXT: mr 3, 5
2514 ; CHECK-O0-NEXT: mtfprwz 0, 3
2515 ; CHECK-O0-NEXT: xscpsgndp 35, 0, 0
2516 ; CHECK-O0-NEXT: vinsertb 2, 3, 0
2517 ; CHECK-O0-NEXT: blr
2518 ;
2519 ; CHECK-BE-OPT-LABEL: insert_byte_15:
2520 ; CHECK-BE-OPT: # %bb.0: # %entry
2521 ; CHECK-BE-OPT-NEXT: mtvsrwz 35, 5
2522 ; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 15
2523 ; CHECK-BE-OPT-NEXT: blr
2524 ;
2525 ; CHECK-BE-O0-LABEL: insert_byte_15:
2526 ; CHECK-BE-O0: # %bb.0: # %entry
2527 ; CHECK-BE-O0-NEXT: mr 3, 5
2528 ; CHECK-BE-O0-NEXT: mtfprwz 0, 3
2529 ; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 0
2530 ; CHECK-BE-O0-NEXT: vinsertb 2, 3, 15
2531 ; CHECK-BE-O0-NEXT: blr
2532 entry:
2533 %vecins = insertelement <16 x i8> %a, i8 %b, i32 15
2534 ret <16 x i8> %vecins
2535 }