| blob | 4bfc413a5a2aa2315f658e3c5ef977976aceabea |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
3 ; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE
4 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
5 ; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU2
7 ; single tests (identical for -mattr=+spe and -mattr=+efpu2)
9 declare float @llvm.fabs.float(float)
10 define float @test_float_abs(float %a) #0 {
11 ; CHECK-LABEL: test_float_abs:
12 ; CHECK: # %bb.0: # %entry
13 ; CHECK-NEXT: efsabs 3, 3
14 ; CHECK-NEXT: blr
15 entry:
16 %0 = tail call float @llvm.fabs.float(float %a)
17 ret float %0
18 }
20 define float @test_fnabs(float %a) #0 {
21 ; CHECK-LABEL: test_fnabs:
22 ; CHECK: # %bb.0: # %entry
23 ; CHECK-NEXT: efsnabs 3, 3
24 ; CHECK-NEXT: blr
25 entry:
26 %0 = tail call float @llvm.fabs.float(float %a)
27 %sub = fsub float -0.000000e+00, %0
28 ret float %sub
29 }
31 define float @test_fdiv(float %a, float %b) #0 {
32 ; CHECK-LABEL: test_fdiv:
33 ; CHECK: # %bb.0: # %entry
34 ; CHECK-NEXT: efsdiv 3, 3, 4
35 ; CHECK-NEXT: blr
36 entry:
37 %v = fdiv float %a, %b
38 ret float %v
40 }
42 define float @test_fmul(float %a, float %b) #0 {
43 ; CHECK-LABEL: test_fmul:
44 ; CHECK: # %bb.0: # %entry
45 ; CHECK-NEXT: efsmul 3, 3, 4
46 ; CHECK-NEXT: blr
47 entry:
48 %v = fmul float %a, %b
49 ret float %v
50 }
52 define float @test_fadd(float %a, float %b) #0 {
53 ; CHECK-LABEL: test_fadd:
54 ; CHECK: # %bb.0: # %entry
55 ; CHECK-NEXT: efsadd 3, 3, 4
56 ; CHECK-NEXT: blr
57 entry:
58 %v = fadd float %a, %b
59 ret float %v
60 }
62 define float @test_fsub(float %a, float %b) #0 {
63 ; CHECK-LABEL: test_fsub:
64 ; CHECK: # %bb.0: # %entry
65 ; CHECK-NEXT: efssub 3, 3, 4
66 ; CHECK-NEXT: blr
67 entry:
68 %v = fsub float %a, %b
69 ret float %v
70 }
72 define float @test_fneg(float %a) #0 {
73 ; CHECK-LABEL: test_fneg:
74 ; CHECK: # %bb.0: # %entry
75 ; CHECK-NEXT: efsneg 3, 3
76 ; CHECK-NEXT: blr
77 entry:
78 %v = fsub float -0.0, %a
79 ret float %v
80 }
82 define i32 @test_fcmpgt(float %a, float %b) #0 {
83 ; CHECK-LABEL: test_fcmpgt:
84 ; CHECK: # %bb.0: # %entry
85 ; CHECK-NEXT: stwu 1, -16(1)
86 ; CHECK-NEXT: efscmpgt 0, 3, 4
87 ; CHECK-NEXT: ble 0, .LBB7_2
88 ; CHECK-NEXT: # %bb.1: # %tr
89 ; CHECK-NEXT: li 3, 1
90 ; CHECK-NEXT: b .LBB7_3
91 ; CHECK-NEXT: .LBB7_2: # %fa
92 ; CHECK-NEXT: li 3, 0
93 ; CHECK-NEXT: .LBB7_3: # %ret
94 ; CHECK-NEXT: stw 3, 12(1)
95 ; CHECK-NEXT: lwz 3, 12(1)
96 ; CHECK-NEXT: addi 1, 1, 16
97 ; CHECK-NEXT: blr
98 entry:
99 %r = alloca i32, align 4
100 %c = fcmp ogt float %a, %b
101 br i1 %c, label %tr, label %fa
102 tr:
103 store i32 1, ptr %r, align 4
104 br label %ret
105 fa:
106 store i32 0, ptr %r, align 4
107 br label %ret
108 ret:
109 %0 = load i32, ptr %r, align 4
110 ret i32 %0
111 }
113 define i32 @test_fcmpugt(float %a, float %b) #0 {
114 ; CHECK-LABEL: test_fcmpugt:
115 ; CHECK: # %bb.0: # %entry
116 ; CHECK-NEXT: stwu 1, -16(1)
117 ; CHECK-NEXT: efscmpeq 0, 4, 4
118 ; CHECK-NEXT: bc 4, 1, .LBB8_4
119 ; CHECK-NEXT: # %bb.1: # %entry
120 ; CHECK-NEXT: efscmpeq 0, 3, 3
121 ; CHECK-NEXT: bc 4, 1, .LBB8_4
122 ; CHECK-NEXT: # %bb.2: # %entry
123 ; CHECK-NEXT: efscmpgt 0, 3, 4
124 ; CHECK-NEXT: bc 12, 1, .LBB8_4
125 ; CHECK-NEXT: # %bb.3: # %fa
126 ; CHECK-NEXT: li 3, 0
127 ; CHECK-NEXT: b .LBB8_5
128 ; CHECK-NEXT: .LBB8_4: # %tr
129 ; CHECK-NEXT: li 3, 1
130 ; CHECK-NEXT: .LBB8_5: # %ret
131 ; CHECK-NEXT: stw 3, 12(1)
132 ; CHECK-NEXT: lwz 3, 12(1)
133 ; CHECK-NEXT: addi 1, 1, 16
134 ; CHECK-NEXT: blr
135 entry:
136 %r = alloca i32, align 4
137 %c = fcmp ugt float %a, %b
138 br i1 %c, label %tr, label %fa
139 tr:
140 store i32 1, ptr %r, align 4
141 br label %ret
142 fa:
143 store i32 0, ptr %r, align 4
144 br label %ret
145 ret:
146 %0 = load i32, ptr %r, align 4
147 ret i32 %0
148 }
150 define i32 @test_fcmple(float %a, float %b) #0 {
151 ; CHECK-LABEL: test_fcmple:
152 ; CHECK: # %bb.0: # %entry
153 ; CHECK-NEXT: stwu 1, -16(1)
154 ; CHECK-NEXT: efscmpeq 0, 3, 3
155 ; CHECK-NEXT: bc 4, 1, .LBB9_4
156 ; CHECK-NEXT: # %bb.1: # %entry
157 ; CHECK-NEXT: efscmpeq 0, 4, 4
158 ; CHECK-NEXT: bc 4, 1, .LBB9_4
159 ; CHECK-NEXT: # %bb.2: # %entry
160 ; CHECK-NEXT: efscmpgt 0, 3, 4
161 ; CHECK-NEXT: bc 12, 1, .LBB9_4
162 ; CHECK-NEXT: # %bb.3: # %tr
163 ; CHECK-NEXT: li 3, 1
164 ; CHECK-NEXT: b .LBB9_5
165 ; CHECK-NEXT: .LBB9_4: # %fa
166 ; CHECK-NEXT: li 3, 0
167 ; CHECK-NEXT: .LBB9_5: # %ret
168 ; CHECK-NEXT: stw 3, 12(1)
169 ; CHECK-NEXT: lwz 3, 12(1)
170 ; CHECK-NEXT: addi 1, 1, 16
171 ; CHECK-NEXT: blr
172 entry:
173 %r = alloca i32, align 4
174 %c = fcmp ole float %a, %b
175 br i1 %c, label %tr, label %fa
176 tr:
177 store i32 1, ptr %r, align 4
178 br label %ret
179 fa:
180 store i32 0, ptr %r, align 4
181 br label %ret
182 ret:
183 %0 = load i32, ptr %r, align 4
184 ret i32 %0
185 }
187 define i32 @test_fcmpule(float %a, float %b) #0 {
188 ; CHECK-LABEL: test_fcmpule:
189 ; CHECK: # %bb.0: # %entry
190 ; CHECK-NEXT: stwu 1, -16(1)
191 ; CHECK-NEXT: efscmpgt 0, 3, 4
192 ; CHECK-NEXT: bgt 0, .LBB10_2
193 ; CHECK-NEXT: # %bb.1: # %tr
194 ; CHECK-NEXT: li 3, 1
195 ; CHECK-NEXT: b .LBB10_3
196 ; CHECK-NEXT: .LBB10_2: # %fa
197 ; CHECK-NEXT: li 3, 0
198 ; CHECK-NEXT: .LBB10_3: # %ret
199 ; CHECK-NEXT: stw 3, 12(1)
200 ; CHECK-NEXT: lwz 3, 12(1)
201 ; CHECK-NEXT: addi 1, 1, 16
202 ; CHECK-NEXT: blr
203 entry:
204 %r = alloca i32, align 4
205 %c = fcmp ule float %a, %b
206 br i1 %c, label %tr, label %fa
207 tr:
208 store i32 1, ptr %r, align 4
209 br label %ret
210 fa:
211 store i32 0, ptr %r, align 4
212 br label %ret
213 ret:
214 %0 = load i32, ptr %r, align 4
215 ret i32 %0
216 }
218 ; The type of comparison found in C's if (x == y)
219 define i32 @test_fcmpeq(float %a, float %b) #0 {
220 ; CHECK-LABEL: test_fcmpeq:
221 ; CHECK: # %bb.0: # %entry
222 ; CHECK-NEXT: stwu 1, -16(1)
223 ; CHECK-NEXT: efscmpeq 0, 3, 4
224 ; CHECK-NEXT: ble 0, .LBB11_2
225 ; CHECK-NEXT: # %bb.1: # %tr
226 ; CHECK-NEXT: li 3, 1
227 ; CHECK-NEXT: b .LBB11_3
228 ; CHECK-NEXT: .LBB11_2: # %fa
229 ; CHECK-NEXT: li 3, 0
230 ; CHECK-NEXT: .LBB11_3: # %ret
231 ; CHECK-NEXT: stw 3, 12(1)
232 ; CHECK-NEXT: lwz 3, 12(1)
233 ; CHECK-NEXT: addi 1, 1, 16
234 ; CHECK-NEXT: blr
235 entry:
236 %r = alloca i32, align 4
237 %c = fcmp oeq float %a, %b
238 br i1 %c, label %tr, label %fa
239 tr:
240 store i32 1, ptr %r, align 4
241 br label %ret
242 fa:
243 store i32 0, ptr %r, align 4
244 br label %ret
245 ret:
246 %0 = load i32, ptr %r, align 4
247 ret i32 %0
248 }
250 ; (un)ordered tests are expanded to une and oeq so verify
251 define i1 @test_fcmpuno(float %a, float %b) #0 {
252 ; CHECK-LABEL: test_fcmpuno:
253 ; CHECK: # %bb.0: # %entry
254 ; CHECK-NEXT: efscmpeq 0, 3, 3
255 ; CHECK-NEXT: efscmpeq 1, 4, 4
256 ; CHECK-NEXT: li 5, 1
257 ; CHECK-NEXT: crand 20, 5, 1
258 ; CHECK-NEXT: bc 12, 20, .LBB12_2
259 ; CHECK-NEXT: # %bb.1: # %entry
260 ; CHECK-NEXT: ori 3, 5, 0
261 ; CHECK-NEXT: blr
262 ; CHECK-NEXT: .LBB12_2: # %entry
263 ; CHECK-NEXT: li 3, 0
264 ; CHECK-NEXT: blr
265 entry:
266 %r = fcmp uno float %a, %b
267 ret i1 %r
268 }
270 define i1 @test_fcmpord(float %a, float %b) #0 {
271 ; CHECK-LABEL: test_fcmpord:
272 ; CHECK: # %bb.0: # %entry
273 ; CHECK-NEXT: efscmpeq 0, 4, 4
274 ; CHECK-NEXT: efscmpeq 1, 3, 3
275 ; CHECK-NEXT: li 5, 1
276 ; CHECK-NEXT: crnand 20, 5, 1
277 ; CHECK-NEXT: bc 12, 20, .LBB13_2
278 ; CHECK-NEXT: # %bb.1: # %entry
279 ; CHECK-NEXT: ori 3, 5, 0
280 ; CHECK-NEXT: blr
281 ; CHECK-NEXT: .LBB13_2: # %entry
282 ; CHECK-NEXT: li 3, 0
283 ; CHECK-NEXT: blr
284 entry:
285 %r = fcmp ord float %a, %b
286 ret i1 %r
287 }
289 define i1 @test_fcmpueq(float %a, float %b) #0 {
290 ; CHECK-LABEL: test_fcmpueq:
291 ; CHECK: # %bb.0: # %entry
292 ; CHECK-NEXT: efscmpgt 0, 3, 4
293 ; CHECK-NEXT: efscmplt 1, 3, 4
294 ; CHECK-NEXT: li 5, 1
295 ; CHECK-NEXT: cror 20, 5, 1
296 ; CHECK-NEXT: bc 12, 20, .LBB14_2
297 ; CHECK-NEXT: # %bb.1: # %entry
298 ; CHECK-NEXT: ori 3, 5, 0
299 ; CHECK-NEXT: blr
300 ; CHECK-NEXT: .LBB14_2: # %entry
301 ; CHECK-NEXT: li 3, 0
302 ; CHECK-NEXT: blr
303 entry:
304 %r = fcmp ueq float %a, %b
305 ret i1 %r
306 }
308 define i1 @test_fcmpne(float %a, float %b) #0 {
309 ; CHECK-LABEL: test_fcmpne:
310 ; CHECK: # %bb.0: # %entry
311 ; CHECK-NEXT: efscmplt 0, 3, 4
312 ; CHECK-NEXT: efscmpgt 1, 3, 4
313 ; CHECK-NEXT: li 5, 1
314 ; CHECK-NEXT: crnor 20, 5, 1
315 ; CHECK-NEXT: bc 12, 20, .LBB15_2
316 ; CHECK-NEXT: # %bb.1: # %entry
317 ; CHECK-NEXT: ori 3, 5, 0
318 ; CHECK-NEXT: blr
319 ; CHECK-NEXT: .LBB15_2: # %entry
320 ; CHECK-NEXT: li 3, 0
321 ; CHECK-NEXT: blr
322 entry:
323 %r = fcmp one float %a, %b
324 ret i1 %r
325 }
327 define i32 @test_fcmpune(float %a, float %b) #0 {
328 ; CHECK-LABEL: test_fcmpune:
329 ; CHECK: # %bb.0: # %entry
330 ; CHECK-NEXT: stwu 1, -16(1)
331 ; CHECK-NEXT: efscmpeq 0, 3, 4
332 ; CHECK-NEXT: bgt 0, .LBB16_2
333 ; CHECK-NEXT: # %bb.1: # %tr
334 ; CHECK-NEXT: li 3, 1
335 ; CHECK-NEXT: b .LBB16_3
336 ; CHECK-NEXT: .LBB16_2: # %fa
337 ; CHECK-NEXT: li 3, 0
338 ; CHECK-NEXT: .LBB16_3: # %ret
339 ; CHECK-NEXT: stw 3, 12(1)
340 ; CHECK-NEXT: lwz 3, 12(1)
341 ; CHECK-NEXT: addi 1, 1, 16
342 ; CHECK-NEXT: blr
343 entry:
344 %r = alloca i32, align 4
345 %c = fcmp une float %a, %b
346 br i1 %c, label %tr, label %fa
347 tr:
348 store i32 1, ptr %r, align 4
349 br label %ret
350 fa:
351 store i32 0, ptr %r, align 4
352 br label %ret
353 ret:
354 %0 = load i32, ptr %r, align 4
355 ret i32 %0
356 }
358 define i32 @test_fcmplt(float %a, float %b) #0 {
359 ; CHECK-LABEL: test_fcmplt:
360 ; CHECK: # %bb.0: # %entry
361 ; CHECK-NEXT: stwu 1, -16(1)
362 ; CHECK-NEXT: efscmplt 0, 3, 4
363 ; CHECK-NEXT: ble 0, .LBB17_2
364 ; CHECK-NEXT: # %bb.1: # %tr
365 ; CHECK-NEXT: li 3, 1
366 ; CHECK-NEXT: b .LBB17_3
367 ; CHECK-NEXT: .LBB17_2: # %fa
368 ; CHECK-NEXT: li 3, 0
369 ; CHECK-NEXT: .LBB17_3: # %ret
370 ; CHECK-NEXT: stw 3, 12(1)
371 ; CHECK-NEXT: lwz 3, 12(1)
372 ; CHECK-NEXT: addi 1, 1, 16
373 ; CHECK-NEXT: blr
374 entry:
375 %r = alloca i32, align 4
376 %c = fcmp olt float %a, %b
377 br i1 %c, label %tr, label %fa
378 tr:
379 store i32 1, ptr %r, align 4
380 br label %ret
381 fa:
382 store i32 0, ptr %r, align 4
383 br label %ret
384 ret:
385 %0 = load i32, ptr %r, align 4
386 ret i32 %0
387 }
389 define i1 @test_fcmpult(float %a, float %b) #0 {
390 ; CHECK-LABEL: test_fcmpult:
391 ; CHECK: # %bb.0: # %entry
392 ; CHECK-NEXT: efscmpeq 0, 3, 3
393 ; CHECK-NEXT: efscmpeq 1, 4, 4
394 ; CHECK-NEXT: crnand 20, 5, 1
395 ; CHECK-NEXT: efscmplt 0, 3, 4
396 ; CHECK-NEXT: li 5, 1
397 ; CHECK-NEXT: crnor 20, 1, 20
398 ; CHECK-NEXT: bc 12, 20, .LBB18_2
399 ; CHECK-NEXT: # %bb.1: # %entry
400 ; CHECK-NEXT: ori 3, 5, 0
401 ; CHECK-NEXT: blr
402 ; CHECK-NEXT: .LBB18_2: # %entry
403 ; CHECK-NEXT: li 3, 0
404 ; CHECK-NEXT: blr
405 entry:
406 %r = fcmp ult float %a, %b
407 ret i1 %r
408 }
410 define i32 @test_fcmpge(float %a, float %b) #0 {
411 ; CHECK-LABEL: test_fcmpge:
412 ; CHECK: # %bb.0: # %entry
413 ; CHECK-NEXT: stwu 1, -16(1)
414 ; CHECK-NEXT: efscmpeq 0, 3, 3
415 ; CHECK-NEXT: bc 4, 1, .LBB19_4
416 ; CHECK-NEXT: # %bb.1: # %entry
417 ; CHECK-NEXT: efscmpeq 0, 4, 4
418 ; CHECK-NEXT: bc 4, 1, .LBB19_4
419 ; CHECK-NEXT: # %bb.2: # %entry
420 ; CHECK-NEXT: efscmplt 0, 3, 4
421 ; CHECK-NEXT: bc 12, 1, .LBB19_4
422 ; CHECK-NEXT: # %bb.3: # %tr
423 ; CHECK-NEXT: li 3, 1
424 ; CHECK-NEXT: b .LBB19_5
425 ; CHECK-NEXT: .LBB19_4: # %fa
426 ; CHECK-NEXT: li 3, 0
427 ; CHECK-NEXT: .LBB19_5: # %ret
428 ; CHECK-NEXT: stw 3, 12(1)
429 ; CHECK-NEXT: lwz 3, 12(1)
430 ; CHECK-NEXT: addi 1, 1, 16
431 ; CHECK-NEXT: blr
432 entry:
433 %r = alloca i32, align 4
434 %c = fcmp oge float %a, %b
435 br i1 %c, label %tr, label %fa
436 tr:
437 store i32 1, ptr %r, align 4
438 br label %ret
439 fa:
440 store i32 0, ptr %r, align 4
441 br label %ret
442 ret:
443 %0 = load i32, ptr %r, align 4
444 ret i32 %0
445 }
447 define i32 @test_fcmpuge(float %a, float %b) #0 {
448 ; CHECK-LABEL: test_fcmpuge:
449 ; CHECK: # %bb.0: # %entry
450 ; CHECK-NEXT: stwu 1, -16(1)
451 ; CHECK-NEXT: efscmplt 0, 3, 4
452 ; CHECK-NEXT: bgt 0, .LBB20_2
453 ; CHECK-NEXT: # %bb.1: # %tr
454 ; CHECK-NEXT: li 3, 1
455 ; CHECK-NEXT: b .LBB20_3
456 ; CHECK-NEXT: .LBB20_2: # %fa
457 ; CHECK-NEXT: li 3, 0
458 ; CHECK-NEXT: .LBB20_3: # %ret
459 ; CHECK-NEXT: stw 3, 12(1)
460 ; CHECK-NEXT: lwz 3, 12(1)
461 ; CHECK-NEXT: addi 1, 1, 16
462 ; CHECK-NEXT: blr
463 entry:
464 %r = alloca i32, align 4
465 %c = fcmp uge float %a, %b
466 br i1 %c, label %tr, label %fa
467 tr:
468 store i32 1, ptr %r, align 4
469 br label %ret
470 fa:
471 store i32 0, ptr %r, align 4
472 br label %ret
473 ret:
474 %0 = load i32, ptr %r, align 4
475 ret i32 %0
476 }
479 define i32 @test_ftoui(float %a) #0 {
480 ; CHECK-LABEL: test_ftoui:
481 ; CHECK: # %bb.0:
482 ; CHECK-NEXT: efsctuiz 3, 3
483 ; CHECK-NEXT: blr
484 %v = fptoui float %a to i32
485 ret i32 %v
486 }
488 define i32 @test_ftosi(float %a) #0 {
489 ; CHECK-LABEL: test_ftosi:
490 ; CHECK: # %bb.0:
491 ; CHECK-NEXT: efsctsiz 3, 3
492 ; CHECK-NEXT: blr
493 %v = fptosi float %a to i32
494 ret i32 %v
495 }
497 define float @test_ffromui(i32 %a) #0 {
498 ; CHECK-LABEL: test_ffromui:
499 ; CHECK: # %bb.0:
500 ; CHECK-NEXT: efscfui 3, 3
501 ; CHECK-NEXT: blr
502 %v = uitofp i32 %a to float
503 ret float %v
504 }
506 define float @test_ffromsi(i32 %a) #0 {
507 ; CHECK-LABEL: test_ffromsi:
508 ; CHECK: # %bb.0:
509 ; CHECK-NEXT: efscfsi 3, 3
510 ; CHECK-NEXT: blr
511 %v = sitofp i32 %a to float
512 ret float %v
513 }
515 define i32 @test_fasmconst(float %x) #0 {
516 ; CHECK-LABEL: test_fasmconst:
517 ; CHECK: # %bb.0: # %entry
518 ; CHECK-NEXT: stwu 1, -32(1)
519 ; CHECK-NEXT: stw 3, 20(1)
520 ; CHECK-NEXT: stw 3, 24(1)
521 ; CHECK-NEXT: lwz 3, 20(1)
522 ; CHECK-NEXT: #APP
523 ; CHECK-NEXT: efsctsi 3, 3
524 ; CHECK-NEXT: #NO_APP
525 ; CHECK-NEXT: addi 1, 1, 32
526 ; CHECK-NEXT: blr
527 entry:
528 %x.addr = alloca float, align 8
529 store float %x, ptr %x.addr, align 8
530 %0 = load float, ptr %x.addr, align 8
531 %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)
532 ret i32 %1
533 ; Check that it's not loading a double
534 }
535 attributes #0 = { nounwind }
537 ; Double tests
538 ; results depend on -mattr=+spe or -mattr=+efpu2
540 define float @test_dtos(double %a) #0 {
541 ; SPE-LABEL: test_dtos:
542 ; SPE: # %bb.0: # %entry
543 ; SPE-NEXT: evmergelo 3, 3, 4
544 ; SPE-NEXT: efscfd 3, 3
545 ; SPE-NEXT: blr
546 ;
547 ; EFPU2-LABEL: test_dtos:
548 ; EFPU2: # %bb.0: # %entry
549 ; EFPU2-NEXT: mflr 0
550 ; EFPU2-NEXT: stwu 1, -16(1)
551 ; EFPU2-NEXT: stw 0, 20(1)
552 ; EFPU2-NEXT: bl __truncdfsf2
553 ; EFPU2-NEXT: lwz 0, 20(1)
554 ; EFPU2-NEXT: addi 1, 1, 16
555 ; EFPU2-NEXT: mtlr 0
556 ; EFPU2-NEXT: blr
557 entry:
558 %v = fptrunc double %a to float
559 ret float %v
560 }
562 define void @test_double_abs(ptr %aa) #0 {
563 ; SPE-LABEL: test_double_abs:
564 ; SPE: # %bb.0: # %entry
565 ; SPE-NEXT: evldd 4, 0(3)
566 ; SPE-NEXT: efdabs 4, 4
567 ; SPE-NEXT: evstdd 4, 0(3)
568 ; SPE-NEXT: blr
569 ;
570 ; EFPU2-LABEL: test_double_abs:
571 ; EFPU2: # %bb.0: # %entry
572 ; EFPU2-NEXT: lwz 4, 0(3)
573 ; EFPU2-NEXT: clrlwi 4, 4, 1
574 ; EFPU2-NEXT: stw 4, 0(3)
575 ; EFPU2-NEXT: blr
576 entry:
577 %0 = load double, ptr %aa
578 %1 = tail call double @llvm.fabs.f64(double %0) #2
579 store double %1, ptr %aa
580 ret void
581 }
583 ; Function Attrs: nounwind readnone
584 declare double @llvm.fabs.f64(double) #1
586 define void @test_dnabs(ptr %aa) #0 {
587 ; SPE-LABEL: test_dnabs:
588 ; SPE: # %bb.0: # %entry
589 ; SPE-NEXT: evldd 4, 0(3)
590 ; SPE-NEXT: efdnabs 4, 4
591 ; SPE-NEXT: evstdd 4, 0(3)
592 ; SPE-NEXT: blr
593 ;
594 ; EFPU2-LABEL: test_dnabs:
595 ; EFPU2: # %bb.0: # %entry
596 ; EFPU2-NEXT: lwz 4, 0(3)
597 ; EFPU2-NEXT: oris 4, 4, 32768
598 ; EFPU2-NEXT: stw 4, 0(3)
599 ; EFPU2-NEXT: blr
600 entry:
601 %0 = load double, ptr %aa
602 %1 = tail call double @llvm.fabs.f64(double %0) #2
603 %sub = fsub double -0.000000e+00, %1
604 store double %sub, ptr %aa
605 ret void
606 }
608 define double @test_ddiv(double %a, double %b) #0 {
609 ; SPE-LABEL: test_ddiv:
610 ; SPE: # %bb.0: # %entry
611 ; SPE-NEXT: evmergelo 5, 5, 6
612 ; SPE-NEXT: evmergelo 3, 3, 4
613 ; SPE-NEXT: efddiv 4, 3, 5
614 ; SPE-NEXT: evmergehi 3, 4, 4
615 ; SPE-NEXT: blr
616 ;
617 ; EFPU2-LABEL: test_ddiv:
618 ; EFPU2: # %bb.0: # %entry
619 ; EFPU2-NEXT: mflr 0
620 ; EFPU2-NEXT: stwu 1, -16(1)
621 ; EFPU2-NEXT: stw 0, 20(1)
622 ; EFPU2-NEXT: bl __divdf3
623 ; EFPU2-NEXT: lwz 0, 20(1)
624 ; EFPU2-NEXT: addi 1, 1, 16
625 ; EFPU2-NEXT: mtlr 0
626 ; EFPU2-NEXT: blr
627 entry:
628 %v = fdiv double %a, %b
629 ret double %v
631 }
633 define double @test_dmul(double %a, double %b) #0 {
634 ; SPE-LABEL: test_dmul:
635 ; SPE: # %bb.0: # %entry
636 ; SPE-NEXT: evmergelo 5, 5, 6
637 ; SPE-NEXT: evmergelo 3, 3, 4
638 ; SPE-NEXT: efdmul 4, 3, 5
639 ; SPE-NEXT: evmergehi 3, 4, 4
640 ; SPE-NEXT: blr
641 ;
642 ; EFPU2-LABEL: test_dmul:
643 ; EFPU2: # %bb.0: # %entry
644 ; EFPU2-NEXT: mflr 0
645 ; EFPU2-NEXT: stwu 1, -16(1)
646 ; EFPU2-NEXT: stw 0, 20(1)
647 ; EFPU2-NEXT: bl __muldf3
648 ; EFPU2-NEXT: lwz 0, 20(1)
649 ; EFPU2-NEXT: addi 1, 1, 16
650 ; EFPU2-NEXT: mtlr 0
651 ; EFPU2-NEXT: blr
652 entry:
653 %v = fmul double %a, %b
654 ret double %v
655 }
657 define double @test_dadd(double %a, double %b) #0 {
658 ; SPE-LABEL: test_dadd:
659 ; SPE: # %bb.0: # %entry
660 ; SPE-NEXT: evmergelo 5, 5, 6
661 ; SPE-NEXT: evmergelo 3, 3, 4
662 ; SPE-NEXT: efdadd 4, 3, 5
663 ; SPE-NEXT: evmergehi 3, 4, 4
664 ; SPE-NEXT: blr
665 ;
666 ; EFPU2-LABEL: test_dadd:
667 ; EFPU2: # %bb.0: # %entry
668 ; EFPU2-NEXT: mflr 0
669 ; EFPU2-NEXT: stwu 1, -16(1)
670 ; EFPU2-NEXT: stw 0, 20(1)
671 ; EFPU2-NEXT: bl __adddf3
672 ; EFPU2-NEXT: lwz 0, 20(1)
673 ; EFPU2-NEXT: addi 1, 1, 16
674 ; EFPU2-NEXT: mtlr 0
675 ; EFPU2-NEXT: blr
676 entry:
677 %v = fadd double %a, %b
678 ret double %v
679 }
681 define double @test_dsub(double %a, double %b) #0 {
682 ; SPE-LABEL: test_dsub:
683 ; SPE: # %bb.0: # %entry
684 ; SPE-NEXT: evmergelo 5, 5, 6
685 ; SPE-NEXT: evmergelo 3, 3, 4
686 ; SPE-NEXT: efdsub 4, 3, 5
687 ; SPE-NEXT: evmergehi 3, 4, 4
688 ; SPE-NEXT: blr
689 ;
690 ; EFPU2-LABEL: test_dsub:
691 ; EFPU2: # %bb.0: # %entry
692 ; EFPU2-NEXT: mflr 0
693 ; EFPU2-NEXT: stwu 1, -16(1)
694 ; EFPU2-NEXT: stw 0, 20(1)
695 ; EFPU2-NEXT: bl __subdf3
696 ; EFPU2-NEXT: lwz 0, 20(1)
697 ; EFPU2-NEXT: addi 1, 1, 16
698 ; EFPU2-NEXT: mtlr 0
699 ; EFPU2-NEXT: blr
700 entry:
701 %v = fsub double %a, %b
702 ret double %v
703 }
705 define double @test_dneg(double %a) #0 {
706 ; SPE-LABEL: test_dneg:
707 ; SPE: # %bb.0: # %entry
708 ; SPE-NEXT: evmergelo 3, 3, 4
709 ; SPE-NEXT: efdneg 4, 3
710 ; SPE-NEXT: evmergehi 3, 4, 4
711 ; SPE-NEXT: blr
712 ;
713 ; EFPU2-LABEL: test_dneg:
714 ; EFPU2: # %bb.0: # %entry
715 ; EFPU2-NEXT: xoris 3, 3, 32768
716 ; EFPU2-NEXT: blr
717 entry:
718 %v = fsub double -0.0, %a
719 ret double %v
720 }
722 define double @test_stod(float %a) #0 {
723 ; SPE-LABEL: test_stod:
724 ; SPE: # %bb.0: # %entry
725 ; SPE-NEXT: efdcfs 4, 3
726 ; SPE-NEXT: evmergehi 3, 4, 4
727 ; SPE-NEXT: blr
728 ;
729 ; EFPU2-LABEL: test_stod:
730 ; EFPU2: # %bb.0: # %entry
731 ; EFPU2-NEXT: mflr 0
732 ; EFPU2-NEXT: stwu 1, -16(1)
733 ; EFPU2-NEXT: stw 0, 20(1)
734 ; EFPU2-NEXT: bl __extendsfdf2
735 ; EFPU2-NEXT: lwz 0, 20(1)
736 ; EFPU2-NEXT: addi 1, 1, 16
737 ; EFPU2-NEXT: mtlr 0
738 ; EFPU2-NEXT: blr
739 entry:
740 %v = fpext float %a to double
741 ret double %v
742 }
744 ; (un)ordered tests are expanded to une and oeq so verify
745 define i1 @test_dcmpuno(double %a, double %b) #0 {
746 ; SPE-LABEL: test_dcmpuno:
747 ; SPE: # %bb.0: # %entry
748 ; SPE-NEXT: evmergelo 5, 5, 6
749 ; SPE-NEXT: evmergelo 3, 3, 4
750 ; SPE-NEXT: li 7, 1
751 ; SPE-NEXT: efdcmpeq 0, 3, 3
752 ; SPE-NEXT: efdcmpeq 1, 5, 5
753 ; SPE-NEXT: crand 20, 5, 1
754 ; SPE-NEXT: bc 12, 20, .LBB35_2
755 ; SPE-NEXT: # %bb.1: # %entry
756 ; SPE-NEXT: ori 3, 7, 0
757 ; SPE-NEXT: blr
758 ; SPE-NEXT: .LBB35_2: # %entry
759 ; SPE-NEXT: li 3, 0
760 ; SPE-NEXT: blr
761 ;
762 ; EFPU2-LABEL: test_dcmpuno:
763 ; EFPU2: # %bb.0: # %entry
764 ; EFPU2-NEXT: mflr 0
765 ; EFPU2-NEXT: stwu 1, -16(1)
766 ; EFPU2-NEXT: stw 0, 20(1)
767 ; EFPU2-NEXT: bl __unorddf2
768 ; EFPU2-NEXT: cntlzw 3, 3
769 ; EFPU2-NEXT: not 3, 3
770 ; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31
771 ; EFPU2-NEXT: lwz 0, 20(1)
772 ; EFPU2-NEXT: addi 1, 1, 16
773 ; EFPU2-NEXT: mtlr 0
774 ; EFPU2-NEXT: blr
775 entry:
776 %r = fcmp uno double %a, %b
777 ret i1 %r
778 }
780 define i1 @test_dcmpord(double %a, double %b) #0 {
781 ; SPE-LABEL: test_dcmpord:
782 ; SPE: # %bb.0: # %entry
783 ; SPE-NEXT: evmergelo 3, 3, 4
784 ; SPE-NEXT: evmergelo 4, 5, 6
785 ; SPE-NEXT: li 7, 1
786 ; SPE-NEXT: efdcmpeq 0, 4, 4
787 ; SPE-NEXT: efdcmpeq 1, 3, 3
788 ; SPE-NEXT: crnand 20, 5, 1
789 ; SPE-NEXT: bc 12, 20, .LBB36_2
790 ; SPE-NEXT: # %bb.1: # %entry
791 ; SPE-NEXT: ori 3, 7, 0
792 ; SPE-NEXT: blr
793 ; SPE-NEXT: .LBB36_2: # %entry
794 ; SPE-NEXT: li 3, 0
795 ; SPE-NEXT: blr
796 ;
797 ; EFPU2-LABEL: test_dcmpord:
798 ; EFPU2: # %bb.0: # %entry
799 ; EFPU2-NEXT: mflr 0
800 ; EFPU2-NEXT: stwu 1, -16(1)
801 ; EFPU2-NEXT: stw 0, 20(1)
802 ; EFPU2-NEXT: bl __unorddf2
803 ; EFPU2-NEXT: cntlzw 3, 3
804 ; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31
805 ; EFPU2-NEXT: lwz 0, 20(1)
806 ; EFPU2-NEXT: addi 1, 1, 16
807 ; EFPU2-NEXT: mtlr 0
808 ; EFPU2-NEXT: blr
809 entry:
810 %r = fcmp ord double %a, %b
811 ret i1 %r
812 }
814 define i32 @test_dcmpgt(double %a, double %b) #0 {
815 ; SPE-LABEL: test_dcmpgt:
816 ; SPE: # %bb.0: # %entry
817 ; SPE-NEXT: stwu 1, -16(1)
818 ; SPE-NEXT: evmergelo 5, 5, 6
819 ; SPE-NEXT: evmergelo 3, 3, 4
820 ; SPE-NEXT: efdcmpgt 0, 3, 5
821 ; SPE-NEXT: ble 0, .LBB37_2
822 ; SPE-NEXT: # %bb.1: # %tr
823 ; SPE-NEXT: li 3, 1
824 ; SPE-NEXT: b .LBB37_3
825 ; SPE-NEXT: .LBB37_2: # %fa
826 ; SPE-NEXT: li 3, 0
827 ; SPE-NEXT: .LBB37_3: # %ret
828 ; SPE-NEXT: stw 3, 12(1)
829 ; SPE-NEXT: lwz 3, 12(1)
830 ; SPE-NEXT: addi 1, 1, 16
831 ; SPE-NEXT: blr
832 ;
833 ; EFPU2-LABEL: test_dcmpgt:
834 ; EFPU2: # %bb.0: # %entry
835 ; EFPU2-NEXT: mflr 0
836 ; EFPU2-NEXT: stwu 1, -16(1)
837 ; EFPU2-NEXT: stw 0, 20(1)
838 ; EFPU2-NEXT: bl __gtdf2
839 ; EFPU2-NEXT: cmpwi 3, 0
840 ; EFPU2-NEXT: ble 0, .LBB37_2
841 ; EFPU2-NEXT: # %bb.1: # %tr
842 ; EFPU2-NEXT: li 3, 1
843 ; EFPU2-NEXT: b .LBB37_3
844 ; EFPU2-NEXT: .LBB37_2: # %fa
845 ; EFPU2-NEXT: li 3, 0
846 ; EFPU2-NEXT: .LBB37_3: # %ret
847 ; EFPU2-NEXT: stw 3, 12(1)
848 ; EFPU2-NEXT: lwz 3, 12(1)
849 ; EFPU2-NEXT: lwz 0, 20(1)
850 ; EFPU2-NEXT: addi 1, 1, 16
851 ; EFPU2-NEXT: mtlr 0
852 ; EFPU2-NEXT: blr
853 entry:
854 %r = alloca i32, align 4
855 %c = fcmp ogt double %a, %b
856 br i1 %c, label %tr, label %fa
857 tr:
858 store i32 1, ptr %r, align 4
859 br label %ret
860 fa:
861 store i32 0, ptr %r, align 4
862 br label %ret
863 ret:
864 %0 = load i32, ptr %r, align 4
865 ret i32 %0
866 }
868 define i32 @test_dcmpugt(double %a, double %b) #0 {
869 ; SPE-LABEL: test_dcmpugt:
870 ; SPE: # %bb.0: # %entry
871 ; SPE-NEXT: stwu 1, -16(1)
872 ; SPE-NEXT: evmergelo 3, 3, 4
873 ; SPE-NEXT: evmergelo 4, 5, 6
874 ; SPE-NEXT: efdcmpeq 0, 4, 4
875 ; SPE-NEXT: bc 4, 1, .LBB38_4
876 ; SPE-NEXT: # %bb.1: # %entry
877 ; SPE-NEXT: efdcmpeq 0, 3, 3
878 ; SPE-NEXT: bc 4, 1, .LBB38_4
879 ; SPE-NEXT: # %bb.2: # %entry
880 ; SPE-NEXT: efdcmpgt 0, 3, 4
881 ; SPE-NEXT: bc 12, 1, .LBB38_4
882 ; SPE-NEXT: # %bb.3: # %fa
883 ; SPE-NEXT: li 3, 0
884 ; SPE-NEXT: b .LBB38_5
885 ; SPE-NEXT: .LBB38_4: # %tr
886 ; SPE-NEXT: li 3, 1
887 ; SPE-NEXT: .LBB38_5: # %ret
888 ; SPE-NEXT: stw 3, 12(1)
889 ; SPE-NEXT: lwz 3, 12(1)
890 ; SPE-NEXT: addi 1, 1, 16
891 ; SPE-NEXT: blr
892 ;
893 ; EFPU2-LABEL: test_dcmpugt:
894 ; EFPU2: # %bb.0: # %entry
895 ; EFPU2-NEXT: mflr 0
896 ; EFPU2-NEXT: stwu 1, -16(1)
897 ; EFPU2-NEXT: stw 0, 20(1)
898 ; EFPU2-NEXT: bl __ledf2
899 ; EFPU2-NEXT: cmpwi 3, 0
900 ; EFPU2-NEXT: ble 0, .LBB38_2
901 ; EFPU2-NEXT: # %bb.1: # %tr
902 ; EFPU2-NEXT: li 3, 1
903 ; EFPU2-NEXT: b .LBB38_3
904 ; EFPU2-NEXT: .LBB38_2: # %fa
905 ; EFPU2-NEXT: li 3, 0
906 ; EFPU2-NEXT: .LBB38_3: # %ret
907 ; EFPU2-NEXT: stw 3, 12(1)
908 ; EFPU2-NEXT: lwz 3, 12(1)
909 ; EFPU2-NEXT: lwz 0, 20(1)
910 ; EFPU2-NEXT: addi 1, 1, 16
911 ; EFPU2-NEXT: mtlr 0
912 ; EFPU2-NEXT: blr
913 entry:
914 %r = alloca i32, align 4
915 %c = fcmp ugt double %a, %b
916 br i1 %c, label %tr, label %fa
917 tr:
918 store i32 1, ptr %r, align 4
919 br label %ret
920 fa:
921 store i32 0, ptr %r, align 4
922 br label %ret
923 ret:
924 %0 = load i32, ptr %r, align 4
925 ret i32 %0
926 }
928 define i32 @test_dcmple(double %a, double %b) #0 {
929 ; SPE-LABEL: test_dcmple:
930 ; SPE: # %bb.0: # %entry
931 ; SPE-NEXT: stwu 1, -16(1)
932 ; SPE-NEXT: evmergelo 5, 5, 6
933 ; SPE-NEXT: evmergelo 3, 3, 4
934 ; SPE-NEXT: efdcmpgt 0, 3, 5
935 ; SPE-NEXT: bgt 0, .LBB39_2
936 ; SPE-NEXT: # %bb.1: # %tr
937 ; SPE-NEXT: li 3, 1
938 ; SPE-NEXT: b .LBB39_3
939 ; SPE-NEXT: .LBB39_2: # %fa
940 ; SPE-NEXT: li 3, 0
941 ; SPE-NEXT: .LBB39_3: # %ret
942 ; SPE-NEXT: stw 3, 12(1)
943 ; SPE-NEXT: lwz 3, 12(1)
944 ; SPE-NEXT: addi 1, 1, 16
945 ; SPE-NEXT: blr
946 ;
947 ; EFPU2-LABEL: test_dcmple:
948 ; EFPU2: # %bb.0: # %entry
949 ; EFPU2-NEXT: mflr 0
950 ; EFPU2-NEXT: stwu 1, -16(1)
951 ; EFPU2-NEXT: stw 0, 20(1)
952 ; EFPU2-NEXT: bl __gtdf2
953 ; EFPU2-NEXT: cmpwi 3, 0
954 ; EFPU2-NEXT: bgt 0, .LBB39_2
955 ; EFPU2-NEXT: # %bb.1: # %tr
956 ; EFPU2-NEXT: li 3, 1
957 ; EFPU2-NEXT: b .LBB39_3
958 ; EFPU2-NEXT: .LBB39_2: # %fa
959 ; EFPU2-NEXT: li 3, 0
960 ; EFPU2-NEXT: .LBB39_3: # %ret
961 ; EFPU2-NEXT: stw 3, 12(1)
962 ; EFPU2-NEXT: lwz 3, 12(1)
963 ; EFPU2-NEXT: lwz 0, 20(1)
964 ; EFPU2-NEXT: addi 1, 1, 16
965 ; EFPU2-NEXT: mtlr 0
966 ; EFPU2-NEXT: blr
967 entry:
968 %r = alloca i32, align 4
969 %c = fcmp ule double %a, %b
970 br i1 %c, label %tr, label %fa
971 tr:
972 store i32 1, ptr %r, align 4
973 br label %ret
974 fa:
975 store i32 0, ptr %r, align 4
976 br label %ret
977 ret:
978 %0 = load i32, ptr %r, align 4
979 ret i32 %0
980 }
982 define i32 @test_dcmpule(double %a, double %b) #0 {
983 ; SPE-LABEL: test_dcmpule:
984 ; SPE: # %bb.0: # %entry
985 ; SPE-NEXT: stwu 1, -16(1)
986 ; SPE-NEXT: evmergelo 5, 5, 6
987 ; SPE-NEXT: evmergelo 3, 3, 4
988 ; SPE-NEXT: efdcmpgt 0, 3, 5
989 ; SPE-NEXT: bgt 0, .LBB40_2
990 ; SPE-NEXT: # %bb.1: # %tr
991 ; SPE-NEXT: li 3, 1
992 ; SPE-NEXT: b .LBB40_3
993 ; SPE-NEXT: .LBB40_2: # %fa
994 ; SPE-NEXT: li 3, 0
995 ; SPE-NEXT: .LBB40_3: # %ret
996 ; SPE-NEXT: stw 3, 12(1)
997 ; SPE-NEXT: lwz 3, 12(1)
998 ; SPE-NEXT: addi 1, 1, 16
999 ; SPE-NEXT: blr
1000 ;
1001 ; EFPU2-LABEL: test_dcmpule:
1002 ; EFPU2: # %bb.0: # %entry
1003 ; EFPU2-NEXT: mflr 0
1004 ; EFPU2-NEXT: stwu 1, -16(1)
1005 ; EFPU2-NEXT: stw 0, 20(1)
1006 ; EFPU2-NEXT: bl __gtdf2
1007 ; EFPU2-NEXT: cmpwi 3, 0
1008 ; EFPU2-NEXT: bgt 0, .LBB40_2
1009 ; EFPU2-NEXT: # %bb.1: # %tr
1010 ; EFPU2-NEXT: li 3, 1
1011 ; EFPU2-NEXT: b .LBB40_3
1012 ; EFPU2-NEXT: .LBB40_2: # %fa
1013 ; EFPU2-NEXT: li 3, 0
1014 ; EFPU2-NEXT: .LBB40_3: # %ret
1015 ; EFPU2-NEXT: stw 3, 12(1)
1016 ; EFPU2-NEXT: lwz 3, 12(1)
1017 ; EFPU2-NEXT: lwz 0, 20(1)
1018 ; EFPU2-NEXT: addi 1, 1, 16
1019 ; EFPU2-NEXT: mtlr 0
1020 ; EFPU2-NEXT: blr
1021 entry:
1022 %r = alloca i32, align 4
1023 %c = fcmp ule double %a, %b
1024 br i1 %c, label %tr, label %fa
1025 tr:
1026 store i32 1, ptr %r, align 4
1027 br label %ret
1028 fa:
1029 store i32 0, ptr %r, align 4
1030 br label %ret
1031 ret:
1032 %0 = load i32, ptr %r, align 4
1033 ret i32 %0
1034 }
1036 ; The type of comparison found in C's if (x == y)
1037 define i32 @test_dcmpeq(double %a, double %b) #0 {
1038 ; SPE-LABEL: test_dcmpeq:
1039 ; SPE: # %bb.0: # %entry
1040 ; SPE-NEXT: stwu 1, -16(1)
1041 ; SPE-NEXT: evmergelo 5, 5, 6
1042 ; SPE-NEXT: evmergelo 3, 3, 4
1043 ; SPE-NEXT: efdcmpeq 0, 3, 5
1044 ; SPE-NEXT: ble 0, .LBB41_2
1045 ; SPE-NEXT: # %bb.1: # %tr
1046 ; SPE-NEXT: li 3, 1
1047 ; SPE-NEXT: b .LBB41_3
1048 ; SPE-NEXT: .LBB41_2: # %fa
1049 ; SPE-NEXT: li 3, 0
1050 ; SPE-NEXT: .LBB41_3: # %ret
1051 ; SPE-NEXT: stw 3, 12(1)
1052 ; SPE-NEXT: lwz 3, 12(1)
1053 ; SPE-NEXT: addi 1, 1, 16
1054 ; SPE-NEXT: blr
1055 ;
1056 ; EFPU2-LABEL: test_dcmpeq:
1057 ; EFPU2: # %bb.0: # %entry
1058 ; EFPU2-NEXT: mflr 0
1059 ; EFPU2-NEXT: stwu 1, -16(1)
1060 ; EFPU2-NEXT: stw 0, 20(1)
1061 ; EFPU2-NEXT: bl __nedf2
1062 ; EFPU2-NEXT: cmplwi 3, 0
1063 ; EFPU2-NEXT: bne 0, .LBB41_2
1064 ; EFPU2-NEXT: # %bb.1: # %tr
1065 ; EFPU2-NEXT: li 3, 1
1066 ; EFPU2-NEXT: b .LBB41_3
1067 ; EFPU2-NEXT: .LBB41_2: # %fa
1068 ; EFPU2-NEXT: li 3, 0
1069 ; EFPU2-NEXT: .LBB41_3: # %ret
1070 ; EFPU2-NEXT: stw 3, 12(1)
1071 ; EFPU2-NEXT: lwz 3, 12(1)
1072 ; EFPU2-NEXT: lwz 0, 20(1)
1073 ; EFPU2-NEXT: addi 1, 1, 16
1074 ; EFPU2-NEXT: mtlr 0
1075 ; EFPU2-NEXT: blr
1076 entry:
1077 %r = alloca i32, align 4
1078 %c = fcmp oeq double %a, %b
1079 br i1 %c, label %tr, label %fa
1080 tr:
1081 store i32 1, ptr %r, align 4
1082 br label %ret
1083 fa:
1084 store i32 0, ptr %r, align 4
1085 br label %ret
1086 ret:
1087 %0 = load i32, ptr %r, align 4
1088 ret i32 %0
1089 }
1091 define i32 @test_dcmpueq(double %a, double %b) #0 {
1092 ; SPE-LABEL: test_dcmpueq:
1093 ; SPE: # %bb.0: # %entry
1094 ; SPE-NEXT: stwu 1, -16(1)
1095 ; SPE-NEXT: evmergelo 5, 5, 6
1096 ; SPE-NEXT: evmergelo 3, 3, 4
1097 ; SPE-NEXT: efdcmplt 0, 3, 5
1098 ; SPE-NEXT: bc 12, 1, .LBB42_3
1099 ; SPE-NEXT: # %bb.1: # %entry
1100 ; SPE-NEXT: efdcmpgt 0, 3, 5
1101 ; SPE-NEXT: bc 12, 1, .LBB42_3
1102 ; SPE-NEXT: # %bb.2: # %tr
1103 ; SPE-NEXT: li 3, 1
1104 ; SPE-NEXT: b .LBB42_4
1105 ; SPE-NEXT: .LBB42_3: # %fa
1106 ; SPE-NEXT: li 3, 0
1107 ; SPE-NEXT: .LBB42_4: # %ret
1108 ; SPE-NEXT: stw 3, 12(1)
1109 ; SPE-NEXT: lwz 3, 12(1)
1110 ; SPE-NEXT: addi 1, 1, 16
1111 ; SPE-NEXT: blr
1112 ;
1113 ; EFPU2-LABEL: test_dcmpueq:
1114 ; EFPU2: # %bb.0: # %entry
1115 ; EFPU2-NEXT: mflr 0
1116 ; EFPU2-NEXT: stwu 1, -48(1)
1117 ; EFPU2-NEXT: mfcr 12
1118 ; EFPU2-NEXT: stw 0, 52(1)
1119 ; EFPU2-NEXT: stw 12, 24(1)
1120 ; EFPU2-NEXT: stw 27, 28(1) # 4-byte Folded Spill
1121 ; EFPU2-NEXT: mr 27, 3
1122 ; EFPU2-NEXT: stw 28, 32(1) # 4-byte Folded Spill
1123 ; EFPU2-NEXT: mr 28, 4
1124 ; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill
1125 ; EFPU2-NEXT: mr 29, 5
1126 ; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill
1127 ; EFPU2-NEXT: mr 30, 6
1128 ; EFPU2-NEXT: bl __eqdf2
1129 ; EFPU2-NEXT: cmpwi 2, 3, 0
1130 ; EFPU2-NEXT: mr 3, 27
1131 ; EFPU2-NEXT: mr 4, 28
1132 ; EFPU2-NEXT: mr 5, 29
1133 ; EFPU2-NEXT: mr 6, 30
1134 ; EFPU2-NEXT: bl __unorddf2
1135 ; EFPU2-NEXT: bc 12, 10, .LBB42_3
1136 ; EFPU2-NEXT: # %bb.1: # %entry
1137 ; EFPU2-NEXT: cmpwi 3, 0
1138 ; EFPU2-NEXT: bc 4, 2, .LBB42_3
1139 ; EFPU2-NEXT: # %bb.2: # %fa
1140 ; EFPU2-NEXT: li 3, 0
1141 ; EFPU2-NEXT: b .LBB42_4
1142 ; EFPU2-NEXT: .LBB42_3: # %tr
1143 ; EFPU2-NEXT: li 3, 1
1144 ; EFPU2-NEXT: .LBB42_4: # %ret
1145 ; EFPU2-NEXT: stw 3, 20(1)
1146 ; EFPU2-NEXT: lwz 3, 20(1)
1147 ; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
1148 ; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
1149 ; EFPU2-NEXT: lwz 28, 32(1) # 4-byte Folded Reload
1150 ; EFPU2-NEXT: lwz 12, 24(1)
1151 ; EFPU2-NEXT: lwz 27, 28(1) # 4-byte Folded Reload
1152 ; EFPU2-NEXT: mtcrf 32, 12 # cr2
1153 ; EFPU2-NEXT: lwz 0, 52(1)
1154 ; EFPU2-NEXT: addi 1, 1, 48
1155 ; EFPU2-NEXT: mtlr 0
1156 ; EFPU2-NEXT: blr
1157 entry:
1158 %r = alloca i32, align 4
1159 %c = fcmp ueq double %a, %b
1160 br i1 %c, label %tr, label %fa
1161 tr:
1162 store i32 1, ptr %r, align 4
1163 br label %ret
1164 fa:
1165 store i32 0, ptr %r, align 4
1166 br label %ret
1167 ret:
1168 %0 = load i32, ptr %r, align 4
1169 ret i32 %0
1170 }
1172 define i1 @test_dcmpne(double %a, double %b) #0 {
1173 ; SPE-LABEL: test_dcmpne:
1174 ; SPE: # %bb.0: # %entry
1175 ; SPE-NEXT: evmergelo 5, 5, 6
1176 ; SPE-NEXT: evmergelo 3, 3, 4
1177 ; SPE-NEXT: li 7, 1
1178 ; SPE-NEXT: efdcmplt 0, 3, 5
1179 ; SPE-NEXT: efdcmpgt 1, 3, 5
1180 ; SPE-NEXT: crnor 20, 5, 1
1181 ; SPE-NEXT: bc 12, 20, .LBB43_2
1182 ; SPE-NEXT: # %bb.1: # %entry
1183 ; SPE-NEXT: ori 3, 7, 0
1184 ; SPE-NEXT: blr
1185 ; SPE-NEXT: .LBB43_2: # %entry
1186 ; SPE-NEXT: li 3, 0
1187 ; SPE-NEXT: blr
1188 ;
1189 ; EFPU2-LABEL: test_dcmpne:
1190 ; EFPU2: # %bb.0: # %entry
1191 ; EFPU2-NEXT: mflr 0
1192 ; EFPU2-NEXT: stwu 1, -48(1)
1193 ; EFPU2-NEXT: mfcr 12
1194 ; EFPU2-NEXT: stw 0, 52(1)
1195 ; EFPU2-NEXT: stw 12, 24(1)
1196 ; EFPU2-NEXT: stw 27, 28(1) # 4-byte Folded Spill
1197 ; EFPU2-NEXT: mr 27, 3
1198 ; EFPU2-NEXT: stw 28, 32(1) # 4-byte Folded Spill
1199 ; EFPU2-NEXT: mr 28, 4
1200 ; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill
1201 ; EFPU2-NEXT: mr 29, 5
1202 ; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill
1203 ; EFPU2-NEXT: mr 30, 6
1204 ; EFPU2-NEXT: bl __unorddf2
1205 ; EFPU2-NEXT: cmpwi 2, 3, 0
1206 ; EFPU2-NEXT: mr 3, 27
1207 ; EFPU2-NEXT: mr 4, 28
1208 ; EFPU2-NEXT: mr 5, 29
1209 ; EFPU2-NEXT: mr 6, 30
1210 ; EFPU2-NEXT: bl __eqdf2
1211 ; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
1212 ; EFPU2-NEXT: cmpwi 3, 0
1213 ; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
1214 ; EFPU2-NEXT: li 4, 1
1215 ; EFPU2-NEXT: lwz 28, 32(1) # 4-byte Folded Reload
1216 ; EFPU2-NEXT: crorc 20, 2, 10
1217 ; EFPU2-NEXT: lwz 12, 24(1)
1218 ; EFPU2-NEXT: bc 12, 20, .LBB43_2
1219 ; EFPU2-NEXT: # %bb.1: # %entry
1220 ; EFPU2-NEXT: ori 3, 4, 0
1221 ; EFPU2-NEXT: b .LBB43_3
1222 ; EFPU2-NEXT: .LBB43_2: # %entry
1223 ; EFPU2-NEXT: li 3, 0
1224 ; EFPU2-NEXT: .LBB43_3: # %entry
1225 ; EFPU2-NEXT: lwz 27, 28(1) # 4-byte Folded Reload
1226 ; EFPU2-NEXT: mtcrf 32, 12 # cr2
1227 ; EFPU2-NEXT: lwz 0, 52(1)
1228 ; EFPU2-NEXT: addi 1, 1, 48
1229 ; EFPU2-NEXT: mtlr 0
1230 ; EFPU2-NEXT: blr
1231 entry:
1232 %r = fcmp one double %a, %b
1233 ret i1 %r
1234 }
1236 define i32 @test_dcmpune(double %a, double %b) #0 {
1237 ; SPE-LABEL: test_dcmpune:
1238 ; SPE: # %bb.0: # %entry
1239 ; SPE-NEXT: stwu 1, -16(1)
1240 ; SPE-NEXT: evmergelo 5, 5, 6
1241 ; SPE-NEXT: evmergelo 3, 3, 4
1242 ; SPE-NEXT: efdcmpeq 0, 3, 5
1243 ; SPE-NEXT: bgt 0, .LBB44_2
1244 ; SPE-NEXT: # %bb.1: # %tr
1245 ; SPE-NEXT: li 3, 1
1246 ; SPE-NEXT: b .LBB44_3
1247 ; SPE-NEXT: .LBB44_2: # %fa
1248 ; SPE-NEXT: li 3, 0
1249 ; SPE-NEXT: .LBB44_3: # %ret
1250 ; SPE-NEXT: stw 3, 12(1)
1251 ; SPE-NEXT: lwz 3, 12(1)
1252 ; SPE-NEXT: addi 1, 1, 16
1253 ; SPE-NEXT: blr
1254 ;
1255 ; EFPU2-LABEL: test_dcmpune:
1256 ; EFPU2: # %bb.0: # %entry
1257 ; EFPU2-NEXT: mflr 0
1258 ; EFPU2-NEXT: stwu 1, -16(1)
1259 ; EFPU2-NEXT: stw 0, 20(1)
1260 ; EFPU2-NEXT: bl __eqdf2
1261 ; EFPU2-NEXT: cmplwi 3, 0
1262 ; EFPU2-NEXT: beq 0, .LBB44_2
1263 ; EFPU2-NEXT: # %bb.1: # %tr
1264 ; EFPU2-NEXT: li 3, 1
1265 ; EFPU2-NEXT: b .LBB44_3
1266 ; EFPU2-NEXT: .LBB44_2: # %fa
1267 ; EFPU2-NEXT: li 3, 0
1268 ; EFPU2-NEXT: .LBB44_3: # %ret
1269 ; EFPU2-NEXT: stw 3, 12(1)
1270 ; EFPU2-NEXT: lwz 3, 12(1)
1271 ; EFPU2-NEXT: lwz 0, 20(1)
1272 ; EFPU2-NEXT: addi 1, 1, 16
1273 ; EFPU2-NEXT: mtlr 0
1274 ; EFPU2-NEXT: blr
1275 entry:
1276 %r = alloca i32, align 4
1277 %c = fcmp une double %a, %b
1278 br i1 %c, label %tr, label %fa
1279 tr:
1280 store i32 1, ptr %r, align 4
1281 br label %ret
1282 fa:
1283 store i32 0, ptr %r, align 4
1284 br label %ret
1285 ret:
1286 %0 = load i32, ptr %r, align 4
1287 ret i32 %0
1288 }
1290 define i32 @test_dcmplt(double %a, double %b) #0 {
1291 ; SPE-LABEL: test_dcmplt:
1292 ; SPE: # %bb.0: # %entry
1293 ; SPE-NEXT: stwu 1, -16(1)
1294 ; SPE-NEXT: evmergelo 5, 5, 6
1295 ; SPE-NEXT: evmergelo 3, 3, 4
1296 ; SPE-NEXT: efdcmplt 0, 3, 5
1297 ; SPE-NEXT: ble 0, .LBB45_2
1298 ; SPE-NEXT: # %bb.1: # %tr
1299 ; SPE-NEXT: li 3, 1
1300 ; SPE-NEXT: b .LBB45_3
1301 ; SPE-NEXT: .LBB45_2: # %fa
1302 ; SPE-NEXT: li 3, 0
1303 ; SPE-NEXT: .LBB45_3: # %ret
1304 ; SPE-NEXT: stw 3, 12(1)
1305 ; SPE-NEXT: lwz 3, 12(1)
1306 ; SPE-NEXT: addi 1, 1, 16
1307 ; SPE-NEXT: blr
1308 ;
1309 ; EFPU2-LABEL: test_dcmplt:
1310 ; EFPU2: # %bb.0: # %entry
1311 ; EFPU2-NEXT: mflr 0
1312 ; EFPU2-NEXT: stwu 1, -16(1)
1313 ; EFPU2-NEXT: stw 0, 20(1)
1314 ; EFPU2-NEXT: bl __ltdf2
1315 ; EFPU2-NEXT: cmpwi 3, 0
1316 ; EFPU2-NEXT: bge 0, .LBB45_2
1317 ; EFPU2-NEXT: # %bb.1: # %tr
1318 ; EFPU2-NEXT: li 3, 1
1319 ; EFPU2-NEXT: b .LBB45_3
1320 ; EFPU2-NEXT: .LBB45_2: # %fa
1321 ; EFPU2-NEXT: li 3, 0
1322 ; EFPU2-NEXT: .LBB45_3: # %ret
1323 ; EFPU2-NEXT: stw 3, 12(1)
1324 ; EFPU2-NEXT: lwz 3, 12(1)
1325 ; EFPU2-NEXT: lwz 0, 20(1)
1326 ; EFPU2-NEXT: addi 1, 1, 16
1327 ; EFPU2-NEXT: mtlr 0
1328 ; EFPU2-NEXT: blr
1329 entry:
1330 %r = alloca i32, align 4
1331 %c = fcmp olt double %a, %b
1332 br i1 %c, label %tr, label %fa
1333 tr:
1334 store i32 1, ptr %r, align 4
1335 br label %ret
1336 fa:
1337 store i32 0, ptr %r, align 4
1338 br label %ret
1339 ret:
1340 %0 = load i32, ptr %r, align 4
1341 ret i32 %0
1342 }
1344 define i32 @test_dcmpult(double %a, double %b) #0 {
1345 ; SPE-LABEL: test_dcmpult:
1346 ; SPE: # %bb.0: # %entry
1347 ; SPE-NEXT: stwu 1, -16(1)
1348 ; SPE-NEXT: evmergelo 3, 3, 4
1349 ; SPE-NEXT: evmergelo 4, 5, 6
1350 ; SPE-NEXT: efdcmpeq 0, 4, 4
1351 ; SPE-NEXT: bc 4, 1, .LBB46_4
1352 ; SPE-NEXT: # %bb.1: # %entry
1353 ; SPE-NEXT: efdcmpeq 0, 3, 3
1354 ; SPE-NEXT: bc 4, 1, .LBB46_4
1355 ; SPE-NEXT: # %bb.2: # %entry
1356 ; SPE-NEXT: efdcmplt 0, 3, 4
1357 ; SPE-NEXT: bc 12, 1, .LBB46_4
1358 ; SPE-NEXT: # %bb.3: # %fa
1359 ; SPE-NEXT: li 3, 0
1360 ; SPE-NEXT: b .LBB46_5
1361 ; SPE-NEXT: .LBB46_4: # %tr
1362 ; SPE-NEXT: li 3, 1
1363 ; SPE-NEXT: .LBB46_5: # %ret
1364 ; SPE-NEXT: stw 3, 12(1)
1365 ; SPE-NEXT: lwz 3, 12(1)
1366 ; SPE-NEXT: addi 1, 1, 16
1367 ; SPE-NEXT: blr
1368 ;
1369 ; EFPU2-LABEL: test_dcmpult:
1370 ; EFPU2: # %bb.0: # %entry
1371 ; EFPU2-NEXT: mflr 0
1372 ; EFPU2-NEXT: stwu 1, -16(1)
1373 ; EFPU2-NEXT: stw 0, 20(1)
1374 ; EFPU2-NEXT: bl __gedf2
1375 ; EFPU2-NEXT: cmpwi 3, 0
1376 ; EFPU2-NEXT: bge 0, .LBB46_2
1377 ; EFPU2-NEXT: # %bb.1: # %tr
1378 ; EFPU2-NEXT: li 3, 1
1379 ; EFPU2-NEXT: b .LBB46_3
1380 ; EFPU2-NEXT: .LBB46_2: # %fa
1381 ; EFPU2-NEXT: li 3, 0
1382 ; EFPU2-NEXT: .LBB46_3: # %ret
1383 ; EFPU2-NEXT: stw 3, 12(1)
1384 ; EFPU2-NEXT: lwz 3, 12(1)
1385 ; EFPU2-NEXT: lwz 0, 20(1)
1386 ; EFPU2-NEXT: addi 1, 1, 16
1387 ; EFPU2-NEXT: mtlr 0
1388 ; EFPU2-NEXT: blr
1389 entry:
1390 %r = alloca i32, align 4
1391 %c = fcmp ult double %a, %b
1392 br i1 %c, label %tr, label %fa
1393 tr:
1394 store i32 1, ptr %r, align 4
1395 br label %ret
1396 fa:
1397 store i32 0, ptr %r, align 4
1398 br label %ret
1399 ret:
1400 %0 = load i32, ptr %r, align 4
1401 ret i32 %0
1402 }
1404 define i1 @test_dcmpge(double %a, double %b) #0 {
1405 ; SPE-LABEL: test_dcmpge:
1406 ; SPE: # %bb.0: # %entry
1407 ; SPE-NEXT: evmergelo 3, 3, 4
1408 ; SPE-NEXT: evmergelo 4, 5, 6
1409 ; SPE-NEXT: li 7, 1
1410 ; SPE-NEXT: efdcmpeq 0, 4, 4
1411 ; SPE-NEXT: efdcmpeq 1, 3, 3
1412 ; SPE-NEXT: efdcmplt 5, 3, 4
1413 ; SPE-NEXT: crand 20, 5, 1
1414 ; SPE-NEXT: crorc 20, 21, 20
1415 ; SPE-NEXT: bc 12, 20, .LBB47_2
1416 ; SPE-NEXT: # %bb.1: # %entry
1417 ; SPE-NEXT: ori 3, 7, 0
1418 ; SPE-NEXT: blr
1419 ; SPE-NEXT: .LBB47_2: # %entry
1420 ; SPE-NEXT: li 3, 0
1421 ; SPE-NEXT: blr
1422 ;
1423 ; EFPU2-LABEL: test_dcmpge:
1424 ; EFPU2: # %bb.0: # %entry
1425 ; EFPU2-NEXT: mflr 0
1426 ; EFPU2-NEXT: stwu 1, -16(1)
1427 ; EFPU2-NEXT: stw 0, 20(1)
1428 ; EFPU2-NEXT: bl __gedf2
1429 ; EFPU2-NEXT: not 3, 3
1430 ; EFPU2-NEXT: srwi 3, 3, 31
1431 ; EFPU2-NEXT: lwz 0, 20(1)
1432 ; EFPU2-NEXT: addi 1, 1, 16
1433 ; EFPU2-NEXT: mtlr 0
1434 ; EFPU2-NEXT: blr
1435 entry:
1436 %r = fcmp oge double %a, %b
1437 ret i1 %r
1438 }
1440 define i32 @test_dcmpuge(double %a, double %b) #0 {
1441 ; SPE-LABEL: test_dcmpuge:
1442 ; SPE: # %bb.0: # %entry
1443 ; SPE-NEXT: stwu 1, -16(1)
1444 ; SPE-NEXT: evmergelo 5, 5, 6
1445 ; SPE-NEXT: evmergelo 3, 3, 4
1446 ; SPE-NEXT: efdcmplt 0, 3, 5
1447 ; SPE-NEXT: bgt 0, .LBB48_2
1448 ; SPE-NEXT: # %bb.1: # %tr
1449 ; SPE-NEXT: li 3, 1
1450 ; SPE-NEXT: b .LBB48_3
1451 ; SPE-NEXT: .LBB48_2: # %fa
1452 ; SPE-NEXT: li 3, 0
1453 ; SPE-NEXT: .LBB48_3: # %ret
1454 ; SPE-NEXT: stw 3, 12(1)
1455 ; SPE-NEXT: lwz 3, 12(1)
1456 ; SPE-NEXT: addi 1, 1, 16
1457 ; SPE-NEXT: blr
1458 ;
1459 ; EFPU2-LABEL: test_dcmpuge:
1460 ; EFPU2: # %bb.0: # %entry
1461 ; EFPU2-NEXT: mflr 0
1462 ; EFPU2-NEXT: stwu 1, -16(1)
1463 ; EFPU2-NEXT: stw 0, 20(1)
1464 ; EFPU2-NEXT: bl __ltdf2
1465 ; EFPU2-NEXT: cmpwi 3, 0
1466 ; EFPU2-NEXT: blt 0, .LBB48_2
1467 ; EFPU2-NEXT: # %bb.1: # %tr
1468 ; EFPU2-NEXT: li 3, 1
1469 ; EFPU2-NEXT: b .LBB48_3
1470 ; EFPU2-NEXT: .LBB48_2: # %fa
1471 ; EFPU2-NEXT: li 3, 0
1472 ; EFPU2-NEXT: .LBB48_3: # %ret
1473 ; EFPU2-NEXT: stw 3, 12(1)
1474 ; EFPU2-NEXT: lwz 3, 12(1)
1475 ; EFPU2-NEXT: lwz 0, 20(1)
1476 ; EFPU2-NEXT: addi 1, 1, 16
1477 ; EFPU2-NEXT: mtlr 0
1478 ; EFPU2-NEXT: blr
1479 entry:
1480 %r = alloca i32, align 4
1481 %c = fcmp uge double %a, %b
1482 br i1 %c, label %tr, label %fa
1483 tr:
1484 store i32 1, ptr %r, align 4
1485 br label %ret
1486 fa:
1487 store i32 0, ptr %r, align 4
1488 br label %ret
1489 ret:
1490 %0 = load i32, ptr %r, align 4
1491 ret i32 %0
1492 }
1494 define double @test_dselect(double %a, double %b, i1 %c) #0 {
1495 ; SPE-LABEL: test_dselect:
1496 ; SPE: # %bb.0: # %entry
1497 ; SPE-NEXT: andi. 7, 7, 1
1498 ; SPE-NEXT: evmergelo 5, 5, 6
1499 ; SPE-NEXT: evmergelo 4, 3, 4
1500 ; SPE-NEXT: bc 12, 1, .LBB49_2
1501 ; SPE-NEXT: # %bb.1: # %entry
1502 ; SPE-NEXT: evor 4, 5, 5
1503 ; SPE-NEXT: .LBB49_2: # %entry
1504 ; SPE-NEXT: evmergehi 3, 4, 4
1505 ; SPE-NEXT: blr
1506 ;
1507 ; EFPU2-LABEL: test_dselect:
1508 ; EFPU2: # %bb.0: # %entry
1509 ; EFPU2-NEXT: andi. 7, 7, 1
1510 ; EFPU2-NEXT: bclr 12, 1, 0
1511 ; EFPU2-NEXT: # %bb.1: # %entry
1512 ; EFPU2-NEXT: ori 3, 5, 0
1513 ; EFPU2-NEXT: ori 4, 6, 0
1514 ; EFPU2-NEXT: blr
1515 entry:
1516 %r = select i1 %c, double %a, double %b
1517 ret double %r
1518 }
1520 define i32 @test_dtoui(double %a) #0 {
1521 ; SPE-LABEL: test_dtoui:
1522 ; SPE: # %bb.0: # %entry
1523 ; SPE-NEXT: evmergelo 3, 3, 4
1524 ; SPE-NEXT: efdctuiz 3, 3
1525 ; SPE-NEXT: blr
1526 ;
1527 ; EFPU2-LABEL: test_dtoui:
1528 ; EFPU2: # %bb.0: # %entry
1529 ; EFPU2-NEXT: mflr 0
1530 ; EFPU2-NEXT: stwu 1, -16(1)
1531 ; EFPU2-NEXT: stw 0, 20(1)
1532 ; EFPU2-NEXT: bl __fixunsdfsi
1533 ; EFPU2-NEXT: lwz 0, 20(1)
1534 ; EFPU2-NEXT: addi 1, 1, 16
1535 ; EFPU2-NEXT: mtlr 0
1536 ; EFPU2-NEXT: blr
1537 entry:
1538 %v = fptoui double %a to i32
1539 ret i32 %v
1540 }
1542 define i32 @test_dtosi(double %a) #0 {
1543 ; SPE-LABEL: test_dtosi:
1544 ; SPE: # %bb.0: # %entry
1545 ; SPE-NEXT: evmergelo 3, 3, 4
1546 ; SPE-NEXT: efdctsiz 3, 3
1547 ; SPE-NEXT: blr
1548 ;
1549 ; EFPU2-LABEL: test_dtosi:
1550 ; EFPU2: # %bb.0: # %entry
1551 ; EFPU2-NEXT: mflr 0
1552 ; EFPU2-NEXT: stwu 1, -16(1)
1553 ; EFPU2-NEXT: stw 0, 20(1)
1554 ; EFPU2-NEXT: bl __fixdfsi
1555 ; EFPU2-NEXT: lwz 0, 20(1)
1556 ; EFPU2-NEXT: addi 1, 1, 16
1557 ; EFPU2-NEXT: mtlr 0
1558 ; EFPU2-NEXT: blr
1559 entry:
1560 %v = fptosi double %a to i32
1561 ret i32 %v
1562 }
1564 define double @test_dfromui(i32 %a) #0 {
1565 ; SPE-LABEL: test_dfromui:
1566 ; SPE: # %bb.0: # %entry
1567 ; SPE-NEXT: efdcfui 4, 3
1568 ; SPE-NEXT: evmergehi 3, 4, 4
1569 ; SPE-NEXT: blr
1570 ;
1571 ; EFPU2-LABEL: test_dfromui:
1572 ; EFPU2: # %bb.0: # %entry
1573 ; EFPU2-NEXT: mflr 0
1574 ; EFPU2-NEXT: stwu 1, -16(1)
1575 ; EFPU2-NEXT: stw 0, 20(1)
1576 ; EFPU2-NEXT: bl __floatunsidf
1577 ; EFPU2-NEXT: lwz 0, 20(1)
1578 ; EFPU2-NEXT: addi 1, 1, 16
1579 ; EFPU2-NEXT: mtlr 0
1580 ; EFPU2-NEXT: blr
1581 entry:
1582 %v = uitofp i32 %a to double
1583 ret double %v
1584 }
1586 define double @test_dfromsi(i32 %a) #0 {
1587 ; SPE-LABEL: test_dfromsi:
1588 ; SPE: # %bb.0: # %entry
1589 ; SPE-NEXT: efdcfsi 4, 3
1590 ; SPE-NEXT: evmergehi 3, 4, 4
1591 ; SPE-NEXT: blr
1592 ;
1593 ; EFPU2-LABEL: test_dfromsi:
1594 ; EFPU2: # %bb.0: # %entry
1595 ; EFPU2-NEXT: mflr 0
1596 ; EFPU2-NEXT: stwu 1, -16(1)
1597 ; EFPU2-NEXT: stw 0, 20(1)
1598 ; EFPU2-NEXT: bl __floatsidf
1599 ; EFPU2-NEXT: lwz 0, 20(1)
1600 ; EFPU2-NEXT: addi 1, 1, 16
1601 ; EFPU2-NEXT: mtlr 0
1602 ; EFPU2-NEXT: blr
1603 entry:
1604 %v = sitofp i32 %a to double
1605 ret double %v
1606 }
1608 declare double @test_spill_spe_regs(double, double);
1609 define dso_local void @test_func2() #0 {
1610 ; CHECK-LABEL: test_func2:
1611 ; CHECK: # %bb.0: # %entry
1612 ; CHECK-NEXT: blr
1613 entry:
1614 ret void
1615 }
1617 declare void @test_memset(ptr nocapture writeonly, i8, i32, i1)
1618 @global_var1 = global i32 0, align 4
1619 define double @test_spill(double %a, i32 %a1, i64 %a2, ptr %a3, ptr %a4, ptr %a5) #0 {
1620 ; SPE-LABEL: test_spill:
1621 ; SPE: # %bb.0: # %entry
1622 ; SPE-NEXT: mflr 0
1623 ; SPE-NEXT: stwu 1, -288(1)
1624 ; SPE-NEXT: li 5, 256
1625 ; SPE-NEXT: stw 0, 292(1)
1626 ; SPE-NEXT: lis 6, .LCPI55_0@ha
1627 ; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill
1628 ; SPE-NEXT: li 5, .LCPI55_0@l
1629 ; SPE-NEXT: evlddx 5, 6, 5
1630 ; SPE-NEXT: stw 31, 284(1) # 4-byte Folded Spill
1631 ; SPE-NEXT: evstdd 14, 128(1) # 8-byte Folded Spill
1632 ; SPE-NEXT: evstdd 15, 136(1) # 8-byte Folded Spill
1633 ; SPE-NEXT: evstdd 16, 144(1) # 8-byte Folded Spill
1634 ; SPE-NEXT: evstdd 17, 152(1) # 8-byte Folded Spill
1635 ; SPE-NEXT: evstdd 18, 160(1) # 8-byte Folded Spill
1636 ; SPE-NEXT: evstdd 19, 168(1) # 8-byte Folded Spill
1637 ; SPE-NEXT: evstdd 20, 176(1) # 8-byte Folded Spill
1638 ; SPE-NEXT: evstdd 21, 184(1) # 8-byte Folded Spill
1639 ; SPE-NEXT: evstdd 22, 192(1) # 8-byte Folded Spill
1640 ; SPE-NEXT: evstdd 23, 200(1) # 8-byte Folded Spill
1641 ; SPE-NEXT: evstdd 24, 208(1) # 8-byte Folded Spill
1642 ; SPE-NEXT: evstdd 25, 216(1) # 8-byte Folded Spill
1643 ; SPE-NEXT: evstdd 26, 224(1) # 8-byte Folded Spill
1644 ; SPE-NEXT: evstdd 27, 232(1) # 8-byte Folded Spill
1645 ; SPE-NEXT: evstdd 28, 240(1) # 8-byte Folded Spill
1646 ; SPE-NEXT: evstdd 29, 248(1) # 8-byte Folded Spill
1647 ; SPE-NEXT: evmergelo 3, 3, 4
1648 ; SPE-NEXT: lwz 4, 296(1)
1649 ; SPE-NEXT: efdadd 3, 3, 3
1650 ; SPE-NEXT: efdadd 3, 3, 5
1651 ; SPE-NEXT: evstdd 3, 24(1) # 8-byte Folded Spill
1652 ; SPE-NEXT: stw 4, 20(1) # 4-byte Folded Spill
1653 ; SPE-NEXT: #APP
1654 ; SPE-NEXT: #NO_APP
1655 ; SPE-NEXT: addi 3, 1, 76
1656 ; SPE-NEXT: li 4, 0
1657 ; SPE-NEXT: li 5, 24
1658 ; SPE-NEXT: li 6, 1
1659 ; SPE-NEXT: li 30, 0
1660 ; SPE-NEXT: bl test_memset
1661 ; SPE-NEXT: lwz 3, 20(1) # 4-byte Folded Reload
1662 ; SPE-NEXT: stw 30, 0(3)
1663 ; SPE-NEXT: bl test_func2
1664 ; SPE-NEXT: addi 3, 1, 32
1665 ; SPE-NEXT: li 4, 0
1666 ; SPE-NEXT: li 5, 20
1667 ; SPE-NEXT: li 6, 1
1668 ; SPE-NEXT: bl test_memset
1669 ; SPE-NEXT: evldd 4, 24(1) # 8-byte Folded Reload
1670 ; SPE-NEXT: li 5, 256
1671 ; SPE-NEXT: evmergehi 3, 4, 4
1672 ; SPE-NEXT: evlddx 30, 1, 5 # 8-byte Folded Reload
1673 ; SPE-NEXT: evldd 29, 248(1) # 8-byte Folded Reload
1674 ; SPE-NEXT: evldd 28, 240(1) # 8-byte Folded Reload
1675 ; SPE-NEXT: evldd 27, 232(1) # 8-byte Folded Reload
1676 ; SPE-NEXT: evldd 26, 224(1) # 8-byte Folded Reload
1677 ; SPE-NEXT: evldd 25, 216(1) # 8-byte Folded Reload
1678 ; SPE-NEXT: evldd 24, 208(1) # 8-byte Folded Reload
1679 ; SPE-NEXT: evldd 23, 200(1) # 8-byte Folded Reload
1680 ; SPE-NEXT: evldd 22, 192(1) # 8-byte Folded Reload
1681 ; SPE-NEXT: evldd 21, 184(1) # 8-byte Folded Reload
1682 ; SPE-NEXT: evldd 20, 176(1) # 8-byte Folded Reload
1683 ; SPE-NEXT: evldd 19, 168(1) # 8-byte Folded Reload
1684 ; SPE-NEXT: evldd 18, 160(1) # 8-byte Folded Reload
1685 ; SPE-NEXT: evldd 17, 152(1) # 8-byte Folded Reload
1686 ; SPE-NEXT: evldd 16, 144(1) # 8-byte Folded Reload
1687 ; SPE-NEXT: evldd 15, 136(1) # 8-byte Folded Reload
1688 ; SPE-NEXT: evldd 14, 128(1) # 8-byte Folded Reload
1689 ; SPE-NEXT: lwz 31, 284(1) # 4-byte Folded Reload
1690 ; SPE-NEXT: lwz 0, 292(1)
1691 ; SPE-NEXT: addi 1, 1, 288
1692 ; SPE-NEXT: mtlr 0
1693 ; SPE-NEXT: blr
1694 ;
1695 ; EFPU2-LABEL: test_spill:
1696 ; EFPU2: # %bb.0: # %entry
1697 ; EFPU2-NEXT: mflr 0
1698 ; EFPU2-NEXT: stwu 1, -128(1)
1699 ; EFPU2-NEXT: mr 5, 3
1700 ; EFPU2-NEXT: mr 6, 4
1701 ; EFPU2-NEXT: stw 0, 132(1)
1702 ; EFPU2-NEXT: stw 27, 108(1) # 4-byte Folded Spill
1703 ; EFPU2-NEXT: stw 28, 112(1) # 4-byte Folded Spill
1704 ; EFPU2-NEXT: stw 29, 116(1) # 4-byte Folded Spill
1705 ; EFPU2-NEXT: stw 30, 120(1) # 4-byte Folded Spill
1706 ; EFPU2-NEXT: lwz 28, 136(1)
1707 ; EFPU2-NEXT: bl __adddf3
1708 ; EFPU2-NEXT: lis 5, 16393
1709 ; EFPU2-NEXT: lis 6, -4069
1710 ; EFPU2-NEXT: ori 5, 5, 8697
1711 ; EFPU2-NEXT: ori 6, 6, 34414
1712 ; EFPU2-NEXT: #APP
1713 ; EFPU2-NEXT: #NO_APP
1714 ; EFPU2-NEXT: bl __adddf3
1715 ; EFPU2-NEXT: mr 30, 3
1716 ; EFPU2-NEXT: mr 29, 4
1717 ; EFPU2-NEXT: addi 3, 1, 56
1718 ; EFPU2-NEXT: li 4, 0
1719 ; EFPU2-NEXT: li 5, 24
1720 ; EFPU2-NEXT: li 6, 1
1721 ; EFPU2-NEXT: li 27, 0
1722 ; EFPU2-NEXT: bl test_memset
1723 ; EFPU2-NEXT: stw 27, 0(28)
1724 ; EFPU2-NEXT: bl test_func2
1725 ; EFPU2-NEXT: addi 3, 1, 12
1726 ; EFPU2-NEXT: li 4, 0
1727 ; EFPU2-NEXT: li 5, 20
1728 ; EFPU2-NEXT: li 6, 1
1729 ; EFPU2-NEXT: bl test_memset
1730 ; EFPU2-NEXT: mr 3, 30
1731 ; EFPU2-NEXT: mr 4, 29
1732 ; EFPU2-NEXT: lwz 30, 120(1) # 4-byte Folded Reload
1733 ; EFPU2-NEXT: lwz 29, 116(1) # 4-byte Folded Reload
1734 ; EFPU2-NEXT: lwz 28, 112(1) # 4-byte Folded Reload
1735 ; EFPU2-NEXT: lwz 27, 108(1) # 4-byte Folded Reload
1736 ; EFPU2-NEXT: lwz 0, 132(1)
1737 ; EFPU2-NEXT: addi 1, 1, 128
1738 ; EFPU2-NEXT: mtlr 0
1739 ; EFPU2-NEXT: blr
1740 entry:
1741 %v1 = alloca [13 x i32], align 4
1742 %v2 = alloca [11 x i32], align 4
1743 %0 = fadd double %a, %a
1744 call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
1745 %1 = fadd double %0, 3.14159
1746 call void @test_memset(ptr align 4 %v1, i8 0, i32 24, i1 true)
1747 store i32 0, ptr %a5, align 4
1748 call void @test_func2()
1749 call void @test_memset(ptr align 4 %v2, i8 0, i32 20, i1 true)
1750 br label %return
1752 return:
1753 ret double %1
1755 }
1757 define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
1758 ; CHECK-LABEL: test_fma:
1759 ; CHECK: # %bb.0: # %entry
1760 ; CHECK-NEXT: mflr 0
1761 ; CHECK-NEXT: stwu 1, -32(1)
1762 ; CHECK-NEXT: cmpwi 3, 0
1763 ; CHECK-NEXT: stw 0, 36(1)
1764 ; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill
1765 ; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill
1766 ; CHECK-NEXT: ble 0, .LBB56_3
1767 ; CHECK-NEXT: # %bb.1: # %for.body.preheader
1768 ; CHECK-NEXT: mr 30, 3
1769 ; CHECK-NEXT: li 29, 0
1770 ; CHECK-NEXT: # implicit-def: $r5
1771 ; CHECK-NEXT: .LBB56_2: # %for.body
1772 ; CHECK-NEXT: #
1773 ; CHECK-NEXT: efscfsi 3, 29
1774 ; CHECK-NEXT: mr 4, 3
1775 ; CHECK-NEXT: bl fmaf
1776 ; CHECK-NEXT: addi 30, 30, -1
1777 ; CHECK-NEXT: mr 5, 3
1778 ; CHECK-NEXT: cmplwi 30, 0
1779 ; CHECK-NEXT: addi 29, 29, 1
1780 ; CHECK-NEXT: bc 12, 1, .LBB56_2
1781 ; CHECK-NEXT: b .LBB56_4
1782 ; CHECK-NEXT: .LBB56_3:
1783 ; CHECK-NEXT: # implicit-def: $r5
1784 ; CHECK-NEXT: .LBB56_4: # %for.cond.cleanup
1785 ; CHECK-NEXT: mr 3, 5
1786 ; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
1787 ; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
1788 ; CHECK-NEXT: lwz 0, 36(1)
1789 ; CHECK-NEXT: addi 1, 1, 32
1790 ; CHECK-NEXT: mtlr 0
1791 ; CHECK-NEXT: blr
1792 entry:
1793 %cmp8 = icmp sgt i32 %d, 0
1794 br i1 %cmp8, label %for.body, label %for.cond.cleanup
1796 for.cond.cleanup: ; preds = %for.body, %entry
1797 %e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ]
1798 ret float %e.0.lcssa
1800 for.body: ; preds = %for.body, %entry
1801 %f.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
1802 %e.09 = phi float [ %0, %for.body ], [ undef, %entry ]
1803 %conv = sitofp i32 %f.010 to float
1804 %0 = tail call float @llvm.fma.f32(float %conv, float %conv, float %e.09)
1805 %inc = add nuw nsw i32 %f.010, 1
1806 %exitcond = icmp eq i32 %inc, %d
1807 br i1 %exitcond, label %for.cond.cleanup, label %for.body
1808 }
1810 ; Function Attrs: nounwind readnone speculatable willreturn
1811 declare float @llvm.fma.f32(float, float, float) #1
1813 attributes #1 = { nounwind readnone speculatable willreturn }
1815 %struct.a = type { float, float }
1817 declare i32 @foo(double)
1819 define void @d(ptr %e, ptr %f) #0 {
1820 ; SPE-LABEL: d:
1821 ; SPE: # %bb.0: # %entry
1822 ; SPE-NEXT: mflr 0
1823 ; SPE-NEXT: stwu 1, -48(1)
1824 ; SPE-NEXT: stw 0, 52(1)
1825 ; SPE-NEXT: lwz 4, 0(4)
1826 ; SPE-NEXT: lwz 3, 0(3)
1827 ; SPE-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
1828 ; SPE-NEXT: efdcfs 29, 4
1829 ; SPE-NEXT: stw 28, 32(1) # 4-byte Folded Spill
1830 ; SPE-NEXT: mr 4, 29
1831 ; SPE-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
1832 ; SPE-NEXT: efdcfs 30, 3
1833 ; SPE-NEXT: evmergehi 3, 29, 29
1834 ; SPE-NEXT: bl foo
1835 ; SPE-NEXT: mr 28, 3
1836 ; SPE-NEXT: evmergehi 3, 30, 30
1837 ; SPE-NEXT: mr 4, 30
1838 ; SPE-NEXT: bl foo
1839 ; SPE-NEXT: efdcfsi 3, 28
1840 ; SPE-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
1841 ; SPE-NEXT: efdmul 3, 29, 3
1842 ; SPE-NEXT: efscfd 3, 3
1843 ; SPE-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
1844 ; SPE-NEXT: stw 3, 0(3)
1845 ; SPE-NEXT: lwz 28, 32(1) # 4-byte Folded Reload
1846 ; SPE-NEXT: lwz 0, 52(1)
1847 ; SPE-NEXT: addi 1, 1, 48
1848 ; SPE-NEXT: mtlr 0
1849 ; SPE-NEXT: blr
1850 ;
1851 ; EFPU2-LABEL: d:
1852 ; EFPU2: # %bb.0: # %entry
1853 ; EFPU2-NEXT: mflr 0
1854 ; EFPU2-NEXT: stwu 1, -32(1)
1855 ; EFPU2-NEXT: stw 0, 36(1)
1856 ; EFPU2-NEXT: lwz 3, 0(3)
1857 ; EFPU2-NEXT: stw 26, 8(1) # 4-byte Folded Spill
1858 ; EFPU2-NEXT: stw 27, 12(1) # 4-byte Folded Spill
1859 ; EFPU2-NEXT: stw 28, 16(1) # 4-byte Folded Spill
1860 ; EFPU2-NEXT: stw 29, 20(1) # 4-byte Folded Spill
1861 ; EFPU2-NEXT: stw 30, 24(1) # 4-byte Folded Spill
1862 ; EFPU2-NEXT: mr 30, 4
1863 ; EFPU2-NEXT: bl __extendsfdf2
1864 ; EFPU2-NEXT: mr 28, 3
1865 ; EFPU2-NEXT: lwz 3, 0(30)
1866 ; EFPU2-NEXT: mr 29, 4
1867 ; EFPU2-NEXT: bl __extendsfdf2
1868 ; EFPU2-NEXT: mr 30, 4
1869 ; EFPU2-NEXT: mr 27, 3
1870 ; EFPU2-NEXT: bl foo
1871 ; EFPU2-NEXT: mr 26, 3
1872 ; EFPU2-NEXT: mr 3, 28
1873 ; EFPU2-NEXT: mr 4, 29
1874 ; EFPU2-NEXT: bl foo
1875 ; EFPU2-NEXT: mr 3, 26
1876 ; EFPU2-NEXT: bl __floatsidf
1877 ; EFPU2-NEXT: mr 6, 4
1878 ; EFPU2-NEXT: mr 5, 3
1879 ; EFPU2-NEXT: mr 3, 27
1880 ; EFPU2-NEXT: mr 4, 30
1881 ; EFPU2-NEXT: bl __muldf3
1882 ; EFPU2-NEXT: bl __truncdfsf2
1883 ; EFPU2-NEXT: stw 3, 0(3)
1884 ; EFPU2-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
1885 ; EFPU2-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
1886 ; EFPU2-NEXT: lwz 28, 16(1) # 4-byte Folded Reload
1887 ; EFPU2-NEXT: lwz 27, 12(1) # 4-byte Folded Reload
1888 ; EFPU2-NEXT: lwz 26, 8(1) # 4-byte Folded Reload
1889 ; EFPU2-NEXT: lwz 0, 36(1)
1890 ; EFPU2-NEXT: addi 1, 1, 32
1891 ; EFPU2-NEXT: mtlr 0
1892 ; EFPU2-NEXT: blr
1893 entry:
1894 %0 = load float, ptr undef
1895 %conv = fpext float %0 to double
1896 %1 = load float, ptr %f
1897 %g = fpext float %1 to double
1898 %2 = call i32 @foo(double %g)
1899 %h = call i32 @foo(double %conv)
1900 %n = sitofp i32 %2 to double
1901 %k = fmul double %g, %n
1902 %l = fptrunc double %k to float
1903 store float %l, ptr undef
1904 ret void
1905 }
1906 attributes #0 = { nounwind }