| blob | 4b19cb30aba2a9086b33e6df806e0b9df9c21fcc |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
3 ; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
4 ; RUN: -check-prefix=CHECK-LE %s
5 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
6 ; RUN: -mtriple=powerpc64-linux-gnu < %s | FileCheck \
7 ; RUN: -check-prefix=CHECK-BE %s
8 ; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
9 ; RUN: -mtriple=powerpc-linux-gnu < %s | FileCheck \
10 ; RUN: -check-prefix=CHECK-32 %s
12 ; Free probe
13 define i8 @f0() #0 nounwind {
14 ; CHECK-LE-LABEL: f0:
15 ; CHECK-LE: # %bb.0: # %entry
16 ; CHECK-LE-NEXT: li r3, 3
17 ; CHECK-LE-NEXT: stb r3, -64(r1)
18 ; CHECK-LE-NEXT: lbz r3, -64(r1)
19 ; CHECK-LE-NEXT: blr
20 ;
21 ; CHECK-BE-LABEL: f0:
22 ; CHECK-BE: # %bb.0: # %entry
23 ; CHECK-BE-NEXT: li r3, 3
24 ; CHECK-BE-NEXT: stb r3, -64(r1)
25 ; CHECK-BE-NEXT: lbz r3, -64(r1)
26 ; CHECK-BE-NEXT: blr
27 ;
28 ; CHECK-32-LABEL: f0:
29 ; CHECK-32: # %bb.0: # %entry
30 ; CHECK-32-NEXT: stwu r1, -80(r1)
31 ; CHECK-32-NEXT: li r3, 3
32 ; CHECK-32-NEXT: stb r3, 16(r1)
33 ; CHECK-32-NEXT: lbz r3, 16(r1)
34 ; CHECK-32-NEXT: addi r1, r1, 80
35 ; CHECK-32-NEXT: blr
36 entry:
37 %a = alloca i8, i64 64
38 %b = getelementptr inbounds i8, ptr %a, i64 63
39 store volatile i8 3, ptr %a
40 %c = load volatile i8, ptr %a
41 ret i8 %c
42 }
44 define i8 @f1() #0 "stack-probe-size"="0" {
45 ; CHECK-LE-LABEL: f1:
46 ; CHECK-LE: # %bb.0: # %entry
47 ; CHECK-LE-NEXT: mr r0, r1
48 ; CHECK-LE-NEXT: .cfi_def_cfa r0, 0
49 ; CHECK-LE-NEXT: li r12, 259
50 ; CHECK-LE-NEXT: mtctr r12
51 ; CHECK-LE-NEXT: .LBB1_1: # %entry
52 ; CHECK-LE-NEXT: #
53 ; CHECK-LE-NEXT: stdu r0, -16(r1)
54 ; CHECK-LE-NEXT: bdnz .LBB1_1
55 ; CHECK-LE-NEXT: # %bb.2: # %entry
56 ; CHECK-LE-NEXT: .cfi_def_cfa_register r1
57 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 4144
58 ; CHECK-LE-NEXT: li r3, 3
59 ; CHECK-LE-NEXT: stb r3, 48(r1)
60 ; CHECK-LE-NEXT: lbz r3, 48(r1)
61 ; CHECK-LE-NEXT: addi r1, r1, 4144
62 ; CHECK-LE-NEXT: blr
63 ;
64 ; CHECK-BE-LABEL: f1:
65 ; CHECK-BE: # %bb.0: # %entry
66 ; CHECK-BE-NEXT: mr r0, r1
67 ; CHECK-BE-NEXT: .cfi_def_cfa r0, 0
68 ; CHECK-BE-NEXT: li r12, 260
69 ; CHECK-BE-NEXT: mtctr r12
70 ; CHECK-BE-NEXT: .LBB1_1: # %entry
71 ; CHECK-BE-NEXT: #
72 ; CHECK-BE-NEXT: stdu r0, -16(r1)
73 ; CHECK-BE-NEXT: bdnz .LBB1_1
74 ; CHECK-BE-NEXT: # %bb.2: # %entry
75 ; CHECK-BE-NEXT: .cfi_def_cfa_register r1
76 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 4160
77 ; CHECK-BE-NEXT: li r3, 3
78 ; CHECK-BE-NEXT: stb r3, 64(r1)
79 ; CHECK-BE-NEXT: lbz r3, 64(r1)
80 ; CHECK-BE-NEXT: addi r1, r1, 4160
81 ; CHECK-BE-NEXT: blr
82 ;
83 ; CHECK-32-LABEL: f1:
84 ; CHECK-32: # %bb.0: # %entry
85 ; CHECK-32-NEXT: mr r0, r1
86 ; CHECK-32-NEXT: .cfi_def_cfa r0, 0
87 ; CHECK-32-NEXT: li r12, 257
88 ; CHECK-32-NEXT: mtctr r12
89 ; CHECK-32-NEXT: .LBB1_1: # %entry
90 ; CHECK-32-NEXT: #
91 ; CHECK-32-NEXT: stwu r0, -16(r1)
92 ; CHECK-32-NEXT: bdnz .LBB1_1
93 ; CHECK-32-NEXT: # %bb.2: # %entry
94 ; CHECK-32-NEXT: .cfi_def_cfa_register r1
95 ; CHECK-32-NEXT: sub r0, r1, r0
96 ; CHECK-32-NEXT: sub r0, r1, r0
97 ; CHECK-32-NEXT: .cfi_def_cfa_offset 4112
98 ; CHECK-32-NEXT: li r3, 3
99 ; CHECK-32-NEXT: stb r3, 16(r1)
100 ; CHECK-32-NEXT: lbz r3, 16(r1)
101 ; CHECK-32-NEXT: addi r1, r1, 4112
102 ; CHECK-32-NEXT: blr
103 entry:
104 %a = alloca i8, i64 4096
105 %b = getelementptr inbounds i8, ptr %a, i64 63
106 store volatile i8 3, ptr %a
107 %c = load volatile i8, ptr %a
108 ret i8 %c
109 }
111 define i8 @f2() #0 {
112 ; CHECK-LE-LABEL: f2:
113 ; CHECK-LE: # %bb.0: # %entry
114 ; CHECK-LE-NEXT: mr r0, r1
115 ; CHECK-LE-NEXT: .cfi_def_cfa r0, 0
116 ; CHECK-LE-NEXT: stdu r0, -48(r1)
117 ; CHECK-LE-NEXT: li r12, 16
118 ; CHECK-LE-NEXT: mtctr r12
119 ; CHECK-LE-NEXT: .LBB2_1: # %entry
120 ; CHECK-LE-NEXT: #
121 ; CHECK-LE-NEXT: stdu r0, -4096(r1)
122 ; CHECK-LE-NEXT: bdnz .LBB2_1
123 ; CHECK-LE-NEXT: # %bb.2: # %entry
124 ; CHECK-LE-NEXT: .cfi_def_cfa_register r1
125 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 65584
126 ; CHECK-LE-NEXT: li r3, 3
127 ; CHECK-LE-NEXT: stb r3, 48(r1)
128 ; CHECK-LE-NEXT: lbz r3, 48(r1)
129 ; CHECK-LE-NEXT: ld r1, 0(r1)
130 ; CHECK-LE-NEXT: blr
131 ;
132 ; CHECK-BE-LABEL: f2:
133 ; CHECK-BE: # %bb.0: # %entry
134 ; CHECK-BE-NEXT: mr r0, r1
135 ; CHECK-BE-NEXT: .cfi_def_cfa r0, 0
136 ; CHECK-BE-NEXT: stdu r0, -64(r1)
137 ; CHECK-BE-NEXT: li r12, 16
138 ; CHECK-BE-NEXT: mtctr r12
139 ; CHECK-BE-NEXT: .LBB2_1: # %entry
140 ; CHECK-BE-NEXT: #
141 ; CHECK-BE-NEXT: stdu r0, -4096(r1)
142 ; CHECK-BE-NEXT: bdnz .LBB2_1
143 ; CHECK-BE-NEXT: # %bb.2: # %entry
144 ; CHECK-BE-NEXT: .cfi_def_cfa_register r1
145 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 65600
146 ; CHECK-BE-NEXT: li r3, 3
147 ; CHECK-BE-NEXT: stb r3, 64(r1)
148 ; CHECK-BE-NEXT: lbz r3, 64(r1)
149 ; CHECK-BE-NEXT: ld r1, 0(r1)
150 ; CHECK-BE-NEXT: blr
151 ;
152 ; CHECK-32-LABEL: f2:
153 ; CHECK-32: # %bb.0: # %entry
154 ; CHECK-32-NEXT: mr r0, r1
155 ; CHECK-32-NEXT: .cfi_def_cfa r0, 0
156 ; CHECK-32-NEXT: stwu r0, -16(r1)
157 ; CHECK-32-NEXT: li r12, 16
158 ; CHECK-32-NEXT: mtctr r12
159 ; CHECK-32-NEXT: .LBB2_1: # %entry
160 ; CHECK-32-NEXT: #
161 ; CHECK-32-NEXT: stwu r0, -4096(r1)
162 ; CHECK-32-NEXT: bdnz .LBB2_1
163 ; CHECK-32-NEXT: # %bb.2: # %entry
164 ; CHECK-32-NEXT: .cfi_def_cfa_register r1
165 ; CHECK-32-NEXT: sub r0, r1, r0
166 ; CHECK-32-NEXT: sub r0, r1, r0
167 ; CHECK-32-NEXT: .cfi_def_cfa_offset 65552
168 ; CHECK-32-NEXT: li r3, 3
169 ; CHECK-32-NEXT: stb r3, 16(r1)
170 ; CHECK-32-NEXT: mr r0, r31
171 ; CHECK-32-NEXT: lbz r3, 16(r1)
172 ; CHECK-32-NEXT: lwz r31, 0(r1)
173 ; CHECK-32-NEXT: mr r1, r31
174 ; CHECK-32-NEXT: mr r31, r0
175 ; CHECK-32-NEXT: blr
176 entry:
177 %a = alloca i8, i64 65536
178 %b = getelementptr inbounds i8, ptr %a, i64 63
179 store volatile i8 3, ptr %a
180 %c = load volatile i8, ptr %a
181 ret i8 %c
182 }
184 define i8 @f3() #0 "stack-probe-size"="32768" {
185 ; CHECK-LE-LABEL: f3:
186 ; CHECK-LE: # %bb.0: # %entry
187 ; CHECK-LE-NEXT: mr r0, r1
188 ; CHECK-LE-NEXT: .cfi_def_cfa r0, 0
189 ; CHECK-LE-NEXT: stdu r0, -48(r1)
190 ; CHECK-LE-NEXT: stdu r0, -32768(r1)
191 ; CHECK-LE-NEXT: stdu r0, -32768(r1)
192 ; CHECK-LE-NEXT: .cfi_def_cfa_register r1
193 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 65584
194 ; CHECK-LE-NEXT: li r3, 3
195 ; CHECK-LE-NEXT: stb r3, 48(r1)
196 ; CHECK-LE-NEXT: lbz r3, 48(r1)
197 ; CHECK-LE-NEXT: ld r1, 0(r1)
198 ; CHECK-LE-NEXT: blr
199 ;
200 ; CHECK-BE-LABEL: f3:
201 ; CHECK-BE: # %bb.0: # %entry
202 ; CHECK-BE-NEXT: mr r0, r1
203 ; CHECK-BE-NEXT: .cfi_def_cfa r0, 0
204 ; CHECK-BE-NEXT: stdu r0, -64(r1)
205 ; CHECK-BE-NEXT: stdu r0, -32768(r1)
206 ; CHECK-BE-NEXT: stdu r0, -32768(r1)
207 ; CHECK-BE-NEXT: .cfi_def_cfa_register r1
208 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 65600
209 ; CHECK-BE-NEXT: li r3, 3
210 ; CHECK-BE-NEXT: stb r3, 64(r1)
211 ; CHECK-BE-NEXT: lbz r3, 64(r1)
212 ; CHECK-BE-NEXT: ld r1, 0(r1)
213 ; CHECK-BE-NEXT: blr
214 ;
215 ; CHECK-32-LABEL: f3:
216 ; CHECK-32: # %bb.0: # %entry
217 ; CHECK-32-NEXT: mr r0, r1
218 ; CHECK-32-NEXT: .cfi_def_cfa r0, 0
219 ; CHECK-32-NEXT: stwu r0, -16(r1)
220 ; CHECK-32-NEXT: stwu r0, -32768(r1)
221 ; CHECK-32-NEXT: stwu r0, -32768(r1)
222 ; CHECK-32-NEXT: .cfi_def_cfa_register r1
223 ; CHECK-32-NEXT: sub r0, r1, r0
224 ; CHECK-32-NEXT: sub r0, r1, r0
225 ; CHECK-32-NEXT: .cfi_def_cfa_offset 65552
226 ; CHECK-32-NEXT: li r3, 3
227 ; CHECK-32-NEXT: stb r3, 16(r1)
228 ; CHECK-32-NEXT: mr r0, r31
229 ; CHECK-32-NEXT: lbz r3, 16(r1)
230 ; CHECK-32-NEXT: lwz r31, 0(r1)
231 ; CHECK-32-NEXT: mr r1, r31
232 ; CHECK-32-NEXT: mr r31, r0
233 ; CHECK-32-NEXT: blr
234 entry:
235 %a = alloca i8, i64 65536
236 %b = getelementptr inbounds i8, ptr %a, i64 63
237 store volatile i8 3, ptr %a
238 %c = load volatile i8, ptr %a
239 ret i8 %c
240 }
242 ; Same as f2, but without protection.
243 define i8 @f4() {
244 ; CHECK-LE-LABEL: f4:
245 ; CHECK-LE: # %bb.0: # %entry
246 ; CHECK-LE-NEXT: lis r0, -2
247 ; CHECK-LE-NEXT: ori r0, r0, 65488
248 ; CHECK-LE-NEXT: stdux r1, r1, r0
249 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 65584
250 ; CHECK-LE-NEXT: li r3, 3
251 ; CHECK-LE-NEXT: stb r3, 48(r1)
252 ; CHECK-LE-NEXT: lbz r3, 48(r1)
253 ; CHECK-LE-NEXT: ld r1, 0(r1)
254 ; CHECK-LE-NEXT: blr
255 ;
256 ; CHECK-BE-LABEL: f4:
257 ; CHECK-BE: # %bb.0: # %entry
258 ; CHECK-BE-NEXT: lis r0, -2
259 ; CHECK-BE-NEXT: ori r0, r0, 65472
260 ; CHECK-BE-NEXT: stdux r1, r1, r0
261 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 65600
262 ; CHECK-BE-NEXT: li r3, 3
263 ; CHECK-BE-NEXT: stb r3, 64(r1)
264 ; CHECK-BE-NEXT: lbz r3, 64(r1)
265 ; CHECK-BE-NEXT: ld r1, 0(r1)
266 ; CHECK-BE-NEXT: blr
267 ;
268 ; CHECK-32-LABEL: f4:
269 ; CHECK-32: # %bb.0: # %entry
270 ; CHECK-32-NEXT: lis r0, -2
271 ; CHECK-32-NEXT: ori r0, r0, 65520
272 ; CHECK-32-NEXT: stwux r1, r1, r0
273 ; CHECK-32-NEXT: sub r0, r1, r0
274 ; CHECK-32-NEXT: .cfi_def_cfa_offset 65552
275 ; CHECK-32-NEXT: li r3, 3
276 ; CHECK-32-NEXT: stb r3, 16(r1)
277 ; CHECK-32-NEXT: mr r0, r31
278 ; CHECK-32-NEXT: lbz r3, 16(r1)
279 ; CHECK-32-NEXT: lwz r31, 0(r1)
280 ; CHECK-32-NEXT: mr r1, r31
281 ; CHECK-32-NEXT: mr r31, r0
282 ; CHECK-32-NEXT: blr
283 entry:
284 %a = alloca i8, i64 65536
285 %b = getelementptr inbounds i8, ptr %a, i64 63
286 store volatile i8 3, ptr %a
287 %c = load volatile i8, ptr %a
288 ret i8 %c
289 }
291 define i8 @f5() #0 "stack-probe-size"="65536" {
292 ; CHECK-LE-LABEL: f5:
293 ; CHECK-LE: # %bb.0: # %entry
294 ; CHECK-LE-NEXT: mr r0, r1
295 ; CHECK-LE-NEXT: .cfi_def_cfa r0, 0
296 ; CHECK-LE-NEXT: stdu r0, -48(r1)
297 ; CHECK-LE-NEXT: li r12, 16
298 ; CHECK-LE-NEXT: mtctr r12
299 ; CHECK-LE-NEXT: lis r12, -1
300 ; CHECK-LE-NEXT: ori r12, r12, 0
301 ; CHECK-LE-NEXT: .LBB5_1: # %entry
302 ; CHECK-LE-NEXT: #
303 ; CHECK-LE-NEXT: stdux r0, r1, r12
304 ; CHECK-LE-NEXT: bdnz .LBB5_1
305 ; CHECK-LE-NEXT: # %bb.2: # %entry
306 ; CHECK-LE-NEXT: .cfi_def_cfa_register r1
307 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 1048624
308 ; CHECK-LE-NEXT: li r3, 3
309 ; CHECK-LE-NEXT: stb r3, 48(r1)
310 ; CHECK-LE-NEXT: lbz r3, 48(r1)
311 ; CHECK-LE-NEXT: ld r1, 0(r1)
312 ; CHECK-LE-NEXT: blr
313 ;
314 ; CHECK-BE-LABEL: f5:
315 ; CHECK-BE: # %bb.0: # %entry
316 ; CHECK-BE-NEXT: mr r0, r1
317 ; CHECK-BE-NEXT: .cfi_def_cfa r0, 0
318 ; CHECK-BE-NEXT: stdu r0, -64(r1)
319 ; CHECK-BE-NEXT: li r12, 16
320 ; CHECK-BE-NEXT: mtctr r12
321 ; CHECK-BE-NEXT: lis r12, -1
322 ; CHECK-BE-NEXT: ori r12, r12, 0
323 ; CHECK-BE-NEXT: .LBB5_1: # %entry
324 ; CHECK-BE-NEXT: #
325 ; CHECK-BE-NEXT: stdux r0, r1, r12
326 ; CHECK-BE-NEXT: bdnz .LBB5_1
327 ; CHECK-BE-NEXT: # %bb.2: # %entry
328 ; CHECK-BE-NEXT: .cfi_def_cfa_register r1
329 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 1048640
330 ; CHECK-BE-NEXT: li r3, 3
331 ; CHECK-BE-NEXT: stb r3, 64(r1)
332 ; CHECK-BE-NEXT: lbz r3, 64(r1)
333 ; CHECK-BE-NEXT: ld r1, 0(r1)
334 ; CHECK-BE-NEXT: blr
335 ;
336 ; CHECK-32-LABEL: f5:
337 ; CHECK-32: # %bb.0: # %entry
338 ; CHECK-32-NEXT: mr r0, r1
339 ; CHECK-32-NEXT: .cfi_def_cfa r0, 0
340 ; CHECK-32-NEXT: stwu r0, -16(r1)
341 ; CHECK-32-NEXT: li r12, 16
342 ; CHECK-32-NEXT: mtctr r12
343 ; CHECK-32-NEXT: lis r12, -1
344 ; CHECK-32-NEXT: ori r12, r12, 0
345 ; CHECK-32-NEXT: .LBB5_1: # %entry
346 ; CHECK-32-NEXT: #
347 ; CHECK-32-NEXT: stwux r0, r1, r12
348 ; CHECK-32-NEXT: bdnz .LBB5_1
349 ; CHECK-32-NEXT: # %bb.2: # %entry
350 ; CHECK-32-NEXT: .cfi_def_cfa_register r1
351 ; CHECK-32-NEXT: sub r0, r1, r0
352 ; CHECK-32-NEXT: sub r0, r1, r0
353 ; CHECK-32-NEXT: .cfi_def_cfa_offset 1048592
354 ; CHECK-32-NEXT: li r3, 3
355 ; CHECK-32-NEXT: stb r3, 16(r1)
356 ; CHECK-32-NEXT: mr r0, r31
357 ; CHECK-32-NEXT: lbz r3, 16(r1)
358 ; CHECK-32-NEXT: lwz r31, 0(r1)
359 ; CHECK-32-NEXT: mr r1, r31
360 ; CHECK-32-NEXT: mr r31, r0
361 ; CHECK-32-NEXT: blr
362 entry:
363 %a = alloca i8, i64 1048576
364 %b = getelementptr inbounds i8, ptr %a, i64 63
365 store volatile i8 3, ptr %a
366 %c = load volatile i8, ptr %a
367 ret i8 %c
368 }
370 define i8 @f6() #0 {
371 ; CHECK-LE-LABEL: f6:
372 ; CHECK-LE: # %bb.0: # %entry
373 ; CHECK-LE-NEXT: mr r0, r1
374 ; CHECK-LE-NEXT: .cfi_def_cfa r0, 0
375 ; CHECK-LE-NEXT: stdu r0, -48(r1)
376 ; CHECK-LE-NEXT: lis r12, 4
377 ; CHECK-LE-NEXT: ori r12, r12, 0
378 ; CHECK-LE-NEXT: mtctr r12
379 ; CHECK-LE-NEXT: .LBB6_1: # %entry
380 ; CHECK-LE-NEXT: #
381 ; CHECK-LE-NEXT: stdu r0, -4096(r1)
382 ; CHECK-LE-NEXT: bdnz .LBB6_1
383 ; CHECK-LE-NEXT: # %bb.2: # %entry
384 ; CHECK-LE-NEXT: .cfi_def_cfa_register r1
385 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 1073741872
386 ; CHECK-LE-NEXT: li r3, 3
387 ; CHECK-LE-NEXT: stb r3, 48(r1)
388 ; CHECK-LE-NEXT: lbz r3, 48(r1)
389 ; CHECK-LE-NEXT: ld r1, 0(r1)
390 ; CHECK-LE-NEXT: blr
391 ;
392 ; CHECK-BE-LABEL: f6:
393 ; CHECK-BE: # %bb.0: # %entry
394 ; CHECK-BE-NEXT: mr r0, r1
395 ; CHECK-BE-NEXT: .cfi_def_cfa r0, 0
396 ; CHECK-BE-NEXT: stdu r0, -64(r1)
397 ; CHECK-BE-NEXT: lis r12, 4
398 ; CHECK-BE-NEXT: ori r12, r12, 0
399 ; CHECK-BE-NEXT: mtctr r12
400 ; CHECK-BE-NEXT: .LBB6_1: # %entry
401 ; CHECK-BE-NEXT: #
402 ; CHECK-BE-NEXT: stdu r0, -4096(r1)
403 ; CHECK-BE-NEXT: bdnz .LBB6_1
404 ; CHECK-BE-NEXT: # %bb.2: # %entry
405 ; CHECK-BE-NEXT: .cfi_def_cfa_register r1
406 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 1073741888
407 ; CHECK-BE-NEXT: li r3, 3
408 ; CHECK-BE-NEXT: stb r3, 64(r1)
409 ; CHECK-BE-NEXT: lbz r3, 64(r1)
410 ; CHECK-BE-NEXT: ld r1, 0(r1)
411 ; CHECK-BE-NEXT: blr
412 ;
413 ; CHECK-32-LABEL: f6:
414 ; CHECK-32: # %bb.0: # %entry
415 ; CHECK-32-NEXT: mr r0, r1
416 ; CHECK-32-NEXT: .cfi_def_cfa r0, 0
417 ; CHECK-32-NEXT: stwu r0, -16(r1)
418 ; CHECK-32-NEXT: lis r12, 4
419 ; CHECK-32-NEXT: ori r12, r12, 0
420 ; CHECK-32-NEXT: mtctr r12
421 ; CHECK-32-NEXT: .LBB6_1: # %entry
422 ; CHECK-32-NEXT: #
423 ; CHECK-32-NEXT: stwu r0, -4096(r1)
424 ; CHECK-32-NEXT: bdnz .LBB6_1
425 ; CHECK-32-NEXT: # %bb.2: # %entry
426 ; CHECK-32-NEXT: .cfi_def_cfa_register r1
427 ; CHECK-32-NEXT: sub r0, r1, r0
428 ; CHECK-32-NEXT: sub r0, r1, r0
429 ; CHECK-32-NEXT: .cfi_def_cfa_offset 1073741840
430 ; CHECK-32-NEXT: li r3, 3
431 ; CHECK-32-NEXT: stb r3, 16(r1)
432 ; CHECK-32-NEXT: mr r0, r31
433 ; CHECK-32-NEXT: lbz r3, 16(r1)
434 ; CHECK-32-NEXT: lwz r31, 0(r1)
435 ; CHECK-32-NEXT: mr r1, r31
436 ; CHECK-32-NEXT: mr r31, r0
437 ; CHECK-32-NEXT: blr
438 entry:
439 %a = alloca i8, i64 1073741824
440 %b = getelementptr inbounds i8, ptr %a, i64 63
441 store volatile i8 3, ptr %a
442 %c = load volatile i8, ptr %a
443 ret i8 %c
444 }
446 define i8 @f7() #0 "stack-probe-size"="65536" {
447 ; CHECK-LE-LABEL: f7:
448 ; CHECK-LE: # %bb.0: # %entry
449 ; CHECK-LE-NEXT: mr r0, r1
450 ; CHECK-LE-NEXT: .cfi_def_cfa r0, 0
451 ; CHECK-LE-NEXT: lis r12, -1
452 ; CHECK-LE-NEXT: ori r12, r12, 13776
453 ; CHECK-LE-NEXT: stdux r0, r1, r12
454 ; CHECK-LE-NEXT: li r12, 15258
455 ; CHECK-LE-NEXT: mtctr r12
456 ; CHECK-LE-NEXT: lis r12, -1
457 ; CHECK-LE-NEXT: ori r12, r12, 0
458 ; CHECK-LE-NEXT: .LBB7_1: # %entry
459 ; CHECK-LE-NEXT: #
460 ; CHECK-LE-NEXT: stdux r0, r1, r12
461 ; CHECK-LE-NEXT: bdnz .LBB7_1
462 ; CHECK-LE-NEXT: # %bb.2: # %entry
463 ; CHECK-LE-NEXT: .cfi_def_cfa_register r1
464 ; CHECK-LE-NEXT: .cfi_def_cfa_offset 1000000048
465 ; CHECK-LE-NEXT: li r3, 3
466 ; CHECK-LE-NEXT: stb r3, 41(r1)
467 ; CHECK-LE-NEXT: lbz r3, 41(r1)
468 ; CHECK-LE-NEXT: ld r1, 0(r1)
469 ; CHECK-LE-NEXT: blr
470 ;
471 ; CHECK-BE-LABEL: f7:
472 ; CHECK-BE: # %bb.0: # %entry
473 ; CHECK-BE-NEXT: mr r0, r1
474 ; CHECK-BE-NEXT: .cfi_def_cfa r0, 0
475 ; CHECK-BE-NEXT: lis r12, -1
476 ; CHECK-BE-NEXT: ori r12, r12, 13760
477 ; CHECK-BE-NEXT: stdux r0, r1, r12
478 ; CHECK-BE-NEXT: li r12, 15258
479 ; CHECK-BE-NEXT: mtctr r12
480 ; CHECK-BE-NEXT: lis r12, -1
481 ; CHECK-BE-NEXT: ori r12, r12, 0
482 ; CHECK-BE-NEXT: .LBB7_1: # %entry
483 ; CHECK-BE-NEXT: #
484 ; CHECK-BE-NEXT: stdux r0, r1, r12
485 ; CHECK-BE-NEXT: bdnz .LBB7_1
486 ; CHECK-BE-NEXT: # %bb.2: # %entry
487 ; CHECK-BE-NEXT: .cfi_def_cfa_register r1
488 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 1000000064
489 ; CHECK-BE-NEXT: li r3, 3
490 ; CHECK-BE-NEXT: stb r3, 57(r1)
491 ; CHECK-BE-NEXT: lbz r3, 57(r1)
492 ; CHECK-BE-NEXT: ld r1, 0(r1)
493 ; CHECK-BE-NEXT: blr
494 ;
495 ; CHECK-32-LABEL: f7:
496 ; CHECK-32: # %bb.0: # %entry
497 ; CHECK-32-NEXT: mr r0, r1
498 ; CHECK-32-NEXT: .cfi_def_cfa r0, 0
499 ; CHECK-32-NEXT: lis r12, -1
500 ; CHECK-32-NEXT: ori r12, r12, 13808
501 ; CHECK-32-NEXT: stwux r0, r1, r12
502 ; CHECK-32-NEXT: li r12, 15258
503 ; CHECK-32-NEXT: mtctr r12
504 ; CHECK-32-NEXT: lis r12, -1
505 ; CHECK-32-NEXT: ori r12, r12, 0
506 ; CHECK-32-NEXT: .LBB7_1: # %entry
507 ; CHECK-32-NEXT: #
508 ; CHECK-32-NEXT: stwux r0, r1, r12
509 ; CHECK-32-NEXT: bdnz .LBB7_1
510 ; CHECK-32-NEXT: # %bb.2: # %entry
511 ; CHECK-32-NEXT: .cfi_def_cfa_register r1
512 ; CHECK-32-NEXT: sub r0, r1, r0
513 ; CHECK-32-NEXT: sub r0, r1, r0
514 ; CHECK-32-NEXT: .cfi_def_cfa_offset 1000000016
515 ; CHECK-32-NEXT: li r3, 3
516 ; CHECK-32-NEXT: stb r3, 9(r1)
517 ; CHECK-32-NEXT: mr r0, r31
518 ; CHECK-32-NEXT: lbz r3, 9(r1)
519 ; CHECK-32-NEXT: lwz r31, 0(r1)
520 ; CHECK-32-NEXT: mr r1, r31
521 ; CHECK-32-NEXT: mr r31, r0
522 ; CHECK-32-NEXT: blr
523 entry:
524 %a = alloca i8, i64 1000000007
525 %b = getelementptr inbounds i8, ptr %a, i64 101
526 store volatile i8 3, ptr %a
527 %c = load volatile i8, ptr %a
528 ret i8 %c
529 }
531 ; alloca + align < probe_size
532 define i32 @f8(i64 %i) local_unnamed_addr #0 {
533 ; CHECK-LE-LABEL: f8:
534 ; CHECK-LE: # %bb.0:
535 ; CHECK-LE-NEXT: clrldi r0, r1, 58
536 ; CHECK-LE-NEXT: std r30, -16(r1)
537 ; CHECK-LE-NEXT: mr r30, r1
538 ; CHECK-LE-NEXT: subfic r0, r0, -896
539 ; CHECK-LE-NEXT: stdux r1, r1, r0
540 ; CHECK-LE-NEXT: .cfi_def_cfa_register r30
541 ; CHECK-LE-NEXT: .cfi_offset r30, -16
542 ; CHECK-LE-NEXT: sldi r3, r3, 2
543 ; CHECK-LE-NEXT: addi r4, r1, 64
544 ; CHECK-LE-NEXT: li r5, 1
545 ; CHECK-LE-NEXT: stwx r5, r4, r3
546 ; CHECK-LE-NEXT: lwz r3, 64(r1)
547 ; CHECK-LE-NEXT: mr r1, r30
548 ; CHECK-LE-NEXT: ld r30, -16(r1)
549 ; CHECK-LE-NEXT: blr
550 ;
551 ; CHECK-BE-LABEL: f8:
552 ; CHECK-BE: # %bb.0:
553 ; CHECK-BE-NEXT: clrldi r0, r1, 58
554 ; CHECK-BE-NEXT: std r30, -16(r1)
555 ; CHECK-BE-NEXT: mr r30, r1
556 ; CHECK-BE-NEXT: subfic r0, r0, -896
557 ; CHECK-BE-NEXT: stdux r1, r1, r0
558 ; CHECK-BE-NEXT: .cfi_def_cfa_register r30
559 ; CHECK-BE-NEXT: .cfi_offset r30, -16
560 ; CHECK-BE-NEXT: addi r4, r1, 64
561 ; CHECK-BE-NEXT: li r5, 1
562 ; CHECK-BE-NEXT: sldi r3, r3, 2
563 ; CHECK-BE-NEXT: stwx r5, r4, r3
564 ; CHECK-BE-NEXT: lwz r3, 64(r1)
565 ; CHECK-BE-NEXT: mr r1, r30
566 ; CHECK-BE-NEXT: ld r30, -16(r1)
567 ; CHECK-BE-NEXT: blr
568 ;
569 ; CHECK-32-LABEL: f8:
570 ; CHECK-32: # %bb.0:
571 ; CHECK-32-NEXT: clrlwi r0, r1, 26
572 ; CHECK-32-NEXT: subfic r0, r0, -896
573 ; CHECK-32-NEXT: stwux r1, r1, r0
574 ; CHECK-32-NEXT: sub r0, r1, r0
575 ; CHECK-32-NEXT: addic r0, r0, -8
576 ; CHECK-32-NEXT: stwx r30, 0, r0
577 ; CHECK-32-NEXT: addic r30, r0, 8
578 ; CHECK-32-NEXT: .cfi_def_cfa_register r30
579 ; CHECK-32-NEXT: .cfi_offset r30, -8
580 ; CHECK-32-NEXT: addi r3, r1, 64
581 ; CHECK-32-NEXT: li r5, 1
582 ; CHECK-32-NEXT: slwi r4, r4, 2
583 ; CHECK-32-NEXT: stwx r5, r3, r4
584 ; CHECK-32-NEXT: mr r0, r31
585 ; CHECK-32-NEXT: lwz r3, 64(r1)
586 ; CHECK-32-NEXT: lwz r31, 0(r1)
587 ; CHECK-32-NEXT: lwz r30, -8(r31)
588 ; CHECK-32-NEXT: mr r1, r31
589 ; CHECK-32-NEXT: mr r31, r0
590 ; CHECK-32-NEXT: blr
591 %a = alloca i32, i32 200, align 64
592 %b = getelementptr inbounds i32, ptr %a, i64 %i
593 store volatile i32 1, ptr %b
594 %c = load volatile i32, ptr %a
595 ret i32 %c
596 }
598 ; alloca > probe_size, align > probe_size
599 define i32 @f9(i64 %i) local_unnamed_addr #0 {
600 ; CHECK-LE-LABEL: f9:
601 ; CHECK-LE: # %bb.0:
602 ; CHECK-LE-NEXT: clrldi r12, r1, 53
603 ; CHECK-LE-NEXT: std r30, -16(r1)
604 ; CHECK-LE-NEXT: mr r30, r1
605 ; CHECK-LE-NEXT: sub r0, r1, r12
606 ; CHECK-LE-NEXT: li r12, -10240
607 ; CHECK-LE-NEXT: add r0, r12, r0
608 ; CHECK-LE-NEXT: sub r12, r0, r1
609 ; CHECK-LE-NEXT: cmpdi r12, -4096
610 ; CHECK-LE-NEXT: bge cr0, .LBB9_2
611 ; CHECK-LE-NEXT: .LBB9_1:
612 ; CHECK-LE-NEXT: stdu r30, -4096(r1)
613 ; CHECK-LE-NEXT: addi r12, r12, 4096
614 ; CHECK-LE-NEXT: cmpdi r12, -4096
615 ; CHECK-LE-NEXT: blt cr0, .LBB9_1
616 ; CHECK-LE-NEXT: .LBB9_2:
617 ; CHECK-LE-NEXT: stdux r30, r1, r12
618 ; CHECK-LE-NEXT: mr r0, r30
619 ; CHECK-LE-NEXT: .cfi_def_cfa_register r0
620 ; CHECK-LE-NEXT: .cfi_def_cfa_register r30
621 ; CHECK-LE-NEXT: .cfi_offset r30, -16
622 ; CHECK-LE-NEXT: sldi r3, r3, 2
623 ; CHECK-LE-NEXT: addi r4, r1, 2048
624 ; CHECK-LE-NEXT: li r5, 1
625 ; CHECK-LE-NEXT: stwx r5, r4, r3
626 ; CHECK-LE-NEXT: lwz r3, 2048(r1)
627 ; CHECK-LE-NEXT: mr r1, r30
628 ; CHECK-LE-NEXT: ld r30, -16(r1)
629 ; CHECK-LE-NEXT: blr
630 ;
631 ; CHECK-BE-LABEL: f9:
632 ; CHECK-BE: # %bb.0:
633 ; CHECK-BE-NEXT: clrldi r12, r1, 53
634 ; CHECK-BE-NEXT: std r30, -16(r1)
635 ; CHECK-BE-NEXT: mr r30, r1
636 ; CHECK-BE-NEXT: sub r0, r1, r12
637 ; CHECK-BE-NEXT: li r12, -10240
638 ; CHECK-BE-NEXT: add r0, r12, r0
639 ; CHECK-BE-NEXT: sub r12, r0, r1
640 ; CHECK-BE-NEXT: cmpdi r12, -4096
641 ; CHECK-BE-NEXT: bge cr0, .LBB9_2
642 ; CHECK-BE-NEXT: .LBB9_1:
643 ; CHECK-BE-NEXT: stdu r30, -4096(r1)
644 ; CHECK-BE-NEXT: addi r12, r12, 4096
645 ; CHECK-BE-NEXT: cmpdi r12, -4096
646 ; CHECK-BE-NEXT: blt cr0, .LBB9_1
647 ; CHECK-BE-NEXT: .LBB9_2:
648 ; CHECK-BE-NEXT: stdux r30, r1, r12
649 ; CHECK-BE-NEXT: mr r0, r30
650 ; CHECK-BE-NEXT: .cfi_def_cfa_register r0
651 ; CHECK-BE-NEXT: .cfi_def_cfa_register r30
652 ; CHECK-BE-NEXT: .cfi_offset r30, -16
653 ; CHECK-BE-NEXT: addi r4, r1, 2048
654 ; CHECK-BE-NEXT: li r5, 1
655 ; CHECK-BE-NEXT: sldi r3, r3, 2
656 ; CHECK-BE-NEXT: stwx r5, r4, r3
657 ; CHECK-BE-NEXT: lwz r3, 2048(r1)
658 ; CHECK-BE-NEXT: mr r1, r30
659 ; CHECK-BE-NEXT: ld r30, -16(r1)
660 ; CHECK-BE-NEXT: blr
661 ;
662 ; CHECK-32-LABEL: f9:
663 ; CHECK-32: # %bb.0:
664 ; CHECK-32-NEXT: clrlwi r12, r1, 21
665 ; CHECK-32-NEXT: sub r0, r1, r12
666 ; CHECK-32-NEXT: li r12, -10240
667 ; CHECK-32-NEXT: add r0, r12, r0
668 ; CHECK-32-NEXT: sub r12, r0, r1
669 ; CHECK-32-NEXT: mr r0, r1
670 ; CHECK-32-NEXT: cmpwi r12, -4096
671 ; CHECK-32-NEXT: bge cr0, .LBB9_2
672 ; CHECK-32-NEXT: .LBB9_1:
673 ; CHECK-32-NEXT: stwu r0, -4096(r1)
674 ; CHECK-32-NEXT: addi r12, r12, 4096
675 ; CHECK-32-NEXT: cmpwi r12, -4096
676 ; CHECK-32-NEXT: blt cr0, .LBB9_1
677 ; CHECK-32-NEXT: .LBB9_2:
678 ; CHECK-32-NEXT: stwux r0, r1, r12
679 ; CHECK-32-NEXT: .cfi_def_cfa_register r0
680 ; CHECK-32-NEXT: sub r0, r1, r0
681 ; CHECK-32-NEXT: sub r0, r1, r0
682 ; CHECK-32-NEXT: addic r0, r0, -8
683 ; CHECK-32-NEXT: stwx r30, 0, r0
684 ; CHECK-32-NEXT: addic r30, r0, 8
685 ; CHECK-32-NEXT: .cfi_def_cfa_register r30
686 ; CHECK-32-NEXT: .cfi_offset r30, -8
687 ; CHECK-32-NEXT: addi r3, r1, 2048
688 ; CHECK-32-NEXT: li r5, 1
689 ; CHECK-32-NEXT: slwi r4, r4, 2
690 ; CHECK-32-NEXT: stwx r5, r3, r4
691 ; CHECK-32-NEXT: mr r0, r31
692 ; CHECK-32-NEXT: lwz r3, 2048(r1)
693 ; CHECK-32-NEXT: lwz r31, 0(r1)
694 ; CHECK-32-NEXT: lwz r30, -8(r31)
695 ; CHECK-32-NEXT: mr r1, r31
696 ; CHECK-32-NEXT: mr r31, r0
697 ; CHECK-32-NEXT: blr
698 %a = alloca i32, i32 2000, align 2048
699 %b = getelementptr inbounds i32, ptr %a, i64 %i
700 store volatile i32 1, ptr %b
701 %c = load volatile i32, ptr %a
702 ret i32 %c
703 }
705 ; alloca < probe_size, align < probe_size, alloca + align > probe_size
706 define i32 @f10(i64 %i) local_unnamed_addr #0 {
707 ; CHECK-LE-LABEL: f10:
708 ; CHECK-LE: # %bb.0:
709 ; CHECK-LE-NEXT: clrldi r12, r1, 54
710 ; CHECK-LE-NEXT: std r30, -16(r1)
711 ; CHECK-LE-NEXT: mr r30, r1
712 ; CHECK-LE-NEXT: sub r0, r1, r12
713 ; CHECK-LE-NEXT: li r12, -5120
714 ; CHECK-LE-NEXT: add r0, r12, r0
715 ; CHECK-LE-NEXT: sub r12, r0, r1
716 ; CHECK-LE-NEXT: cmpdi r12, -4096
717 ; CHECK-LE-NEXT: bge cr0, .LBB10_2
718 ; CHECK-LE-NEXT: .LBB10_1:
719 ; CHECK-LE-NEXT: stdu r30, -4096(r1)
720 ; CHECK-LE-NEXT: addi r12, r12, 4096
721 ; CHECK-LE-NEXT: cmpdi r12, -4096
722 ; CHECK-LE-NEXT: blt cr0, .LBB10_1
723 ; CHECK-LE-NEXT: .LBB10_2:
724 ; CHECK-LE-NEXT: stdux r30, r1, r12
725 ; CHECK-LE-NEXT: mr r0, r30
726 ; CHECK-LE-NEXT: .cfi_def_cfa_register r0
727 ; CHECK-LE-NEXT: .cfi_def_cfa_register r30
728 ; CHECK-LE-NEXT: .cfi_offset r30, -16
729 ; CHECK-LE-NEXT: sldi r3, r3, 2
730 ; CHECK-LE-NEXT: addi r4, r1, 1024
731 ; CHECK-LE-NEXT: li r5, 1
732 ; CHECK-LE-NEXT: stwx r5, r4, r3
733 ; CHECK-LE-NEXT: lwz r3, 1024(r1)
734 ; CHECK-LE-NEXT: mr r1, r30
735 ; CHECK-LE-NEXT: ld r30, -16(r1)
736 ; CHECK-LE-NEXT: blr
737 ;
738 ; CHECK-BE-LABEL: f10:
739 ; CHECK-BE: # %bb.0:
740 ; CHECK-BE-NEXT: clrldi r12, r1, 54
741 ; CHECK-BE-NEXT: std r30, -16(r1)
742 ; CHECK-BE-NEXT: mr r30, r1
743 ; CHECK-BE-NEXT: sub r0, r1, r12
744 ; CHECK-BE-NEXT: li r12, -5120
745 ; CHECK-BE-NEXT: add r0, r12, r0
746 ; CHECK-BE-NEXT: sub r12, r0, r1
747 ; CHECK-BE-NEXT: cmpdi r12, -4096
748 ; CHECK-BE-NEXT: bge cr0, .LBB10_2
749 ; CHECK-BE-NEXT: .LBB10_1:
750 ; CHECK-BE-NEXT: stdu r30, -4096(r1)
751 ; CHECK-BE-NEXT: addi r12, r12, 4096
752 ; CHECK-BE-NEXT: cmpdi r12, -4096
753 ; CHECK-BE-NEXT: blt cr0, .LBB10_1
754 ; CHECK-BE-NEXT: .LBB10_2:
755 ; CHECK-BE-NEXT: stdux r30, r1, r12
756 ; CHECK-BE-NEXT: mr r0, r30
757 ; CHECK-BE-NEXT: .cfi_def_cfa_register r0
758 ; CHECK-BE-NEXT: .cfi_def_cfa_register r30
759 ; CHECK-BE-NEXT: .cfi_offset r30, -16
760 ; CHECK-BE-NEXT: addi r4, r1, 1024
761 ; CHECK-BE-NEXT: li r5, 1
762 ; CHECK-BE-NEXT: sldi r3, r3, 2
763 ; CHECK-BE-NEXT: stwx r5, r4, r3
764 ; CHECK-BE-NEXT: lwz r3, 1024(r1)
765 ; CHECK-BE-NEXT: mr r1, r30
766 ; CHECK-BE-NEXT: ld r30, -16(r1)
767 ; CHECK-BE-NEXT: blr
768 ;
769 ; CHECK-32-LABEL: f10:
770 ; CHECK-32: # %bb.0:
771 ; CHECK-32-NEXT: clrlwi r12, r1, 22
772 ; CHECK-32-NEXT: sub r0, r1, r12
773 ; CHECK-32-NEXT: li r12, -5120
774 ; CHECK-32-NEXT: add r0, r12, r0
775 ; CHECK-32-NEXT: sub r12, r0, r1
776 ; CHECK-32-NEXT: mr r0, r1
777 ; CHECK-32-NEXT: cmpwi r12, -4096
778 ; CHECK-32-NEXT: bge cr0, .LBB10_2
779 ; CHECK-32-NEXT: .LBB10_1:
780 ; CHECK-32-NEXT: stwu r0, -4096(r1)
781 ; CHECK-32-NEXT: addi r12, r12, 4096
782 ; CHECK-32-NEXT: cmpwi r12, -4096
783 ; CHECK-32-NEXT: blt cr0, .LBB10_1
784 ; CHECK-32-NEXT: .LBB10_2:
785 ; CHECK-32-NEXT: stwux r0, r1, r12
786 ; CHECK-32-NEXT: .cfi_def_cfa_register r0
787 ; CHECK-32-NEXT: sub r0, r1, r0
788 ; CHECK-32-NEXT: sub r0, r1, r0
789 ; CHECK-32-NEXT: addic r0, r0, -8
790 ; CHECK-32-NEXT: stwx r30, 0, r0
791 ; CHECK-32-NEXT: addic r30, r0, 8
792 ; CHECK-32-NEXT: .cfi_def_cfa_register r30
793 ; CHECK-32-NEXT: .cfi_offset r30, -8
794 ; CHECK-32-NEXT: addi r3, r1, 1024
795 ; CHECK-32-NEXT: li r5, 1
796 ; CHECK-32-NEXT: slwi r4, r4, 2
797 ; CHECK-32-NEXT: stwx r5, r3, r4
798 ; CHECK-32-NEXT: mr r0, r31
799 ; CHECK-32-NEXT: lwz r3, 1024(r1)
800 ; CHECK-32-NEXT: lwz r31, 0(r1)
801 ; CHECK-32-NEXT: lwz r30, -8(r31)
802 ; CHECK-32-NEXT: mr r1, r31
803 ; CHECK-32-NEXT: mr r31, r0
804 ; CHECK-32-NEXT: blr
805 %a = alloca i32, i32 1000, align 1024
806 %b = getelementptr inbounds i32, ptr %a, i64 %i
807 store volatile i32 1, ptr %b
808 %c = load volatile i32, ptr %a
809 ret i32 %c
810 }
812 define void @f11(i32 %vla_size, i64 %i) #0 {
813 ; CHECK-LE-LABEL: f11:
814 ; CHECK-LE: # %bb.0:
815 ; CHECK-LE-NEXT: clrldi r12, r1, 49
816 ; CHECK-LE-NEXT: std r31, -8(r1)
817 ; CHECK-LE-NEXT: std r30, -16(r1)
818 ; CHECK-LE-NEXT: mr r30, r1
819 ; CHECK-LE-NEXT: sub r0, r1, r12
820 ; CHECK-LE-NEXT: lis r12, -2
821 ; CHECK-LE-NEXT: ori r12, r12, 32768
822 ; CHECK-LE-NEXT: add r0, r12, r0
823 ; CHECK-LE-NEXT: sub r12, r0, r1
824 ; CHECK-LE-NEXT: cmpdi r12, -4096
825 ; CHECK-LE-NEXT: bge cr0, .LBB11_2
826 ; CHECK-LE-NEXT: .LBB11_1:
827 ; CHECK-LE-NEXT: stdu r30, -4096(r1)
828 ; CHECK-LE-NEXT: addi r12, r12, 4096
829 ; CHECK-LE-NEXT: cmpdi r12, -4096
830 ; CHECK-LE-NEXT: blt cr0, .LBB11_1
831 ; CHECK-LE-NEXT: .LBB11_2:
832 ; CHECK-LE-NEXT: stdux r30, r1, r12
833 ; CHECK-LE-NEXT: mr r0, r30
834 ; CHECK-LE-NEXT: .cfi_def_cfa_register r0
835 ; CHECK-LE-NEXT: .cfi_def_cfa_register r30
836 ; CHECK-LE-NEXT: .cfi_offset r31, -8
837 ; CHECK-LE-NEXT: .cfi_offset r30, -16
838 ; CHECK-LE-NEXT: clrldi r3, r3, 32
839 ; CHECK-LE-NEXT: lis r5, 1
840 ; CHECK-LE-NEXT: mr r31, r1
841 ; CHECK-LE-NEXT: li r6, 1
842 ; CHECK-LE-NEXT: sldi r4, r4, 2
843 ; CHECK-LE-NEXT: addi r3, r3, 15
844 ; CHECK-LE-NEXT: ori r5, r5, 0
845 ; CHECK-LE-NEXT: rldicl r3, r3, 60, 4
846 ; CHECK-LE-NEXT: add r5, r31, r5
847 ; CHECK-LE-NEXT: rldicl r3, r3, 4, 31
848 ; CHECK-LE-NEXT: stwx r6, r5, r4
849 ; CHECK-LE-NEXT: li r4, -32768
850 ; CHECK-LE-NEXT: li r6, -4096
851 ; CHECK-LE-NEXT: neg r5, r3
852 ; CHECK-LE-NEXT: ld r3, 0(r1)
853 ; CHECK-LE-NEXT: and r4, r5, r4
854 ; CHECK-LE-NEXT: mr r5, r4
855 ; CHECK-LE-NEXT: divd r7, r5, r6
856 ; CHECK-LE-NEXT: add r4, r1, r5
857 ; CHECK-LE-NEXT: mulld r6, r7, r6
858 ; CHECK-LE-NEXT: sub r5, r5, r6
859 ; CHECK-LE-NEXT: stdux r3, r1, r5
860 ; CHECK-LE-NEXT: cmpd r1, r4
861 ; CHECK-LE-NEXT: beq cr0, .LBB11_4
862 ; CHECK-LE-NEXT: .LBB11_3:
863 ; CHECK-LE-NEXT: stdu r3, -4096(r1)
864 ; CHECK-LE-NEXT: cmpd r1, r4
865 ; CHECK-LE-NEXT: bne cr0, .LBB11_3
866 ; CHECK-LE-NEXT: .LBB11_4:
867 ; CHECK-LE-NEXT: addi r3, r1, -32768
868 ; CHECK-LE-NEXT: lbz r3, 0(r3)
869 ; CHECK-LE-NEXT: mr r1, r30
870 ; CHECK-LE-NEXT: ld r31, -8(r1)
871 ; CHECK-LE-NEXT: ld r30, -16(r1)
872 ; CHECK-LE-NEXT: blr
873 ;
874 ; CHECK-BE-LABEL: f11:
875 ; CHECK-BE: # %bb.0:
876 ; CHECK-BE-NEXT: clrldi r12, r1, 49
877 ; CHECK-BE-NEXT: std r31, -8(r1)
878 ; CHECK-BE-NEXT: std r30, -16(r1)
879 ; CHECK-BE-NEXT: mr r30, r1
880 ; CHECK-BE-NEXT: sub r0, r1, r12
881 ; CHECK-BE-NEXT: lis r12, -2
882 ; CHECK-BE-NEXT: ori r12, r12, 32768
883 ; CHECK-BE-NEXT: add r0, r12, r0
884 ; CHECK-BE-NEXT: sub r12, r0, r1
885 ; CHECK-BE-NEXT: cmpdi r12, -4096
886 ; CHECK-BE-NEXT: bge cr0, .LBB11_2
887 ; CHECK-BE-NEXT: .LBB11_1:
888 ; CHECK-BE-NEXT: stdu r30, -4096(r1)
889 ; CHECK-BE-NEXT: addi r12, r12, 4096
890 ; CHECK-BE-NEXT: cmpdi r12, -4096
891 ; CHECK-BE-NEXT: blt cr0, .LBB11_1
892 ; CHECK-BE-NEXT: .LBB11_2:
893 ; CHECK-BE-NEXT: stdux r30, r1, r12
894 ; CHECK-BE-NEXT: mr r0, r30
895 ; CHECK-BE-NEXT: .cfi_def_cfa_register r0
896 ; CHECK-BE-NEXT: .cfi_def_cfa_register r30
897 ; CHECK-BE-NEXT: .cfi_offset r31, -8
898 ; CHECK-BE-NEXT: .cfi_offset r30, -16
899 ; CHECK-BE-NEXT: clrldi r3, r3, 32
900 ; CHECK-BE-NEXT: lis r5, 1
901 ; CHECK-BE-NEXT: addi r3, r3, 15
902 ; CHECK-BE-NEXT: mr r31, r1
903 ; CHECK-BE-NEXT: ori r5, r5, 0
904 ; CHECK-BE-NEXT: rldicl r3, r3, 60, 4
905 ; CHECK-BE-NEXT: add r5, r31, r5
906 ; CHECK-BE-NEXT: sldi r4, r4, 2
907 ; CHECK-BE-NEXT: li r6, 1
908 ; CHECK-BE-NEXT: rldicl r3, r3, 4, 31
909 ; CHECK-BE-NEXT: stwx r6, r5, r4
910 ; CHECK-BE-NEXT: neg r7, r3
911 ; CHECK-BE-NEXT: li r4, -32768
912 ; CHECK-BE-NEXT: and r4, r7, r4
913 ; CHECK-BE-NEXT: ld r3, 0(r1)
914 ; CHECK-BE-NEXT: mr r7, r4
915 ; CHECK-BE-NEXT: li r4, -4096
916 ; CHECK-BE-NEXT: divd r5, r7, r4
917 ; CHECK-BE-NEXT: mulld r4, r5, r4
918 ; CHECK-BE-NEXT: sub r5, r7, r4
919 ; CHECK-BE-NEXT: add r4, r1, r7
920 ; CHECK-BE-NEXT: stdux r3, r1, r5
921 ; CHECK-BE-NEXT: cmpd r1, r4
922 ; CHECK-BE-NEXT: beq cr0, .LBB11_4
923 ; CHECK-BE-NEXT: .LBB11_3:
924 ; CHECK-BE-NEXT: stdu r3, -4096(r1)
925 ; CHECK-BE-NEXT: cmpd r1, r4
926 ; CHECK-BE-NEXT: bne cr0, .LBB11_3
927 ; CHECK-BE-NEXT: .LBB11_4:
928 ; CHECK-BE-NEXT: addi r3, r1, -32768
929 ; CHECK-BE-NEXT: lbz r3, 0(r3)
930 ; CHECK-BE-NEXT: mr r1, r30
931 ; CHECK-BE-NEXT: ld r31, -8(r1)
932 ; CHECK-BE-NEXT: ld r30, -16(r1)
933 ; CHECK-BE-NEXT: blr
934 ;
935 ; CHECK-32-LABEL: f11:
936 ; CHECK-32: # %bb.0:
937 ; CHECK-32-NEXT: clrlwi r12, r1, 17
938 ; CHECK-32-NEXT: sub r0, r1, r12
939 ; CHECK-32-NEXT: lis r12, -2
940 ; CHECK-32-NEXT: ori r12, r12, 32768
941 ; CHECK-32-NEXT: add r0, r12, r0
942 ; CHECK-32-NEXT: sub r12, r0, r1
943 ; CHECK-32-NEXT: mr r0, r1
944 ; CHECK-32-NEXT: cmpwi r12, -4096
945 ; CHECK-32-NEXT: bge cr0, .LBB11_2
946 ; CHECK-32-NEXT: .LBB11_1:
947 ; CHECK-32-NEXT: stwu r0, -4096(r1)
948 ; CHECK-32-NEXT: addi r12, r12, 4096
949 ; CHECK-32-NEXT: cmpwi r12, -4096
950 ; CHECK-32-NEXT: blt cr0, .LBB11_1
951 ; CHECK-32-NEXT: .LBB11_2:
952 ; CHECK-32-NEXT: stwux r0, r1, r12
953 ; CHECK-32-NEXT: .cfi_def_cfa_register r0
954 ; CHECK-32-NEXT: sub r0, r1, r0
955 ; CHECK-32-NEXT: sub r0, r1, r0
956 ; CHECK-32-NEXT: addic r0, r0, -4
957 ; CHECK-32-NEXT: stwx r31, 0, r0
958 ; CHECK-32-NEXT: addic r0, r0, -4
959 ; CHECK-32-NEXT: stwx r30, 0, r0
960 ; CHECK-32-NEXT: addic r30, r0, 8
961 ; CHECK-32-NEXT: .cfi_def_cfa_register r30
962 ; CHECK-32-NEXT: .cfi_offset r31, -4
963 ; CHECK-32-NEXT: .cfi_offset r30, -8
964 ; CHECK-32-NEXT: lis r4, 1
965 ; CHECK-32-NEXT: mr r31, r1
966 ; CHECK-32-NEXT: ori r4, r4, 0
967 ; CHECK-32-NEXT: addi r3, r3, 15
968 ; CHECK-32-NEXT: add r4, r31, r4
969 ; CHECK-32-NEXT: li r5, 1
970 ; CHECK-32-NEXT: slwi r6, r6, 2
971 ; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27
972 ; CHECK-32-NEXT: neg r7, r3
973 ; CHECK-32-NEXT: stwx r5, r4, r6
974 ; CHECK-32-NEXT: li r4, -32768
975 ; CHECK-32-NEXT: and r4, r7, r4
976 ; CHECK-32-NEXT: lwz r3, 0(r1)
977 ; CHECK-32-NEXT: mr r7, r4
978 ; CHECK-32-NEXT: li r4, -4096
979 ; CHECK-32-NEXT: divw r5, r7, r4
980 ; CHECK-32-NEXT: mullw r4, r5, r4
981 ; CHECK-32-NEXT: sub r5, r7, r4
982 ; CHECK-32-NEXT: add r4, r1, r7
983 ; CHECK-32-NEXT: stwux r3, r1, r5
984 ; CHECK-32-NEXT: cmpw r1, r4
985 ; CHECK-32-NEXT: beq cr0, .LBB11_4
986 ; CHECK-32-NEXT: .LBB11_3:
987 ; CHECK-32-NEXT: stwu r3, -4096(r1)
988 ; CHECK-32-NEXT: cmpw r1, r4
989 ; CHECK-32-NEXT: bne cr0, .LBB11_3
990 ; CHECK-32-NEXT: .LBB11_4:
991 ; CHECK-32-NEXT: addi r3, r1, -32768
992 ; CHECK-32-NEXT: lbz r3, 0(r3)
993 ; CHECK-32-NEXT: lwz r31, 0(r1)
994 ; CHECK-32-NEXT: lwz r0, -4(r31)
995 ; CHECK-32-NEXT: lwz r30, -8(r31)
996 ; CHECK-32-NEXT: mr r1, r31
997 ; CHECK-32-NEXT: mr r31, r0
998 ; CHECK-32-NEXT: blr
999 %a = alloca i32, i32 4096, align 32768
1000 %b = getelementptr inbounds i32, ptr %a, i64 %i
1001 store volatile i32 1, ptr %b
1002 %1 = zext i32 %vla_size to i64
1003 %vla = alloca i8, i64 %1, align 2048
1004 %2 = load volatile i8, ptr %vla, align 2048
1005 ret void
1006 }
1008 attributes #0 = { "probe-stack"="inline-asm" }